Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip

Abstract

In an embodiment a method includes providing a growth substrate comprising a growth surface formed by a planar region having a plurality of three-dimensional surface structures on the planar region, directly applying a nucleation layer of oxygen-containing AlN to the growth surface and growing a nitride-based semiconductor layer sequence on the nucleation layer, wherein growing the semiconductor layer sequence includes selectively growing the semiconductor layer sequence upwards from the planar region such that a growth of the semiconductor layer sequence on surfaces of the three-dimensional surface structures is reduced or non-existent compared to a growth on the planar region, wherein the nucleation layer is applied onto both the planar region and the three-dimensional surface structures of the growth surface, and wherein a selectivity of the growth of the semiconductor layer sequence on the planar region is targetedly adjusted by an oxygen content of the nucleation layer.

Claims

1. A method for producing an electronic semiconductor chip, the method comprising: providing a growth substrate comprising a growth surface formed by a planar region having a plurality of three-dimensional surface structures on the planar region; directly applying a nucleation layer of oxygen-containing AlN to the growth surface; and growing a nitride-based semiconductor layer sequence on the nucleation layer, wherein growing the semiconductor layer sequence comprises selectively growing the semiconductor layer sequence upwards from the planar region such that a growth of the semiconductor layer sequence on surfaces of the three-dimensional surface structures is reduced or non-existent compared to a growth on the planar region, wherein the nucleation layer is applied onto both the planar region and the three-dimensional surface structures of the growth surface, and wherein a selectivity of the growth of the semiconductor layer sequence on the planar region is targetedly adjusted by an oxygen content of the nucleation layer.

2. The method according to claim 1, wherein the three-dimensional surface structures are formed by grooves projecting into the growth substrate.

3. The method according to claim 2, wherein the grooves are conical or pyramidal grooves.

4. The method according to claim 2, wherein the grooves have a round cross-section or a polygonal cross-section when the growth surface is viewed from above.

5. The method according to claim 1, wherein the growth substrate is pre-conditioned in an O.sub.2 plasma such that the growth surface is terminated with oxygen.

6. The method according to claim 1, wherein the three-dimensional surface structures comprise conical or pyramidal elevations on the planar region.

7. The method according to claim 1, wherein the semiconductor chip is a light-emitting or light-detecting diode.

8. The method according to claim 1, wherein the oxygen content of the nucleation layer is more than 10.sup.19 cm.sup.−3.

9. The method according to claim 1, wherein a weight proportion of oxygen on the nucleation layer is greater than or equal to 0.01%.

10. The method according to claim 9, wherein the weight proportion of oxygen on the nucleation layer is less than or equal to 10%.

11. The method according to claim 1, wherein applying the nucleation layer comprises applying a layer of oxygen-free AlN and subsequently oxidizing this layer.

12. A method for producing an electronic semiconductor chip, the method comprising: providing a growth surface comprising a plurality of three-dimensional surface structures on a planar region; applying an oxygen-containing nucleation layer to the growth surface; and growing a nitride-based semiconductor layer sequence on the nucleation layer, wherein growing the semiconductor layer sequence comprises selectively growing the semiconductor layer sequence such that a growth of the semiconductor layer sequence on surfaces of the three-dimensional surface structures is reduced or non-existent compared to a growth on the planar region, wherein the nucleation layer is applied onto both the planar region and the three-dimensional surface structures of the growth surface, and wherein a selectivity of the growth of the semiconductor layer sequence on the planar region is adjusted by an oxygen content of the nucleation layer.

13. The method according to claim 12, wherein the nucleation layer is formed by a plurality of posts arranged next to each other, and wherein sections of a flat region as well as sections of the three-dimensional surface structures are covered by the posts.

14. The method according to claim 12, wherein the oxygen content of the nucleation layer is more than 10.sup.19 cm.sup.−3.

15. The method according to claim 12, wherein a weight proportion of oxygen on the nucleation layer is greater than or equal to 0.01%.

16. The method according to claim 12, wherein a weight proportion of oxygen on the nucleation layer is less than or equal to 10%.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Further advantages, advantageous embodiments and developments result from the embodiments described below in conjunction with the illustrations.

(2) Shown in:

(3) FIGS. 1a to 5 are schematic diagrams of steps in a method for producing an electronic semiconductor chip,

(4) FIGS. 6a to 6c are secondary electron microscope images of the growth of GaN on nucleation layers pursuant to further embodiments and

(5) FIG. 7 are measurements of wafer bows during the semiconductor growth when using different nucleation layer compositions.

(6) Identical, similar or seemingly identical elements in the embodiments and illustrations can always be furnished with the same reference signs. The elements shown and the size ratios amongst each other should not be viewed as true-to-scale; instead individual elements, such as layers, components, structural units and areas, can be shown exaggeratedly large for the sake of better representation and/or better understanding.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(7) FIGS. 1A to 5 shows steps in a method for producing an electronic semiconductor chip 100. Said electronic semiconductor chip wo is purely exemplarily designed as a light-emitting diode with an optoelectronic active layer, which is set up for generating and emitting light during operation. As an alternative to a light-emitting diode, the electronic semiconductor chip wo can, for example, also be designed as a light-detecting diode or as another semiconductor element, for example as transistor, or comprise such an element.

(8) In a first step a growth substrate 1 is provided that, as shown in FIG. 1A, comprises a growth surface 10. Said growth surface 10 is provided for the purpose of growing a semiconductor layer sequence on this one semiconductor layer sequence. The growth substrate 1 in the embodiment shown comprises aluminum oxide (Al.sub.2O.sub.3) and is preferably composed of aluminum oxide. In particular, the growth substrate 1 can be designed as aluminum oxide wafer, on which a semiconductor layer sequence is grown large-scale. The separation of the wafer with the grown semiconductor layer sequence allows a plurality of semiconductor chips to be produced.

(9) The growth surface 10 comprises a two-dimensionally designed flat region 11, on which a plurality of three-dimensionally designed surface structures 12 is arranged. In other words, the surface structures 12 project out of the plane formed by the flat region 11. The three-dimensionally designed surface structures 12 are designed as elevations, which extend upwards away from the flat region 11.

(10) FIGS. 1B and 1C show views of the growth surface 10 from growth substrates 1, in which the cross-section of the surface structures 12 is recognizable. As shown in FIG. 1B, the cross-section of the surface structures 12 can be round and in particular circular, and therefore the surface structures 12 can be designed as conical elevations. Alternatively, the surface structures 12 can also comprise an angular, for example a hexagonal cross-section, as shown in FIG. 1C, and therefore the surface structures 12 can also be designed as pyramidal elevations on the flat region 11, said flat region 11 extends between the surface structures 12 designed as elevations.

(11) The flat region 11 is more preferably formed by a crystallographic c surface or (−c) surface of the aluminum oxide, which is particularly suitable for growing nitride-based semiconductor materials. Accordingly, the surfaces of the surface structures 12 are formed by a plurality of other crystal surfaces in compliance with their orientation relative to the flat region 11.

(12) Alternatively to the embodiment shown, the growth substrate 1 can, for example, also comprise a growth surface 10 formed by silicon or silicon carbide and be correspondingly designed, for example, as silicon wafer or silicon carbide wafer. Furthermore, another possibility is that the growth substrate comprises or consists of another material stated above in the general section above.

(13) FIG. 1D shows an alternative embodiment for the growth substrate 1, in which the surface structures 12 are designed in contrast to the embodiment in FIG. 1a as grooves projecting from the flat region 11 into the growth substrate 1. Similarly to the previously described elevations, the grooves can, for example, be conical or pyramidal. The following description of the further steps refers purely exemplarily to the embodiment of the growth substrate 1 pursuant to FIG. 1 with elevations as surface structures, but the growth substrate in the steps described in the following can also be provided with grooves as surface structures 12.

(14) In a further step, as shown in FIG. 2, a nucleation layer 2 is applied to the growth surface 10. In particular, said nucleation layer 2 is applied large-scale, i.e. on the flat region 11 as well as on the three-dimensionally designed surface structures 12 of the growth surface 10. The nucleation layer 2 consists of oxygen-containing aluminum nitride, i.e. AlN:O or AlON, which is applied directly to the growth surface 10.

(15) For example, a metal-organic vapor-phase epitaxy (MOVPE) can be used to this end, in which an oxygen-containing starting material is used in addition to suitable starting materials for providing Al and N, as described in the general section. Alternatively or additionally, as described in the general section, an oxygen termination of the growth surface 10 can be implemented.

(16) As an alternative to an MOVPE method, the nucleation layer 2 can also be applied by means of a sputtering method. As described in the general section, an Al target in a nitrogen atmosphere that also additionally contains oxygen can, for example, be used to this end. Furthermore, another method described in the general section above is also possible.

(17) The amount of oxygen in the nucleation layer 2 is controlled in such a way that the oxygen content in the nucleation layer 2 equals more than 10.sup.19 cm.sup.−3. In particular, the weight proportion of the oxygen on the nucleation layer 2 can preferably be greater than or equal to 0.01%, greater than or equal to 0.1%, greater than or equal to 0.2% or greater or equal to 0.5%. Furthermore, the weight proportion of the oxygen on the nucleation layer can preferably be less than or equal to 10%, less than or equal to 5% or less than or equal to 1.5%.

(18) The thickness of the nucleation layer 2 is greater than or equal to 1 nm, greater than or equal to 5 nm, greater than or equal to 10 nm, greater than or equal to 30 nm or greater than or equal to 50 nm. Furthermore, the nucleation layer 2 can be produced with a thickness of less than or equal to 1000 nm, less than or equal to 200 nm or less than or equal to 150 nm. For example, the thickness of the nucleation layer can be approximately 100 nm.

(19) In a further step described in conjunction with FIG. 3 to 5, a nitride-based semiconductor layer sequence is grown on the nucleation layer by means of MOVPE.

(20) As shown in FIG. 3, the growth of the semiconductor layer ensues selectively from the flat region 11. As described in the general section, this is possible due to the fact that the nucleation layer 2 is not composed of AlN, as is usual in prior art, but instead additionally contains oxygen. The oxygen content of the nucleation layer 2 allows the selectivity of the growth of the semiconductor layer sequence to be adjusted on the flat region 11, and therefore the semiconductor material to be grown is predominantly grown from the flat region 11 to the nucleation layer 2 due to the desired selectivity. Conversely, little or no growth occurs on the surfaces of the three-dimensionally designed surface structures 12 due to the use of the oxygen-containing AlN nucleation layer 2, as can be seen in FIG. 3 in which an initial stage of the growth process for producing the semiconductor layer sequence 3 can be seen: a semiconductor material 30, which is applied for producing a first semiconductor layer 31 of the semiconductor layer sequence 3, grows selectively upwards from the flat region 11 on the nucleation layer 2.

(21) FIGS. 6A and 6B show secondary electron microscope images of a corresponding stage in the method when growing GaN on an oxygen-containing AlN nucleation layer. The images correspond to a view from above of the growth surface according to the view in FIG. 1C. In the event of the image in FIG. 6a, the nucleation layer was applied by means of MOVPE using an oxygen-containing starting material, whereas, in the event of the image in FIG. 6, the nucleation layer was sputtered on by adding oxygen. In both images it is very clearly recognizable that the surface structures 12 show only little or no growth whatsoever of the semiconductor material 30 and that the latter instead grows selectively between the surface structures 12 and thus on the flat region of the growth surface.

(22) In comparison to this, the growth on a corresponding growth substrate when using an oxygen-free AlN nucleation layer is shown. As is easily recognizable, the growth here ensues more intensively on the surfaces of the surface structures, which are covered by the semiconductor material 30 and are thus unrecognizable in the image. As a result, the grown semiconductor material 30 forms no uniform crystal surface, but instead comprises a plurality of crystal surfaces, which leads to a poor material quality of the further grown semiconductor material or in subsequently grown semiconductor layer sequence.

(23) The addition of oxygen during the production of the nucleation layer 2 thus allows a strong selectivity of the subsequent growth process of the semiconductor material of the semiconductor layer sequence to be achieved both when using an MOVPE method and when using a sputtering method for producing the nucleation layer. The addition of oxygen can thus ensue both within an MOVPE method during the corresponding production of the nucleation layer 2 and outside said method during the production of the nucleation layer by means of sputtering. Conversely, alternative nucleation processes with oxygen-free AlN within MOVPE methods always lead to significant parasitic nucleations on the surface structures, as shown in FIG. 6C.

(24) As shown in FIG. 4, the semiconductor material grown on the nucleation layer 2 can be grown so far that a semiconductor layer 31 forms, for example an undoped buffer layer, which then covers the surface structures 12. As an alternative, the semiconductor layer 31 can also comprise a plurality of layers with differing undoped and/or doped materials.

(25) In order to form the semiconductor layer sequence 3, further semiconductor layers are then grown on the semiconductor layer 31. As shown in FIG. 5, said further semiconductor layers can, for example, be formed by doped semiconductor layers 32, 33, between which an optoelectronic active layer 34 is arranged. The semiconductor layer sequence 3 can, in particular, consist of a plurality of doped and undoped layers, which are not shown here for the sake of clarity. In particular, the structure of a semiconductor layer sequence 3 for a light-emitting or light-detecting diode is known to a person skilled in the art and is thus not further elaborated. The semiconductor chip wo shown in FIG. 5 can additionally comprise further layers, such as electrode layers for electrically contacting the semiconductor layer sequence, mirror layers and/or passivation layers, for example, which are likewise not shown for the sake of clarity.

(26) In the exemplary embodiment of the electronic semiconductor chip 100 as light-emitting diode, the semiconductor chip 100 can emit light in the direction of an upper side facing away from the growth substrate 1 as well as in the direction of the growth substrate 1 during operation. A decrease or reduction in total reflection can be achieved by the surface structures 12 for light emitted by the optoelectronic active layer 34 in the direction of the growth substrate 1.

(27) The previously described method allows an improvement in the selectivity of the growth process of the semiconductor layer sequence on the nucleation layer to be achieved by the use of an oxygen-containing AlN nucleation layer on a pre-structured substrate, which can also advantageously lead to a significant expansion of the process parameters of the subsequent layers. Furthermore, the low and preferably scant or non-existent growth of the three-dimensionally designed surface structures positively influences not only the material quality in the event of light-emitting diodes but also the electroscopic parameters, such as light, leakage currents and low current behavior, for example. As no time-consuming temperature ramps and pressure slopes are necessary during the nucleation, it may be possible to perceptibly reduce the growth time in an MOVPE system.

(28) In addition, it has been found that a determination of the degree of relaxation of the deposited oxygen-containing aluminum nitride as nucleation layer and the monitoring degree of the three-dimensionally designed surface structures allows an adjustment of the curvature of the growth substrate during the growth of semiconductor layer sequence. To this end, FIG. 7 shows wafer bows C during the semiconductor growing process in accordance with the processing time t for different compositions of the nucleation layer. It has been found that the curvature of the wafers during growth can be controlled by the characteristics of the oxygen-containing AlN nucleation layer. The targeted addition and amount of oxygen can influence the degree of relaxation of the oxygen-containing AlN and, accordingly, the state of tensioning of the subsequent layers.

(29) The embodiments shown in the illustrations can comprise further and alternative features pursuant to the description in the general section.

(30) The description on the basis of the embodiments does not restrict the invention thereto. Instead, the invention includes every new feature as well as every combination of features, which in particular includes very combination of features in the claims, even if such feature or such claim is not itself explicitly stated in the claims or embodiments.