DUAL CLOCK SIGNAL TO PULSE-WIDTH MODULATED SIGNAL CONVERSION CIRCUIT

Abstract

Disclosed is a dual clock signal to pulse-width modulated signal conversion circuit, comprising: a first counter, an input end of which inputs a first clock signal, and an output end of which outputs a divided signal; an edge reset circuit, an input end of which inputs the divided signal, the output end of which outputs a first reset pulse signal and a second reset pulse signal, the first reset pulse signal being configured for resetting a second counter, and the second reset pulse signal being configured for resetting a third counter; a second counter, an input end of which inputs the second clock signal and the first reset pulse signal, and an output end of which outputs the first pulse-width modulated signal; a third counter, an input end of which inputs the second clock signal and the second reset pulse signal, and an output end of which outputs the second pulse-width modulated signal; a logic processing circuit, an input end of which inputs the first pulse-width modulated signal and the second pulse-width modulated signal, and an output end of which outputs a pulse-width modulated signal PWM_OUT. The disclosure offers high precision, system stability, and good anti-interference.

Claims

1. A dual clock signal to pulse-width modulated signal conversion circuit comprising: an input end configured to receive a first clock signal and a second clock signal, and an output end configured to provide a pulse-width modulated signal; wherein a first clock cycle of the first clock signal is greater than or equal to a second clock cycle of the second clock signal; and a high level average duty cycle of the first pulse-width modulated signal is equal to at least one of a ratio of the second clock cycle of the second clock signal to the first clock cycle of the first clock signal cycle, multiplied by a proportionality coefficient, and 1 minus the ratio of the second clock cycle of the second clock signal to the first clock cycle of the first clock signal, multiplied by the proportionality coefficient K, such that the high level average duty cycle is determined by at least one of the equations:
K×(T0/T1); and 1−K×(T0/T1), wherein T1 represents the first clock cycle, T0 represents the second clock cycle and K represents the proportionality coefficient.

2. The dual clock signal to pulse-width modulated signal conversion circuit according to claim 1, wherein the proportionality coefficient is ½.sup.n, where n is an integer.

3. The dual clock signal to pulse-width modulated signal conversion circuit according to claim 2, wherein n is 0.

4. The dual clock signal to pulse-width modulated signal conversion circuit according to claim 1, wherein a low-level pulse duration and a high-level pulse duration of the pulse-width modulated signal are both equal to an integer multiple of the second clock cycle of the second clock signal.

5. The dual clock signal to pulse-width modulated signal conversion circuit according to claim 1, further comprising: a pulse-width modulation circuit including a first input configured to receive the first clock signal and the second clock signal, and a first output configured to provide a first intermediary pulse-width modulated signal and a second intermediary pulse-width modulated signal; and a logic processing circuit including a second input configured to receive the first intermediary pulse-width modulated signal and the second intermediary pulse-width modulated signal, and a second output configured to provide the pulse-width modulated signal.

6. The dual clock signal to pulse-width modulated signal conversion circuit according to claim 5, wherein a first average frequency of the first intermediary pulse-width modulated signal is equal to a second average frequency of the second intermediary pulse-width modulated signal, and a third cycle of the first intermediary pulse-width modulated signal and a fourth cycle of the second intermediary pulse-width modulated signal are equal to an integer multiple of the second clock cycle of the second clock signal.

7. The dual clock signal to pulse-width modulated signal conversion circuit according to claim 5, wherein a first low-level average duty cycle of the first intermediary pulse-width modulated signal and a second low-level average duty cycle of the second intermediary pulse-width modulated signal are equal to at least one of ½ of the ratio of the second clock cycle of the second clock signal to the first clock cycle of the first clock signal and 1 minus ½ of the ratio of the second clock cycle of the second clock signal to the first clock cycle of the first clock signal.

8. The dual clock signal to pulse-width modulated signal conversion circuit according to claim 5, wherein a first average frequency of the first intermediary pulse-width modulated signal is equal to a second frequency of a divided signal, and a low-level pulse duration and a high-level pulse duration of the first intermediary pulse-width modulated signal are both an integer multiple of the second clock cycle of the second clock signal, wherein a third average frequency of the second intermediary pulse-width modulated signal is equal to the frequency of the divided signal, and a low-level pulse duration and a high-level pulse duration of the second intermediary pulse-width modulated signal are both an integer multiple of the second clock cycle of the second clock signal.

9. The dual clock signal to pulse-width modulated signal conversion circuit according to claim 5, wherein the logic processing circuit performs a logic AND operation on the first intermediary pulse-width modulated signal and the second intermediary pulse-width modulated signal.

10. The dual clock signal to pulse-width modulated signal conversion circuit according to claim 5, wherein the pulse-width modulation circuit comprises: a first counter, configured to receive the first clock signal, and provide a divided signal; an edge reset circuit configured to receive the divided signal and provide a first reset pulse signal and a second reset pulse signal, the first reset pulse signal being configured for resetting a second counter, and the second reset pulse signal being configured for resetting a third counter; the second counter configured to receive the second clock signal and the first reset pulse signal, and provide the first intermediary pulse-width modulated signal; a third counter configured to receive the second clock signal and the second reset pulse signal, and provide the second pulse-width modulated signal.

11. The dual clock signal to pulse-width modulated signal conversion circuit according to claim 10, wherein a fourth cycle of the divided signal is an integer multiple of the first clock cycle of the first clock signal.

12. The dual clock signal to pulse-width modulated signal conversion circuit according to claim 10, wherein the edge reset circuit generates the first reset pulse signal at a rising edge of the divided signal, and generates the second reset pulse signal at the falling edge of the divided signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG. 1 illustrates a circuit diagram of a dual clock signal to pulse-width modulated signal conversion circuit.

[0027] FIG. 2 is a signal sequence diagram of the circuit in FIG. 1.

DETAILED DESCRIPTION OF EMBODIMENTS

[0028] Hereinafter, preferred embodiments of the present disclosure will be illustrated in detail with reference to FIGS. 1˜2.

[0029] As illustrated in FIG. 1, embodiments of the present disclosure provide a dual clock signal to pulse-width modulated signal conversion circuit, the input end of which outputs two ways of asynchronous clock signals, the output end of which outputs a pulse-width modulated signal PWM_OUT, wherein clock cycle T1 of the first clock signal CLK1 is greater than or equal to clock cycle T0 of the second clock signal CLK0_T0, high-level average duty cycle Duty of the pulse-width modulated signal PWM_OUT is equal to the ratio of the clock cycle of the second clock signal to the clock cycle of the first clock signal, multiplied by a proportionality coefficient K, namely, Duty=K×(T0/T1), or equal to 1 minus the ratio, multiplied by a proportionality coefficient K, of the clock cycle of the second clock signal to the clock cycle of the first clock signal, namely, Duty=1−K×(T0/T1). The cycle of the pulse-width modulated signal is an integer multiplicity of the second clock signal cycle, where the proportionality coefficient K=½.sup.n, where the variable n is an integer. In a preferred embodiment of the present disclosure, the variable n is 0.

[0030] The dual clock signal to pulse-width modulated signal conversion circuit further comprises:

[0031] a pulse-width modulation circuit 100, the input end of which inputs the first clock signal CLK1 and the second clock signal CLK0, and the output end of which outputs a first pulse-width modulated signal PWMA and a second pulse-width modulated signal PWMB, wherein low-level duty cycles of PWMA and PWMB are both T0/(2*T1), and high-level duty cycles thereof are both 1−T0/(2*T1);

[0032] a logic processing circuit 105, the input end of which inputs the first pulse-width modulated signal PWMA and the second pulse-width modulated signal PWMB, the output end of which outputs the pulse-width modulated signal PWM_OUT and its inverted signal PWM_OUTB, wherein the logic processing circuit 105 performs logic AND operation on the first pulse-width modulated signal PWMA and the second pulse-width modulated signal PWMB, where PWM_OUT=PWMA & PWMB, and PWM_OUTB=−(PWMA&PWMB).

[0033] Average frequency of the first pulse-width modulated signal is equal to average frequency of the second pulse-width modulated signal. Cycle of the first pulse-width modulated signal and cycle of the second pulse-width modulated signal are both equal to an integer multiplicity of the clock cycle of the second clock signal.

[0034] The pulse-width modulation circuit 100 further comprises:

[0035] a first counter 101, the input end of which inputs the first clock signal CLK1, and the output end of which outputs the divided signal CLKX, wherein cycle of the divided signal CLKX is an integer multiplicity of the clock cycle of the first clock signal CLK1;

[0036] an edge reset circuit 102, the input end of which inputs the divided signal CLKX, and the output end of which outputs a first reset pulse signal RSTB_a and a second reset pulse signal RSTB_b, wherein the edge reset circuit 102 generates the first reset pulse signal RSTB_a at the rising edge of the divided signal CLKX, and the edge reset circuit 102 generates the second reset pulse signal RSTB_b at the falling edge of the divided signal CLKX, the first reset pulse signal RSTB_a being configured for resetting a second counter, and the second reset pulse signal RSTB_b is configured for resetting a third counter;

[0037] a second counter 103, the input end of which inputs the second clock signal CLK0 and the first reset pulse signal RSTB_a, and the output end of which outputs the first pulse-width modulated signal PWMA, wherein average frequency of the first pulse-width modulated signal PWMA is equal to frequency of the divided signal CLKX, and average cycle of the first pulse-width modulated signal PWMA is equal to average cycle of the first reset pulse signal RSTB_a, and low-level pulse duration and high-level pulse duration of the first pulse-width modulated signal PWMA are both an integer multiplicity of the clock cycle of the second clock signal CLK0;

[0038] a third counter 104, the input end of which inputs the second clock signal CLK0 and the second reset pulse signal RSTB_b, and the output end of which outputs the second pulse-width modulated signal PWMB, wherein average frequency of the second pulse-width modulated signal PWMB is equal to the frequency of the divided signal CLKX, and average cycle of the second pulse-width modulated signal PWMB is equal to average cycle of the second reset pulse signal RSTB_b, low-level pulse duration and high-level pulse duration of the second pulse-width modulated signal PWMB being both an integer multiplicity of the clock cycle of the second clock signal CLK0.

[0039] As illustrated in FIG. 2, in an embodiment of the present disclosure, the clock cycle of the first clock signal CLK1 is T1, the clock cycle of the second clock signal CLK0 is T0, the divided signal CLKX refers to the frequency of the first clock signal CLK1 divided by 8, the first reset pulse signal RSTB_a is generated at the rising edge of the divided signal CLKX, and the second reset pulse signal RSTB_b is generated at the falling edge of the divided signal CLKX, the low-level width of the first pulse-width modulated signal PWMA and the low-level width of the second pulse-width modulated signal PWMB being both equal to 4 times the clock cycle of the second clock signal CLK0; the first pulse-width modulated signal PWMA and the second pulse-width modulated signal PWMB are subjected to a logic AND operation to produce two ways of complementary pulse-width modulated signals; the frequency of the pulse-width modulated signal PWM_OUT is twice the frequency of the first pulse-width modulated signal PWMA (in most cases, the multiplicity relationship is 2; however, it is not the case in some edge conditions), PWM_OUT=PWMA & PWMB, PWM_OUTB=−(PWMA & PWMB); then, the average duty cycle of PWM_OUT is Duty=(4*T1−4*T0)/(4*T1)=(T1−T0)/T1=1−T0/T1; while the average duty cycle of PWM_OUTB is Duty=(4*T0)/(4*T1)=T0/T1.

[0040] Embodiments of the present disclosure offer a high precision, a system stability, and a good anti-interference.

[0041] Although the present disclosure has been described in detail through the foregoing preferred embodiments, it should be understood that the illustrations above shall not be regarded as limitations to the present disclosure. The algorithm above is only illustrative, and any algorithm involving two frequency signals and a pulse-width modulated signal falls within the spirit of the present disclosure. After those skilled in the art having read the contents above, many modifications and substitutions to the present disclosure are all obvious.