ELECTRONIC CIRCUIT FOR SINGLE-EVENT LATCH-UP DETECTION AND PROTECTION

Abstract

An electronic circuit for single-event latch-up (SEL) detection and protection of a target integrated circuit (IC) is disclosed. The circuit comprises: a first detector configured for detecting an absolute load current (i) and comparing the absolute load current (i) with a threshold current (i.sub.th); a second detector configured for detecting a rate of change of load current (di/dt) and comparing the rate of change of load current (di/dt) with a threshold current change rate (di/dt).sub.th; and a determination module for triggering a power shut-down to the target IC if the absolute load current (i) exceeds the threshold current (i.sub.th) and/or the rate of change of load current (di/dt) exceeds the threshold current change rate (di/dt).sub.th.

Claims

1. An electronic circuit for single-event latch-up (SEL) detection and protection of a target integrated circuit (IC) comprising: a) a first detector configured for detecting an absolute load current (i) and comparing the absolute load current (i) with a threshold current (i.sub.th); b) a second detector configured for detecting a rate of change of load current (di/dt) and comparing the rate of change of load current (di/dt) with a threshold current change rate (di/dt).sub.th; and c) a determination module for triggering a power shut-down to the target IC if the absolute load current (i) exceeds the threshold current (i.sub.th) and/or the rate of change of load current (di/dt) exceeds the threshold current change rate (di/dt).sub.th.

2. The electronic circuit according to claim 1 wherein the threshold current (i.sub.th) and/or the threshold current change rate (di/dt).sub.th are provided via a threshold determination unit.

3. The electronic circuit according to claim 2 wherein the threshold determination unit is pre-programmed with values for the threshold current (i.sub.th) and/or the threshold current change rate (di/dt).sub.th.

4. The electronic circuit according to claim 2 wherein the threshold determination unit calculates values for the threshold current (i.sub.th) and/or the threshold current change rate (di/dt).sub.th.

5. The electronic circuit according to claim 4 wherein the threshold determination unit monitors an actual load current and/or an actual rate of change of load current to determine a range indicative of normal circuit behavior and determines the threshold values based on an expected maximum value for the normal operating range.

6. The electronic circuit according to claim 5 wherein the threshold values are within a range of 1.5 to 2 times, 2 to 3 times, 3 to 4 times or 4 to 5 times the expected maximum values.

7. The electronic circuit according to claim 1 wherein the absolute load current (i) is detected by measuring the voltage (V) across a resistor R.sub.sense and dividing V by R.sub.sense.

8. (canceled)

9. (canceled).

10. The electronic circuit according to claim 1 wherein the first detector comprises a first comparator for comparing the absolute load current (i) with the threshold current (i.sub.th).

11. The electronic circuit according to claim 1 wherein the second detector comprises a second comparator for comparing the rate of change of load current (di/dt) with the threshold current change rate (di/dt).sub.th.

12. The electronic circuit according to claim 11 wherein the second comparator comprises a first module for comparing the absolute load current (i) with a first load current value (i.sub.th1) and a second module for comparing the absolute load current (i) with a second load current value (i.sub.th2), where i.sub.th2>i.sub.th1 and wherein a time interval (dt) is measured between when the absolute load current (i) exceeds i.sub.th1 to when the absolute load current (i) exceeds i.sub.th2 so as to determine the rate of change of load current (di/dt).

13. The electronic circuit according to claim 12 wherein the threshold current change rate (di/dt).sub.th is set such that di.sub.th=i.sub.th2−k.sub.m and dt.sub.th=a typical time interval for the load current (i) to increase from i.sub.th1 to i.sub.th2 due to a SEL event.

14. The electronic circuit according to claim 12 wherein the threshold current i.sub.th is 10, 20, 30, 50 or 100 times greater than i.sub.th2.

15. The electronic circuit according to claim 1 wherein a filter is employed to filter out false trigger signals caused by normal transient current.

16. The electronic circuit according to claim 1 wherein the determination module comprises one or more logic gates.

17. The electronic circuit according claim 1 wherein the target integrated circuit (IC) is a Commercial-Off-The-Shelf (COTS) IC.

18. The electronic circuit according to claim 1 wherein the target integrated circuit (IC) is configured for a space application.

19. The electronic circuit according to claim 1 wherein the determination module triggers a power cycling stage to shut-down the target IC and subsequently resume power to the target IC after a pre-determined duration.

20. The electronic circuit according to claim 19 wherein the pre-determined duration is calculated to ensure SEL effects are completely eradicated.

21. An electronic device comprising an electronic circuit for single-event latch-up (SEL) detection and protection in accordance with claim 1 and a target integrated circuit (IC).

22. A method of single-event latch-up (SEL) detection and protection for a target integrated circuit (IC) comprising: a) detecting an absolute load current (i); b) comparing the absolute load current (i) with a threshold current (i.sub.th); c) detecting a rate of change of load current (di/dt); d) comparing the rate of change of load current (di/dt) with a threshold current change rate (di/dt).sub.th; and e) triggering a power shut-down to the target IC if the absolute load current (i) exceeds the threshold current (i.sub.th) and/or the rate of change of load current (di/dt) exceeds the threshold current change rate (di/dt).sub.th.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Embodiments of the invention will now be described, by way of example only, with reference to the following drawings, in which:

[0037] FIG. 1 is a schematic diagram of a conventional SEL detection and protection circuit, as explained above;

[0038] FIG. 2 is a block diagram of a generic implementation of an SEL detection and protection circuit in accordance with a first embodiment of the invention;

[0039] FIG. 3 is a block diagram of an SEL detection and protection circuit in accordance with a second embodiment of the invention;

[0040] FIG. 4 is a block diagram of an SEL detection and protection circuit in accordance with a third embodiment of the invention; and

[0041] FIG. 5 is a flow diagram illustrating an SEL detection and protection method in accordance with an embodiment of the invention.

DETAILED DESCRIPTION

[0042] In accordance with a first embodiment of the present invention there is provided an electronic circuit 100 for single-event latch-up (SEL) detection and protection as shown in FIG. 2. The circuit 100 comprises a target COTS IC 102 coupled to a first detector 104 for detecting the absolute load current (i) of the IC 102 and a second detector 106 for detecting the rate of change of load current (di/dt) for the IC 102. Together, the first and second detectors 104, 106 can be considered to constitute a detection stage as will be explained in more detail below.

[0043] A threshold determination unit 108 is provided between the IC 102 and each of the first detector 104 and second detector 106 for providing a threshold current (i.sub.th) and threshold current change rate (di/dt).sub.th. In this embodiment, the threshold current (i.sub.th) and threshold current change rate (di/dt).sub.th are pre-programmed into the threshold determination unit 108. However, in other embodiments the threshold values may be determined by monitoring the actual load current and rate of change of the load current to determine a range indicative of normal circuit behavior, extracting from the range an expected maximum value for the normal operating range and setting the threshold values well above the expected maximum values (e.g. 1.5, 2, 3, 4 or 5 times the expected maximum values).

[0044] Although not shown in FIG. 2, each of the first and second detectors 104, 106 comprise a comparator for comparing the absolute load current (i) with a threshold current (i.sub.th); and the rate of change of load current (di/dt) with a threshold current change rate (di/dt).sub.th, respectively.

[0045] Output signals from each of the first and second detectors 104, 106 are input to a determination stage (i.e. module) 110. The determination stage 110 is configured to trigger a power shut-down to the IC 102 if the absolute load current (i) exceeds the threshold current (i.sub.th) and/or the rate of change of load current (di/dt) exceeds the threshold current change rate (di/dt).sub.th. In the embodiment shown in FIG. 2, the determination stage 110 is coupled to a power cycling stage 112 which is configured to receive a signal from the determination stage 110 and shut-down the IC 102 via power switch 114 and to subsequently resume power to the IC 102 (by reconnecting power switch 114) after a pre-determined duration. The pre-determined duration is established so as to provide sufficient time for the effects of SEL to be eradicated.

[0046] FIG. 3 shows a more detailed embodiment of an SEL detection and protection circuit 120 in accordance with the present invention. This embodiment is based on the general architecture outlined above in relation to FIG. 2 and so like reference numerals will be employed for like features. As illustrated in FIG. 3, the circuit 120 comprises a detection stage 122 in addition to the determination stage 110.

[0047] In FIG. 3, more details of the first and second detectors 104, 106 in the detection stage 122 are shown. In particular, the first detector 104 comprises a voltage amplifier 104a and a first comparator 104b. The voltage amplifier 104a is arranged to sense the load current (i) through a resistor R.sub.sense. The first comparator 104b then compares the load current (i) with the threshold current (i.sub.th) provided by the threshold determination unit 108.

[0048] The second detector 106 comprises an analog differentiator 106a and a second comparator 106b. The analog differentiator 106a is arranged to detect the rate of change of load current (di/dt) through the resistor R.sub.sense. The second comparator 106b then compares the rate of change of load current (di/dt) with the threshold current change rate (di/dt).sub.th provided by the threshold determination unit 108.

[0049] Output signals from each comparator are input to the determination stage 110 as before. In this embodiment, the output signal from the second comparator 106b is put through a low-pass filter 124 before being received by logic gate 126 so as to remove false trigger signals that may be caused by normal transient current. The output signal from the first comparator 104b is also input to the logic gate 126 which will send a signal to the power cycling stage 112 if either of the absolute load current (i) or rate of change of load current (di/dt) has exceeded the respective threshold values (as determined by each comparator).

[0050] Upon receipt of a power shut-down signal from the determination stage 110, the power cycling stage 112 will then disable the power switch 114 to the IC 102 and subsequently resume power to the IC 102 (by reconnecting power switch 114) after a pre-determined duration.

[0051] FIG. 4 shows another detailed embodiment of an SEL detection and protection circuit 130 in accordance with the present invention. This embodiment is also based on the general architecture outlined above in relation to FIG. 2 and has some features in common with the embodiment of FIG. 3 and so like reference numerals will be employed for like features. As illustrated in FIG. 4, the circuit 130 comprises a detection stage 122 and a determination stage 110, similar to FIG. 3.

[0052] In the embodiment of FIG. 4, the load current (i) is again sensed through R.sub.sense and is obtained at the voltage amplifier 104a. However, in this case the rate of change of load current (di/dt) is not directly obtained but is calculated as explained below.

[0053] Similarly to the embodiment of FIG. 3, the obtained load current (i) is compared with an absolute threshold current i.sub.th0 (which is programmed into the system via the threshold determination unit 108) by a first comparator 104b. However, in this case the threshold current change rate (di/dt).sub.th is not programmed directly into the threshold determination unit 108. Instead, first and second threshold current values i.sub.th1 and i.sub.th2 are programmed into the threshold determination unit 108 and each of which are compared to the load current (i) by a comparator 132a and 132b, respectively. Notably, i.sub.th0>>i.sub.th2>i.sub.th1.

[0054] The logic gate 126 in the determination stage 110 monitors the output from each of the comparators 104b, 132a and 132b. When the load current (i) is greater than or equal to i.sub.th1, the determination stage 110 generates a timestamp or starts a clock to measure the time interval (dt) until the load current (i) is greater than or equal to i.sub.th2. If the measured time (dt) is determined to be equal to or within a pre-determined threshold time interval (dt.sub.th) it may be determined that a SEL event has occurred and the power shut-down will be triggered.

[0055] Thus, knowing the difference between i.sub.th1 and i.sub.th2 (di) and the time taken (dt) for the current to increase from i.sub.th1 to i.sub.th2 we can determine the current change rate (di/dt) and can compare it to a threshold current change rate (di/dt).sub.th.

TABLE-US-00001 TABLE 1 Comparison of an embodiment of the invention with the conventional approach Embodiment 2 Conventional Approach Response Time [μs] 100 750 Shutdown Current [mA] 180 400

[0056] Table 1 tabulates the response time and shut-down current for the second embodiment of the present invention described above in relation to FIG. 3 and the conventional approach, when an SEL event is detected. At 150 mA nominal load current, the embodiment of the invention is able to identify the SEL occurrence and shut down the power supply within 100 μs. This is a significant 7.5 times faster than the conventional approach. Furthermore, the shutdown current (i.e. load current when the SEL detection and protection circuit is triggered) is a low 180 mA (which is equivalent to 1.2 times the nominal current) when using the embodiment of the invention. This is a significant greater than 2 times lower than the conventional approach. Thus, embodiments of the invention can achieve a substantially lower shutdown current and a substantially faster response time than the current state of the art. This translates to substantially-enhanced SEL protection for a target IC, and hence the lifetime of a COTS IC can be expected to be significantly extended, which results in substantially increased reliability and greater suitability for demanding applications such as those encountered in space.

[0057] FIG. 5 is a flow diagram illustrating an SEL detection and protection method 200 in accordance with an embodiment of the invention. The method 200 comprises the following steps:

Step 202: detecting an absolute load current (i) for a target IC;
Step 204: detecting a rate of change of load current (di/dt) for the target IC;
Step 206: comparing the absolute load current (i) with a threshold current (i.sub.th);
Step 208: comparing the rate of change of load current (di/dt) with a threshold current change rate (di/dt).sub.th; and
Step 210: triggering a power shut-down to the target IC if the absolute load current (i) exceeds the threshold current (i.sub.th) and/or the rate of change of load current (di/dt) exceeds the threshold current change rate (di/dt).sub.th.

[0058] The method may be implemented by any of the preceding embodiments.

[0059] An advantage of the proposed method is that SEL can be detected using a combination of absolute current detection and current change rate detection so that protection of the target IC can be implemented when either one of these values exceeds its respective threshold value.

[0060] Although only certain embodiments of the present invention have been described in detail, many variations are possible in accordance with the appended claims.