CHARGE AMPLIFIER CIRCUIT WITH A HIGH OUTPUT DYNAMIC RANGE FOR A MICROELECTROMECHANICAL SENSOR

Abstract

A charge amplifier circuit is provided. The charge amplifier circuit is couplable to a transducer that generates an electrical charge that varies with an external stimulus. The charge amplifier circuit includes an amplification stage having an input node, couplable to the transducer, and an output node. The amplification stage biases the input node at a first direct current (DC) voltage. The charge amplifier circuit includes a feedback circuit, which includes a feedback capacitor, electrically coupled between the input and output nodes of the amplification stage. The feedback circuit includes a resistor electrically coupled to the input node, and a level-shifter circuit, electrically coupled between the resistor and the output node. The level-shifter circuit biases the output node at a second DC voltage and as a function of a difference between the second DC voltage and a reference voltage.

Claims

1. A circuit, comprising: an input; an output; an amplification stage coupled between the input and the output and configured to bias the input at a first direct current (DC) voltage; and a feedback circuit including a level shifter and coupled between the input and the output, the feedback circuit being configured to bias the output at a second DC voltage.

2. The circuit according to claim 1, wherein the input is configured to be coupled to a transducer.

3. The circuit according to claim 1, comprising: a feedback capacitance having a first side coupled to the input and a second side coupled to the output; and a feedback resistance having a first terminal coupled to the input and a second terminal.

4. The circuit according to claim 3, wherein the level shifter includes: first and second transistors each having a respective first conduction terminal coupled to the second terminal of the feedback resistance, a respective control terminal coupled to the output, and a respective second conduction terminal.

5. The circuit according to claim 4, wherein the feedback circuit includes: a transconductance amplifier configured to cause a first current to be drawn from the second transistor and cause a second current to be source into the first transistor based on a difference between the second DC voltage and a reference voltage.

6. The circuit according to claim 5, wherein the transconductance amplifier includes: a first differential transistor pair having a control terminal coupled to the output; a second differential transistor pair having a control terminal configured to receive the reference voltage; a first current mirror, coupled to the first differential transistor pair and configured to set the first current to a current flowing in the first differential transistor pair; and a second current mirror, coupled to the second differential transistor pair and configured to set the second current to a current flowing in the second differential transistor pair.

7. The circuit according to claim 1, wherein the level shifter is configured to bias the output at the second DC voltage based on a difference between the second DC voltage and a reference voltage.

8. The circuit according to claim 1, wherein the amplification stage includes: an amplification transistor having a control terminal coupled to the input, a first conduction terminal coupled to the output, and a second conduction terminal configured to receive a supply voltage.

9. A device, comprising: a microelectromechanical system (MEMS) transducer having an output and configured to generate, at the output, an electrical charge that varies temporally; and a charge amplifier circuit including: an input coupled to the output of the MEMS transducer; an output; an amplification stage coupled between the input and the output and configured to bias the input at a first direct current (DC) voltage; and a feedback circuit including a level shifter and coupled between the input and the output, the feedback circuit being configured to bias the output at a second DC voltage.

10. The device according to claim 9, wherein the charge amplifier circuit includes: a feedback capacitance having a first side coupled to the input and a second side coupled to the output; and a feedback resistance having a first terminal coupled to the input and a second terminal.

11. The device according to claim 10, wherein the level shifter includes: first and second transistors each having a respective first conduction terminal coupled to the second terminal of the feedback resistance, a respective control terminal coupled to the output, and a respective second conduction terminal.

12. The device according to claim 11, wherein the feedback circuit includes: a transconductance amplifier configured to cause a first current to be drawn from the second transistor and cause a second current to be source into the first transistor based on a difference between the second DC voltage and a reference voltage.

13. The device according to claim 12, wherein the transconductance amplifier includes: a first differential transistor pair having a control terminal coupled to the output; a second differential transistor pair having a control terminal configured to receive the reference voltage; a first current mirror, coupled to the first differential transistor pair and configured to set the first current to a current flowing in the first differential transistor pair; and a second current mirror, coupled to the second differential transistor pair and configured to set the second current to a current flowing in the second differential transistor pair.

14. The device according to claim 9, wherein the level shifter is configured to bias the output at the second DC voltage based on a difference between the second DC voltage and a reference voltage.

15. The device according to claim 9, wherein the amplification stage includes: an amplification transistor having a control terminal coupled to the input, a first conduction terminal coupled to the output, and a second conduction terminal configured to receive a supply voltage.

16. A method, comprising: receiving, at an input of a charge amplifier circuit, an electrical charge that varies temporally; biasing the input at a first direct current (DC) voltage; and biasing an output of the charge amplifier circuit at a second DC voltage.

17. The method according to claim 16, wherein the charge amplifier circuit includes: a feedback capacitance coupled between the input and the output, a feedback resistance having a first terminal coupled to the input and a second terminal; and a level shifter coupled between the second terminal of the feedback resistance and the output.

18. The method according to claim 17, comprising: drawing, by a transconductance amplifier, a first current from a first transistor and injecting a second current into a second transistor based on a difference between the second DC voltage and a reference voltage, wherein the first and second transistors each have a respective first conduction terminal coupled to the second terminal of the feedback resistance, a respective control terminal coupled to the output, and a respective second conduction terminal.

19. The method according to claim 18, comprising: causing, by the transconductance amplifier, a current that is the same as the first current to flow in a third transistor, wherein the third transistor has a first conduction terminal coupled to the control terminal of the second transistor, a control terminal coupled to the output, and a second conduction terminal.

20. The method according to claim 18, comprising: setting, by a mirror circuitry, the first and second currents to currents that flow in first and second differential transistor pairs of a differential pair, respectively, wherein the first differential transistor pair has a control terminal coupled to the output and the second differential transistor pair has a control terminal configured to receive the reference voltage.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0018] For a better understanding of the present disclosure, preferred embodiments thereof are now described, purely by way of non-limiting example and with reference to the attached drawings, wherein:

[0019] FIG. 1 shows a block diagram of a microelectromechanical system (MEMS) device;

[0020] FIG. 2 shows an equivalent circuit diagram of the MEMS device illustrated in FIG. 1;

[0021] FIG. 3 shows an example of plot of an analog signal, as a function of an electrical charge;

[0022] FIG. 4 shows a principle circuit diagram of the present electronic circuit, coupled to a sensor;

[0023] FIG. 5 shows a circuit diagram of the present electronic circuit, with parts represented schematically in terms of working principle;

[0024] FIGS. 6 and 8 show circuit diagrams of embodiments of the present electronic circuit; and

[0025] FIG. 7 shows plots of voltages and currents generated within the present electronic circuit, as a function of a supply voltage V.sub.DD.

DETAILED DESCRIPTION

[0026] The present circuit is based on the idea of decoupling the biasing voltages of the input node IN and of the output node OUT of the readout circuit, as illustrated schematically in FIG. 4, where elements already present in FIG. 2 are designated by the same reference signs, unless specified otherwise. In addition, the readout circuit, designated by 30, is described limitedly to the differences with respect to what is illustrated in FIG. 1.

[0027] In detail, the readout circuit 30 comprises a feedback circuit 32, which in turn comprises a control circuit 34 and a level shifter 36.

[0028] The control circuit 34 comprises a first input, connected to the output node OUT, and a second input, which in use is set at a reference voltage V.sub.ref. As described in greater detail hereinafter, the reference voltage V.sub.ref is directly proportional to the supply voltage V.sub.DD, or is generated by using a corresponding bandgap circuit (not illustrated). In what follows it is assumed, purely by way of example, that the relation V.sub.ref=0.5*V.sub.DD applies, and that the reference voltage V.sub.ref is generated starting from the supply voltage V.sub.DD by means of a resistive divider (not shown).

[0029] The level shifter 36 is connected between the second terminal of the feedback resistor 22 and the output node OUT. Furthermore, the level shifter 36 is operatively connected to the output of the control circuit 34, as described hereinafter. The resistance of the feedback resistor 22 ranges, for example, between 100 GΩ and 1 TΩ.

[0030] As shown in FIG. 5, the level shifter 36 comprises a respective pair of variable-current generators 40, 42, referred to hereinafter as the “first level-shift generator 40” and the “second level-shift generator 42”, as well as a pair of respective MOSFETs 44, 46, referred to hereinafter as the “first level-shift transistor 44” and the “second level-shift transistor 46”.

[0031] The first level-shift transistor 44 is of the P-channel enhancement-mode type; the second level-shift transistor 46 is of the N-channel depletion-mode type (also known as “native N-channel transistor”). Furthermore, the first and the second level-shift transistors 44, 46 are, for example, of the type with source terminal connected to the bulk.

[0032] In detail, the first level-shift generator 40 has a first and a second conduction terminal, which are connected to the supply node N.sub.DD and to the source terminal, respectively, of the first level-shift transistor 44, which forms a first internal node N.sub.1, which electrically coincides with the second terminal of the feedback resistor 22. Furthermore, the first level-shift generator 40 has a control terminal, which is connected to a first output of the control circuit 34.

[0033] The second level-shift generator 42 has a first and a second conduction terminal, which are connected to the source terminal of the second level-shift transistor 46 and to the ground, respectively, of the readout circuit 30. The source terminal of the second level-shift transistor 46 forms a second internal node N.sub.2, which electrically coincides with the second terminal of the feedback resistor 22, and therefore also with the first internal node N.sub.1. In addition, the second level-shift generator 42 has a respective control terminal, which is connected to a second output of the control circuit 34.

[0034] The drain terminals of the first and of the second level-shift transistors 44, 46 are connected to the ground of the readout circuit 30 and to the supply node N.sub.DD, respectively. The gate terminals of the first and of the second level-shift transistors 44, 46 are connected together so as to form a third internal node N.sub.3, which electrically coincides with the output node OUT.

[0035] In greater detail, the control circuit 34 supplies on its own first and second outputs, respectively, a first and a second control signal V.sub.C, V.sub.C′, which, as described in greater detail hereinafter, depend upon the difference between the output biasing voltage V.sub.CMO and the reference voltage V.sub.ref, so as to form a closed control loop. In this regard, the possible contribution due to the presence of a (small signal) output voltage V.sub.out is irrelevant, since said contribution would fall outside the frequency band in which the control circuit 34 operates.

[0036] As illustrated in FIG. 6, the readout circuit 30 also comprises a pair of transistors 140, 142, referred to hereinafter respectively as “injection transistor 140” and “pick-up transistor 142”.

[0037] In particular, the injection transistor 140 is a P-channel enhancement-mode MOSFET, which performs the function of the first level-shift generator 40. For this purpose, the source and drain terminals of the injection transistor 140 are connected to the supply node N.sub.DD and to the first internal node N.sub.1, respectively.

[0038] The pick-up transistor 142 is an N-channel depletion-mode MOSFET, which performs the function of the second level-shift generator 42. For this purpose, the source and drain terminals of the injection transistor 140 are connected to the second internal node N.sub.2 and to the supply node N.sub.DD, respectively.

[0039] As illustrated again in FIG. 6, the control circuit 34 is formed by an operational amplifier, and hence comprises a differential pair formed by a first and a second MOSFET 51, 52, referred to hereinafter as the “first control transistor 51” and the “second control transistor 52”, respectively. In particular, the first and the second control transistors 51, 52 are P-channel enhancement-mode MOSFETs, the source terminals of which are connected together.

[0040] The control circuit 34 further comprises a respective current generator 154, referred to hereinafter as “control generator 154”. In particular, the control generator 154 is interposed between the supply node N.sub.DD and the source terminals of the first and the second control transistors 51, 52. Furthermore, the control generator 154 generates a constant current I.sub.tot, which divides between the first and the second control transistors 51, 52 as a function of the voltages present on the respective gate terminals, as described hereinafter. For this purpose, the gate terminal of the first control transistor 51 is connected to the third internal node N.sub.3, and therefore also to the output node OUT (not shown in FIG. 6), and the gate terminal of the second control transistor 52 is set at the reference voltage V.sub.ref.

[0041] The control circuit 34 further comprises a third, a fourth, a fifth and a sixth control transistor 53, 54, 55, 56.

[0042] In detail, the third, the fourth and the fifth control transistors 53, 54, 55 are N-channel enhancement-mode MOSFETs; the sixth control transistor 56 is a P-channel enhancement-mode MOSFET. Furthermore, the third, the fourth and the sixth control transistors 53, 54, 56 are diode-connected; i.e., they have the respective drain terminals connected to the respective gate terminals.

[0043] In greater detail, the drain terminals of the third and fourth control transistors 53, 54 are connected to the drain terminals of the first and the second control transistors 51, 52, respectively, and the source terminals of the third and the fourth control transistors 53, 54 are connected to the ground of the readout circuit 30. The gate terminals of the third and the fourth control transistors 53, 54 are connected to the gate terminal of the pick-up transistor 142 and to the gate terminal of the fifth control transistor 55, respectively. The source and drain terminals of the fifth control transistor 55 are connected to the ground of the readout circuit 30 and to the drain terminal of the sixth control transistor 56, respectively. The gate and source terminals of the sixth control transistor 56 are connected to the gate terminal of the injection transistor 140 and to the supply node N.sub.DD, respectively.

[0044] In practice, the third control transistor 53 and the pick-up transistor 142 form a first current mirror, which purely by way of example has a unitary mirroring ratio.

[0045] Consequently, if I.sub.1 is the current that flows in the first control transistor 51, then also the current that flows in the pick-up transistor 142 is equal to the current I.sub.1. In other words, the current drawn by the pick-up transistor 142 from the second internal node N.sub.2, and therefore from the second level-shift transistor 46, is equal to the current I.sub.1.

[0046] The fourth and fifth control transistors 54, 55 form a second current mirror, which purely by way of example has a unitary mirroring ratio. Consequently, if I.sub.2 is the current that flows in the second control transistor 52, then also the current that flows in the fifth control transistor 55 is equal to the current I.sub.2. In addition, the sum of the currents I.sub.1 and I.sub.2 is equal to the current I.sub.tot.

[0047] The sixth control transistor 56 and the injection transistor 140 form a third current mirror, which purely by way of example has a unitary mirroring ratio. Therefore, the current that flows in the injection transistor 140 is equal to the current I.sub.2. In other words, the current injected into the first internal node N.sub.1, and therefore into the first level-shift transistor 44, by the injection transistor 140 is equal to the current I.sub.2.

[0048] In practice, the voltages on the gate terminals of the injection transistor 140 and of the pick-up transistor 142 represent the aforementioned first and second control signals V.sub.C, V.sub.C′.

[0049] In use, the first and the second level-shift transistors 44, 46 operate as voltage followers, since the voltage variations on the respective source terminals follow the voltage variations on the respective gate terminals (and vice versa). Furthermore, in the feedback resistor 22 current does not flow (either in the presence or in the absence of acoustic signals), and the first and the second internal nodes N.sub.1, N.sub.2 are at a voltage equal to V.sub.DD−|V.sub.GS|, where, as mentioned previously, V.sub.GS is the gate-to-source voltage of the MOSFET 18.

[0050] The control circuit 34 functions as a transconductance operational amplifier, which detects the difference between the output biasing voltage V.sub.CMO, present on the third internal node N.sub.3, and the reference voltage V.sub.ref, consequently controlling the injection transistor 140 and the pick-up transistor 142 so as to vary the current that is injected into the first level-shift transistor 44 and the current that is drawn from the second level-shift transistor 46.

[0051] The variations of the current injected into the first level-shift transistor 44 and of the current drawn from the second level-shift transistor 46 cause consequent variations of the voltages of the source terminals of the first and the second level-shift transistors 44, 46. In particular, as the current injected into the first level-shift transistor 44 increases, the voltage on the gate terminal of the latter, and therefore on the first internal node N.sub.1, decreases. Furthermore, as the current tapped from the second level-shift transistor 46 increases, the voltage on the gate terminal of the latter, and therefore on the second internal node N.sub.2, increases. Since, in each of the first and the second level-shift transistors 44, 46, the voltage on the respective gate terminal is equal to the voltage on the respective source terminal (except for the contribution due to the corresponding gate-to-source voltage), the output biasing voltage V.sub.CMO, present on the third internal node N.sub.3, is found to be a combination of the input biasing voltage V.sub.CMI, present on the input node IN, and any one of the gate-to-source voltages of the first and the second level-shift transistors 44, 46.

[0052] FIG. 7 shows an example of the plots of the input biasing voltage V.sub.CMI and of the output biasing voltage V.sub.CMO, as a function of the supply voltage V.sub.DD, as well as the plots of the currents I.sub.1 and I.sub.2, i.e., of the currents that flow in the second level-shift transistor 46 and in the first level-shift transistor 44, respectively. It may be noted that, for relatively low values of the supply voltage V.sub.DD, the current I.sub.2 is to a first approximation negligible, and hence the first level-shift transistor 44 is inhibited, unlike the second level-shift transistor 46, which operates in saturation; instead, for relatively high values of the supply voltage V.sub.DD, the current I.sub.1 becomes to a first approximation negligible, and therefore the second level-shift transistor 46 is inhibited, whereas the first level-shift transistor 44 operates in saturation.

[0053] In practice, thanks to an extremely low threshold voltage, the second level-shift transistor 46 follows, for low values of the supply voltage V.sub.DD, the reference voltage V.sub.ref, varying the voltage on its gate terminal accordingly. In other words, the output biasing voltage V.sub.CMO is imposed by the second level-shift transistor 46, which prevails over the first level-shift transistor 44. In particular, the first level-shift transistor 44 is inhibited as, due to its threshold voltage (for example, with a modulus equal to 650 mV), there is no sufficient voltage difference between its source and gate terminals.

[0054] Next, as the supply voltage V.sub.DD increases, the first level-shift transistor 46 switches on and tends to prevail over the first level-shift transistor 44, feeding back onto its own gate terminal the voltage present on its own source terminal minus the absolute value of its own gate-to-source voltage. In this way, the difficulty of significantly raising, by the second level-shift transistor 46, the voltage on its own gate terminal, is obviated even when the transistor 46 is crossed by a high current. In FIG. 7, the voltage regions in which, the first and the second level-shift transistors 44, 46 prevail are designated by OR2 and OR1, respectively.

[0055] FIG. 7 also shows how the output biasing voltage V.sub.CMO and the reference voltage V.sub.ref are substantially equal, since it is assumed that the gain of the loop that controls the output biasing voltage V.sub.CMO as a function of the difference of the latter with respect to the reference voltage V.sub.ref is high.

[0056] From what has been described and illustrated previously, the advantages that the present solution affords are evident.

[0057] In particular, in the readout circuit 30, the output biasing voltage V.sub.CMO does not follow, but for an approximately constant offset, the supply voltage V.sub.DD. Instead, the output biasing voltage V.sub.CMO is directly proportional to the supply voltage V.sub.DD, which guarantees an increase of the output dynamic range, in addition to a decoupling from the input biasing voltage V.sub.CMI.

[0058] In other words, as the supply voltage V.sub.DD increases, we find a corresponding increase in the AOP.

[0059] In addition, the output biasing voltage V.sub.CMO is set through a closed control loop, hence in a particularly accurate way.

[0060] Moreover, the readout circuit 30 maintains a high input impedance and, for small signals, maintains the same transfer function (understood as ratio between the output voltage V.sub.out and the charge generated by the transducer). In this regard, it can be demonstrated that, in a small-signal regime, V.sub.out=31 q/C.sub.f, where q designates the charge generated by the MEMS transducer 8 and C.sub.f designates the capacitance of the feedback capacitor 20.

[0061] FIG. 8 shows a possible alternative, which is now described limitedly to the differences with respect to what is illustrated in FIG. 6. This alternative does not envisage the use of depletion transistors, and is hence suited to being manufactured in the simplest way in comparison to what is illustrated in FIG. 6, for example by using standard CMOS manufacturing technologies.

[0062] In detail, the second level-shift transistor, here designated by 246, is of the N-channel enhancement-mode type, and hence has a threshold voltage higher than in the case illustrated in FIG. 6. The gate terminal of the second level-shift transistor 246 is connected to a fourth internal node N.sub.4, instead of to the third internal node N.sub.3. In addition, the source terminals of the injection transistor 140 and of the sixth control transistor 56 and the drain terminal of the second level-shift transistor 246 are connected to an additional supply node N.sub.DDls, which is set at an additional supply voltage V.sub.DDls, which is such that V.sub.DDls≥V.sub.DD+ΔV, with ΔV at least equal, for example, to 100 mV. The control generator 154 is interposed between the additional supply node N.sub.DDls and the source terminals of the first and the second control transistors 51, 52.

[0063] Moreover, the readout circuit 30 comprises a first, a second, a third and a fourth additional transistor 201, 202, 203, 204.

[0064] The first additional transistor 201 is a N-channel enhancement-mode MOSFET, the source terminal of which is connected to the ground of the readout circuit 30, and the gate terminal of which is connected to the gate terminal of the third control transistor 53 so as to form a fourth current mirror, which purely by way of example has a unitary mirroring ratio.

[0065] The second, the third and the fourth additional transistors 202, 203, 204 are P-channel enhancement-mode MOSFETs. Furthermore, the second additional transistor 202 is of the type with source terminal connected to the bulk.

[0066] In particular, the gate terminals of the third and of the fourth additional transistors 203, 204 are connected together. Furthermore, the source terminals of the third and of the fourth additional transistors 203, 204 are connected to the additional supply node N.sub.DDls. The drain terminal of the third additional transistor 203 is connected to the drain terminal of the first additional transistor 201, as well as to the gate terminal of the third additional transistor 203, which is hence diode-connected.

[0067] The drain terminal of the fourth additional transistor 204 and the source terminal of the second additional transistor 202 are connected to the fourth internal node N.sub.4. The gate terminal and the drain terminal of the second additional transistor 202 are connected to the third internal node N.sub.3 and to the ground of the readout circuit 30, respectively.

[0068] Thanks to the fourth current mirror, flowing in the first additional transistor 201 is the current I.sub.1, which flows also in the second and fourth additional transistors 202, 204, since the third and fourth additional transistors 203, 204 form a fifth current mirror, which purely by way of example has a unitary mirroring ratio.

[0069] Operatively, the voltage on the fourth internal node N.sub.4 is equal to the voltage present on the second internal node N.sub.2, plus the gate-to-source voltage of the second level-shift transistor 246. Furthermore, the voltage on the third internal node N.sub.3 is equal to the voltage present on the fourth internal node N.sub.4 minus the absolute value of the gate-to-source voltage of the second additional transistor 202, which to a first approximation is equal to the absolute value of the gate-to-source voltage of the second level-shift transistor 246. In this way, the plots of the voltage on the third internal node N.sub.3 and of the currents I.sub.1 and I.sub.2 remain substantially the same as what has been described with reference to the embodiment illustrated in FIG. 6.

[0070] The fact that the additional supply voltage V.sub.DDls is higher than the supply voltage V.sub.DD makes it possible to guarantee a correct drain-to-source voltage of the fourth additional transistor 204, which, as also the other transistors, operates in saturation.

[0071] In conclusion, it is clear that further modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present disclosure, as defined in the annexed claims.

[0072] For instance, the mirroring ratios of one or more of the current mirrors may not be unitary ratios.

[0073] Instead of the MOSFET 18 a circuit including an operational amplifier (not illustrated) may be present.

[0074] Finally, all the MOSFETs may have channels reversed with respect to what has been described.

[0075] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.