CLASS PHI-2 POWER CONVERTER COMPRISING A SELF-OSCILLATING SWITCH CONTROL CIRCUIT

Abstract

A power converter for converting a DC input voltage into an AC output voltage, the power converter having a structure of Phi-2 type, and includes an input terminal for the DC input voltage, an output terminal for the AC output voltage, a power switch equipped with a control electrode, a first electrode and a second electrode linked to a reference potential, the power switch being configured to receive a drive signal at the control electrode, the converter further comprising a self-oscillating circuit, connected between the output terminal and the control electrode, and configured to supply and maintain a sinusoidal drive signal to the power switch from the output voltage.

Claims

1. A power converter for converting a DC input voltage (Vin) into an AC output voltage (Vout), the power converter having a structure of Phi-2 type, and comprising: an input terminal (BEN) for the DC input voltage (Vin), an output terminal (BSO) for the AC output voltage (Vout), a power switch (INT) equipped with a control electrode (G), a first electrode (D) and a second electrode (S) linked to a reference potential (GND), wherein the converter further comprises a self-oscillating circuit, connected between the output terminal (BSO) and the control electrode (G), and configured to supply and maintain a sinusoidal drive signal to the control electrode of the power switch (INT) from the output voltage (Vout).

2. The converter as claimed in claim 1, the self-oscillating circuit comprising a capacitive divider bridge (PDC) connected between the output terminal (BSO) and the reference potential (GND), and further comprising a first inductor (L1) connected on one side to a first midpoint (PM1) of the capacitive divider bridge (PDC) and on the other side to the control electrode (G) via a reactive circuit (CRE).

3. The converter as claimed in claim 2, comprising a second inductor (Lmatch) connected to the output terminal (BSO), a first capacitor (C1) connected between the output terminal (BSO) and the reference potential (GND), the second inductor (Lmatch), the first capacitor (C1) and the first capacitive divider bridge (PDC) being configured to form an “L” configuration impedance matching network for a predefined load value at the output of the converter.

4. The converter as claimed in claim 2, the reactive circuit (CRE) being formed by a second capacitor (C2) connected to the control electrode (G) and by the stray capacitance (Cgs) between the control electrode (G) and the second electrode (S) of the power switch (INT).

5. The converter as claimed in claim 2, the reactive circuit (CRE) comprising at least one series resonant circuit (CRS1, CRS2), connected between the control electrode (G) and the reference potential (GND), and the resonance frequency of which is equal to a corresponding harmonic frequency of the drive signal.

6. The converter as claimed in claim 2, comprising a resistive divider bridge (PDR), connected between the input terminal (BEN) and the reference potential (GND), having a second midpoint (PM2) connected to the first inductor (L2) and to the reactive circuit (CRE), the resistive divider bridge (PDR) being configured to supply a DC component derived from the input voltage (Vin), the DC component being equal to a threshold voltage between the control electrode (G) and the second electrode (S) of the power switch (INT).

Description

[0017] Other features, details and advantages of the invention will emerge on reading the description given with reference to the attached drawings which are given by way of example:

[0018] FIG. 1, already described, represents a Phi-2 class converter according to the state of the art;

[0019] FIG. 2 represents a Phi-2 class converter according to the state of the art, comprising an impedance matching network;

[0020] FIG. 3 represents a first embodiment of a Phi-2 class converter according to the invention;

[0021] FIG. 4 represents a second embodiment of a Phi-2 class converter according to the invention.

[0022] The invention is described in the case where the power switch is a field-effect transistor (for example MOSFET, JFET). The substrate of the transistor can be made of gallium nitride (GaN), of silicon carbide (SiC), or with any other semiconductor material. The drain, the source and the gate mentioned in the description can be designated more generally respectively as a first electrode, a second electrode and a control electrode. The invention can thus also be applied to other types of power switches, for example a transistor of IGBT type, a bipolar transistor or even a thyristor.

[0023] A Phi-2 class converter is generally dimensioned to deliver an output power Pout with a desired load impedance Rdes, from a DC input voltage Vin, with a switching frequency f.sub.switch. The power radiofrequency loads available on the market do not necessarily have a nominal load impedance Rfab equal to the desired load impedance Rdes. In this case, an impedance matching between the desired load impedance Rdes and the nominal load impedance Rfab must thus be performed. In other cases, for a desired load impedance Rdes, it is not possible to dimension a Phi-2 class converter which allows a certain output power value to be obtained. To obtain the desired output power, it is therefore necessary to use another load value and to match the impedance. The impedance matching can even be performed when the desired load Rdes and the nominal load Rfab are theoretically equal, because of the different interfering elements that the circuit can comprise.

[0024] In this case, as FIG. 2 illustrates, it is suitable to insert an “L” configuration impedance matching circuit, comprising an impedance matching inductor Lmatch and an impedance matching capacitor Cmatch.

[0025] The article “Resistance Compression Networks for Radio-Frequency Power Conversion” (Y. Han, O. Leitermann, D. A. Jackson and D. J. Perreault, IEEE Transactions On Power Electronics, Vol. 22, No. 1, January 2007) describes a method for determining an impedance matching circuit.

[0026] FIG. 3 represents a first embodiment of a Phi-2 class converter according to the invention. In the Phi-2 class converter according to the invention, the impedance matching capacitor Cmatch of the “L” configuration impedance matching circuit is replaced by an equivalent network of capacitors C1-C3-C4. The first capacitor C1 is in parallel with the capacitor C3 in series with the capacitor C4. A capacitive divider bridge PDC is obtained by taking a voltage between a first intermediate point PM1, situated between the capacitors C3 and C4, and a reference potential GND (for example a ground). The manufacturer's load Rfab is situated between the output terminal BSO and the reference potential GND. The output voltage Vout can be measured at the terminals of the manufacturer's load Rfab. The capacitive divider bridge PDC and the manufacturer's load Rfab are connected in parallel. Thus, a fraction of the output voltage Vout is taken at the terminals of the capacitor C4. The fraction of the output voltage Vout is calculated in order to supply a voltage level close to the drive voltage of the transistor INT. The output voltage Vout is a sinusoid, which has to be brought to a value that is acceptable by the gate of the transistor INT (approximately 6 V for a GaN transistor), centered around the value of the threshold voltage Vth of the transistor INT.

[0027] A second capacitor C2 is directly connected to the gate G of the transistor INT. The reactive circuit CRE, formed by the first capacitor C1 and by the input capacitance Cgs of the transistor INT, forms another capacitive divider bridge, to further reduce the gate drive voltage. The second capacitor C2 also has a function of filtering of the DC component of the gate voltage Vgs.

[0028] A first inductor L1 is connected to the intermediate point PM1 of the capacitive divider bridge PDC. The first inductor L1 forms an oscillating network with the capacitor C4, the second capacitor C2 and the gate-source capacitance Cgs of the transistor INT. The value of the first inductor L1 is determined such that the oscillation frequency of the oscillating network is equal to the desired switching frequency of the transistor INT. This value will however be able to be corrected, to take account of the dimensioning of the other components. The value of the first inductor L1 is also determined so as to add a phase shift to the output signal, so as to observe the zero-voltage switching (ZVS) condition.

[0029] The voltage Vgs is not linear: it does not increase linearly, as a function of the total load of the gate. The level of the voltage Vgs is equal to the Miller voltage (voltage value corresponding to the Miller plateau), and which designates the voltage necessary to recharge the drain-gate capacitance of the transistor Cgd, also called Miller capacitance. Outside of this level, the voltage Vgs increases, with the same slope before and after the level, proportionally to the total load. Thus, the voltage Vgs obtained on the gate G of the transistor INT cannot be centered around the threshold voltage Vth. In the worst case, the voltage Vgs can be constantly lower than the threshold voltage Vth, which would prevent any switching of the transistor INT.

[0030] To compensate for the nonlinearity of the voltage Vgs, a resistive divider bridge PDR is connected between the input terminal BEN and the reference potential GND. The resistive divider bridge PDR comprises a first resistor R1 in series with a second resistor R2. A second midpoint PM2 is disposed between the first resistor R1 and the second resistor R2. A fraction of the DC input voltage Vin is taken at the second midpoint PM2. This fraction is added to the sinusoidal component extracted from the output voltage Vout. The addition of a DC component to the sinusoidal component provides an assurance of the gate drive signal oscillating about the threshold voltage Vth of the transistor INT.

[0031] The second resistor R2 can be a variable resistor. The adjustment of the value of the second resistor R2 allows the efficiency of the converter to be finely varied.

[0032] The drive circuit of the gate of the transistor INT is therefore self-oscillating in that it creates and maintains the oscillations necessary to the switching of the transistor INT.

[0033] FIG. 4 illustrates a variant of the converter according to the invention.

[0034] The converter according to this variant also comprises a capacitive divider bridge PDC, and a first inductor L1.

[0035] The reactive circuit CRE is composed of at least one series resonant circuit.

[0036] In FIG. 4, two series resonant circuits (CRS1, CRS2) are illustrated, but the presence of a single series resonant circuit can be envisaged. Each of the series resonant circuits is connected between the gate of the transistor INT and the reference potential GND. Each of the series resonant circuits is composed of an inductor (Lh1, Lh2) and a capacitor (Ch1, Ch2). The values of the inductor and of the capacitor of a first series resonant circuit CRS1 are determined such that the resonance frequency of the first series resonant circuit is equal to the frequency of the harmonic of highest amplitude (after that of rank 1, which corresponds to the fundamental component) of the gate voltage of the transistor INT. Thus, the inductor and the capacitor of the first series resonant circuit short-circuit the highest harmonic. Likewise, a second series resonant circuit CRS2 (of rank 2) can be disposed in parallel to the first series resonant circuit CRS1. The values of the inductor and of the capacitor of the second series resonant circuit are determined such that the resonance frequency of the second series resonant circuit is equal to the frequency of the second highest harmonic of the gate voltage of the transistor INT. Other series resonant circuits of the same order can be disposed in parallel. The gate signal is thus rendered more sinusoidal by eliminating the harmonics which distort it, which provokes a more rapid switching on or switching off of the transistor INT, which contributes to enhancing the efficiency of the converter.

[0037] A resistive divider bridge is connected between the input terminal BEN and the reference potential GND, in order to add a DC component and center, if necessary, the sinusoid of the control signal of the gate about the threshold voltage Vth.

[0038] The drive signal is thus primarily composed of its fundamental component, of sinusoidal form. The driving of the gate by a sinusoid allows a better switching of the transistor, and a higher efficiency, to be obtained.

[0039] The converter that is the subject of the invention, according to one or other of the variants, contains only passive components, with no additional DC source. Finally, it contains no transistor other than that necessary to the Phi-2 structure, which avoids having to manage dead times. As a reminder, the management of the dead times is necessary when there are at least two transistors connected in series, in parallel with a voltage source, in order to avoid the presence of short-circuits when two transistors are on at the same time. At high and very high frequency, the switching period is so low that it becomes of the same order of magnitude as the dead times necessary to the correct operation of the circuit, which increases the complexity of the management of the dead times.

[0040] The converter described previously can form part of a DC/DC conversion device by connecting, for example, the output of the converter to a transformation stage, which would itself be connected to a rectifier.

[0041] The following section describes an example of dimensioning of the converter that is the subject of the invention, according to the embodiment illustrated by FIG. 3, for an input voltage Vin of 30 V, an output power of 30 W, and a desired switching frequency f.sub.switch of 40 MHz.

[0042] The dimensioning of the input inductor Lf, of the series resonant network Lr-Cr and of the filter Lmr-Cmr is described in the document “A high-frequency resonant inverter topology with low-voltage stress” (Rivas et al., IEEE Transactions on power electronics, vol. 23, No. 4, July 2008).

[0043] The following are obtained: Lf=50 nH, Lmr=35 nH, Cmr=113 pF, Lr=50 nH, Cr=2 nF.

[0044] The dimensioning of the matching circuit {Lmatch-Cmatch} is described in the article “Resistance Compression Networks for Radio-Frequency Power Conversion” (Y. Han, O. Leitermann, D. A. Jackson and D. J. Perreault, IEEE Transactions On Power Electronics, Vol. 22, No. 1, January 2007).

[0045] The following are obtained: Lmatch=79 nH, Cmatch=165 pF.

[0046] The capacitor Cmatch is divided into C1 parallel with (C3 in series with C4), so as to obtain an impedance for the branch (C3 in series with C4) that is very generously dimensioned (approximately ten times greater) with respect to the output load, in order not to deprive the load of the power that it should receive.

[0047] The capacitive divider bridge PDC must be dimensioned to bring the voltage Vout to within the region of 6 V (the drive voltage of the transistor). The following two dimensioning equations are thus obtained:

[00001]$\begin{array}{cc}\left[\mathrm{Math}.1\right]& \\ \frac{1}{2\pi .Math.f_{\mathrm{switch}}.Math.\left(C3+C4\right)}\text{>>}10.Math.R_{\mathrm{fab}}& \left(1\right)\\ \left[\mathrm{Math}.2\right]& \\ \frac{C3}{C3+C4}>\frac{V_{\mathrm{div}}}{V_{\mathrm{out}}}& \left(2\right)\end{array}$

[0048] In which V.sub.div is equal to the voltage between the first midpoint PM1 and the reference potential GND, and Rfab is the load impedance supplied by the manufacturer.

[0049] The following are found: C3=10 pF, C4=100 pF.

[0050] To find the value of the first inductor L1, the first step is to calculate the equivalent capacitance Ceq of the gate capacitance Cgs and of the second capacitor C2.

[0051] Then, starting from f.sub.switch=f.sub.oscillation (in which f.sub.oscillation is the resonance frequency of the circuit L1-Ceq), the following equation is obtained:

[00002]$\left[\mathrm{Math}.3\right]$$\begin{array}{cc}{f}_{\mathrm{switch}}=\frac{1}{2\pi .Math.\sqrt{L1.Math.\mathrm{Ceq}}}& \left(3\right)\end{array}$

[0052] It is found that L1=200 nH, this value is provisional and will be modified upon the introduction of the second capacitor C2.

[0053] The second capacitor C1 is introduced in order to produce another voltage divider at the gate of the transistor INT. Cgs is given by the datasheet of the transistor INT and the value of the second capacitor C2 is determined by the equation:

[00003]$\left[\mathrm{Math}.4\right]$$\begin{array}{cc}\frac{C2}{C2+\mathrm{Cgs}}=\frac{V_{\mathrm{gs}}}{V_{\mathrm{osc}}}& \left(4\right)\end{array}$

[0054] In which V.sub.gs represents the voltage between the gate and the reference potential GND, and V.sub.osc represents the voltage between the second midpoint PM2 and the reference potential GND.

[0055] C2=300 pF is obtained, and the value of the first inductor L1 is adjusted to 230 nH by using the simulation in order to maintain f.sub.oscillation at 40 MHz.