LAMINATED CELL STRUCTURE AND PREPARATION METHOD THEREOF

Abstract

The invention discloses a laminated cell structure, the laminated cell structure comprising a top cell unit, a bottom cell unit, and an intermediate layer located between the top cell unit and the bottom cell unit; the intermediate layer being configured as a tunnel junction composed of a p.sup.+/n.sup.+ double-layer silicon thin film; the top cell unit comprising an electron transport layer, a perovskite photosensitive layer, a hole transport layer sequentially laminated in the direction from the distance to the vicinity with respect to the intermediate layer, and a front electrode provided on the electron transport layer; and the bottom cell unit being a PERC solar cell. The invention also correspondingly discloses a preparation method for the laminated cell structure. According to the invention, good perovskite cell performance can be obtained by adopting a silicon thin film tunnel junction structure. The laminated cell with the structure has high photoelectric conversion efficiency.

Claims

1. A laminated cell structure, characterized by comprising a top cell unit (1), a bottom cell unit (2), and an intermediate layer unit (3) arranged between the top cell unit (1) and the bottom cell unit (2); wherein the top cell unit (1) comprises an electron transport layer (11), a perovskite photosensitive layer (12), a hole transport layer (13), and a front electrode (17); the electron transport layer (11), the perovskite photosensitive layer (12), and the hole transport layer (13) are sequentially laminated in a direction from the distance to the vicinity with respect to the intermediate layer unit (3), and the hole transport layer (13) is connected with the intermediate layer unit (3); the front electrode (17) is arranged on the electron transport layer (11); the bottom cell unit (2) comprises a passivated contact layer (21), a silicon oxide layer (22), a monocrystalline silicon base layer (23), a rear passivated film layer (24), a rear protective layer (25), and a rear electrode (26) sequentially laminated in a direction from the vicinity to the distance with respect to the intermediate layer unit (3); the passivated contact layer (21), the silicon oxide layer (22), the monocrystalline silicon base layer (23), the rear passivated film layer (24), and the rear protective layer (25) are sequentially laminated in the direction from the vicinity to the distance with respect to the intermediate layer unit (3), and the passivated contact layer (21) is connected with the intermediate layer unit (3); the rear electrode (26) is arranged on the rear protective layer (25); the intermediate layer unit (3) comprises a p.sup.+ silicon thin film layer (31) and an n.sup.+ silicon thin film layer (32), and is configured as a tunnel junction composed of the p.sup.+ silicon thin film layer (31) and the n.sup.+ silicon thin film layer (32).

2. The laminated cell structure according to claim 1, characterized in that the top cell unit (1) further comprises an antireflective layer (14), a transparent conductive layer (15), and a passivated protective film layer (16) arranged on the electron transport layer (11), and the antireflective layer (14), and the transparent conductive layer (15) and the passivated protective film layer (16) are sequentially laminated in a direction from the distance to the vicinity with respect to the electron transport layer (11).

3. The laminated cell structure according to claim 1, characterized in that the hole transport layer (13) is a nickel oxide layer and the electron transport layer (11) is a zinc oxide layer or a lithium fluoride layer.

4. The laminated cell structure according to claim 1, characterized in that the passivated contact layer (21) is an n-type silicon thin film passivated contact layer configured as a textured surface structure.

5. The laminated cell structure according to claim 1, characterized in that the passivated contact layer (21) is formed with an inscribed electrode on its surface facing the intermediate layer unit (3).

6. A preparation method for a laminated cell structure, characterized by comprising the following steps: preparing a bottom cell unit; preparing an intermediate layer unit on the bottom cell unit; the intermediate layer unit being configured as a tunnel junction composed of a p.sup.+ silicon thin film layer and an n.sup.+ silicon thin film layer; and preparing a top cell unit with a perovskite photosensitive layer on the intermediate layer unit.

7. The preparation method for a laminated cell structure according to claim 6, characterized in that the preparing a bottom cell unit specifically comprises the following steps: preparing a textured surface on a front and a back sides of a monocrystalline silicon wafer by using an alkaline solution; respectively forming a first silicon oxide layer and a second silicon oxide layer on the front textured surface and the back textured surface of the monocrystalline silicon wafer; oxidizing and annealing the second silicon oxide layer, and depositing aluminum oxide on the second silicon oxide layer to form a rear passivated film layer; depositing a rear protective layer on the rear passivated film layer, and arranging a rear electrode on the rear protective layer; and depositing a passivated contact layer on the first silicon oxide layer.

8. The preparation method for a laminated cell structure according to claim 7, characterized in that the respectively forming a first silicon oxide layer and a second silicon oxide layer on the front textured surface and the back textured surface of the monocrystalline silicon wafer specifically comprises the following steps: performing phosphorus diffusion on a front textured surface of the monocrystalline silicon wafer to obtain a front textured surface formed with an n-type emitter region; etching and polishing a rear textured surface of the monocrystalline silicon wafer to obtain a rear textured surface with a rear diffusion layer and a side conductive channel removed; and performing thermal oxidation on the monocrystalline silicon wafer in an oxidation furnace, and respectively forming a first silicon oxide layer and a second silicon oxide layer on the front textured surface and the back textured surface of the monocrystalline silicon wafer.

9. The preparation method for a laminated cell structure according to claim 7, characterized in that the preparing an intermediate layer unit on the bottom cell unit is specifically prepared by means of the deposition method, which comprises PVD physical vapor deposition or RPD reactive plasma deposition.

10. The preparation method for a laminated cell structure according to claim 8, characterized in that a textured surface is prepared on the front and back sides of the monocrystalline silicon wafer by using an alkaline solution, the structure of the textured surface being pyramid-shaped.

11. The preparation method for a laminated cell structure according to claim 9, characterized in that after etching and polishing the rear textured surface of the monocrystalline silicon wafer, the method specifically further comprises the following steps: depositing aluminum oxide and silicon nitride on the rear textured surface of the monocrystalline silicon wafer; carrying out laser grooving on the rear textured surface of the monocrystalline silicon wafer, and locally melting the aluminum oxide and silicon nitride layers; printing aluminum paste and silver paste on the rear textured surface of the monocrystalline silicon wafer, and performing sintering; cleaning and oxidizing the front textured surface of the monocrystalline silicon wafer to form a thin oxide layer on the front surface, a thickness of the thin oxide layer being 1-10 nm; and depositing a passivated contact layer on the first silicon oxide layer, wherein the passivated contact layer is n-type doped amorphous or polycrystalline silicon.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0072] In order to explain the technical solutions in the embodiments of the invention more clearly, the following will briefly introduce the drawings needed in the description of the embodiments. Apparently, the drawings in the following description are only some embodiments of the invention. For those of ordinary skills in the art, other drawings can be obtained based on these drawings without creative efforts.

[0073] FIG. 1 is a schematic view of a laminated cell structure provided by an embodiment of the invention;

[0074] FIG. 2 is a flowchart of a laminated cell structure and a preparation method thereof provided by an embodiment of the invention.

[0075] The reference signs in the drawings are indicated as: 1-top cell unit; 11-electron transport layer; 12-perovskite photosensitive layer; 13-hole transport layer; 14-antireflective layer; 15-transparent conductive layer; 16-passivated protective film layer; 17-front electrode; 2-bottom cell unit; 21-passivated contact layer; 22-silicon oxide layer; 23-monocrystalline silicon base layer; 24-rear passivated film layer; 25-rear protective layer; 26-rear electrode; 3-intermediate layer unit; 31-p.sup.+ silicon thin film layer; and 32-n.sup.+ silicon thin film layer.

DESCRIPTION OF THE EMBODIMENTS

[0076] In order to make the object, solutions and advantages of the invention clearer, the solutions in the embodiments of the invention will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the invention. Apparently, the described embodiments are only part of the embodiments of the invention, but not all of the embodiments. Based on the embodiments of the invention, any other embodiment obtained by a person of ordinary skills in the art without involving any creative effort are encompassed within the scope of the invention.

[0077] The application provides a laminated cell structure including a top cell unit 1, a bottom cell unit 2, and an intermediate layer unit 3 arranged between the top cell unit 1 and the bottom cell unit 2.

[0078] The top cell unit 1 includes an electron transport layer 11, a perovskite photosensitive layer 12, a hole transport layer 13, and a front electrode 17.

[0079] The electron transport layer 11, the perovskite photosensitive layer 12, and the hole transport layer 13 are sequentially laminated from the distance to the vicinity with respect to the intermediate layer unit 3, and the hole transport layer 13 is connected with the intermediate layer unit 3; the front electrode 17 is arranged on the electron transport layer 11.

[0080] The bottom cell unit 2 includes a passivated contact layer 21, a silicon oxide layer 22, a monocrystalline silicon base layer 23, a rear passivated film layer 24, a rear protective layer 25, and a rear electrode 26 which are sequentially laminated in a direction from the vicinity to the distance with respect to the intermediate layer.

[0081] The passivated contact layer 21, the silicon oxide layer 22, the monocrystalline silicon base layer 23, the rear passivated film layer 24, and the rear protective layer 25 are sequentially laminated in the direction from the vicinity to the distance with respect to the intermediate layer unit 3. The passivated contact layer 21 is connected with the intermediate layer unit 3; the rear electrode 26 is arranged on the rear protective layer 25.

[0082] The intermediate layer unit 3 includes a p.sup.+ silicon thin film layer 31 and an n.sup.+ silicon thin film layer 32, and is configured as a tunnel junction composed of the p.sup.+ silicon thin film layer 31 and the n.sup.+ silicon thin film layer 32.

[0083] In another implementation mode, the top cell unit 1 further includes an antireflective layer 14, a transparent conductive layer 15, and a passivated protective film layer 16 arranged on the electron transport layer 11, and the antireflective layer 14, the transparent conductive layer 15, and the passivated protective film layer 16 are sequentially laminated in the direction from the distance to the vicinity with respect to the electron transport layer 11.

[0084] In another implementation mode, the hole transport layer 13 is a nickel oxide layer; the electron transport layer 11 is a zinc oxide layer or a lithium fluoride layer.

[0085] In another implementation mode, the passivated contact layer 21 of the bottom cell unit 2 is an n-type silicon thin film passivated contact layer configured as a textured structure.

[0086] In another implementation mode, the passivated contact layer 21 is formed with an inscribed electrode on its surface facing the intermediate layer unit 3.

[0087] The application also provides an embodiment of a preparation method for a cell, which corresponds to the embodiment of the cell structure of the application. As shown in FIG. x, an embodiment of the preparation method may include the following steps:

[0088] S1: preparing a bottom cell unit;

[0089] S2: preparing an intermediate layer unit on the bottom cell unit; the intermediate layer unit being configured as a tunnel junction composed of a p.sup.+ silicon thin film layer and an n.sup.+ silicon thin film layer;

[0090] and S3: preparing a top cell unit with a perovskite photosensitive layer on the intermediate layer unit.

[0091] The preparation of the bottom cell unit may include the following steps:

[0092] preparing a textured surface on the front and back sides of the monocrystalline silicon wafer by using an alkaline solution;

[0093] respectively forming a first silicon oxide layer and a second silicon oxide layer on the front textured surface and the back textured surface of the monocrystalline silicon wafer;

[0094] oxidizing and annealing the second silicon oxide layer, and depositing aluminum oxide on the second silicon oxide layer to form a rear passivated film layer;

[0095] depositing a rear protective layer on the rear passivated film layer, and

[0096] arranging a rear electrode on the rear protective layer;

[0097] depositing a passivated contact layer on the first silicon oxide layer;

[0098] respectively forming a first silicon oxide layer and a second silicon oxide layer on the front textured surface and the back textured surface of the monocrystalline silicon wafer specifically comprises the following steps:

[0099] performing phosphorus diffusion on the front textured surface of the monocrystalline silicon wafer to obtain a front textured surface formed with an n-type emitter region;

[0100] etching and polishing the rear textured surface of the monocrystalline silicon wafer to obtain a rear textured surface with the rear diffusion layer and the side face conductive channel removed;

[0101] and performing thermal oxidation on the monocrystalline silicon wafer in an oxidation furnace, and respectively forming a first silicon oxide layer and a second silicon oxide layer on the front textured surface and the back textured surface of the monocrystalline silicon wafer.

[0102] The front face is cleaned; the front face is oxidized, and a thin oxide layer of 1-10 nm is formed on the front surface; the front passivated contact layer is deposited to form n-type doped amorphous/polycrystalline silicon over the silicon oxide layer.

[0103] An intermediate layer unit is prepared on the bottom cell unit, in particular by a deposition method. The method includes PVD physical vapor deposition or RPD reactive plasma deposition.

[0104] The textured surface is prepared on the front and back sides of the monocrystalline silicon wafer by using an alkaline solution, and the structure of the textured surface is pyramid-shaped.

[0105] After performing etching and polishing on the rear textured surface of the monocrystalline silicon wafer, the method specifically further includes the following steps:

[0106] depositing aluminum oxide and silicon nitride on the rear textured surface of the monocrystalline silicon wafer;

[0107] carrying out laser grooving on the rear textured surface of the monocrystalline silicon wafer, and locally melting the aluminum oxide and silicon nitride layers;

[0108] printing aluminum paste and silver paste on the rear textured surface of the monocrystalline silicon wafer, and performing sintering;

[0109] cleaning and oxidizing the front textured surface of the monocrystalline silicon wafer to form a thin oxide layer on the front surface, wherein the thickness of the thin oxide layer is 1-10 nm; and

[0110] depositing a passivated contact layer on the first silicon oxide layer, wherein the passivated contact layer is n-type doped amorphous or polycrystalline silicon.

[0111] The solutions of the application are further described below with reference to some examples.

Example 1

[0112] The example of the invention provides a laminated cell structure which, as shown in FIG. 1, includes a top cell unit 1, a bottom cell unit 2, and an intermediate layer unit 3 between the top cell unit 1 and the bottom cell unit 2; the intermediate layer unit 3 is configured as a tunnel junction composed of a p.sup.+/n.sup.+ double-layer silicon thin film, specifically including a p.sup.+ silicon thin film layer 31 and an n.sup.+ silicon thin film layer 32;

[0113] the top cell unit 1 includes an electron transport layer 11, a perovskite photosensitive layer 12, a hole transport layer 13 sequentially laminated in a direction from the distance to the vicinity with respect to the intermediate layer unit 3, and a front electrode is provided on the electron transport layer 11;

[0114] the bottom cell unit 2 is a PERC solar cell.

[0115] In the embodiment of the invention, the top cell unit 1 further includes an antireflective layer 14, a transparent conductive layer 15, and a passivated protective film layer 16 sequentially laminated in the direction from the distance to the vicinity with respect to the electron transport layer. The front electrode 17 can be one or more of gold, silver, copper and aluminum; the antireflective layer 14 can be one or more of silicon oxide, silicon nitride, silicon oxynitride and MgF; the transparent conductive layer 15 can be one or more of zinc oxide, tin oxide, molybdenum oxide and indium oxide; the passivated protective film layer 16 is a C60 material; the electron transport layer 11 is a LiF layer; the hole transport layer 13 is Spiro-MeOTAD.

[0116] Further, the bottom cell unit 2 includes a passivated contact layer 21, a silicon oxide layer 22, a monocrystalline silicon base layer 23, a rear passivated film layer 24, a rear protective layer 25, and a rear electrode 26 sequentially laminated in a direction from the vicinity to the distance with respect to the intermediate layer unit 3.

[0117] The hole transport layer 13 is a nickel oxide layer; the electron transport layer 11 is a lithium fluoride layer, and optionally a zinc oxide layer. The passivated contact layer 21 of the bottom cell unit 2 is an n-type silicon thin film passivated contact layer configured as a textured structure. The passivated contact layer 21 is formed with an inscribed electrode on its surface facing the intermediate layer unit 3.

[0118] The rear passivated film layer 24 includes an aluminum oxide layer and a silicon oxide layer, and a p.sup.++ local area rear field layer is further provided on the lower surface of the p type monocrystalline silicon base layer. The rear protective layer 25 is a silicon nitride layer; the rear electrode 26 may be one or more of gold, silver, copper, and aluminum.

Embodiment 2

[0119] The embodiment of the invention provides a preparation method for the laminated cell structure, which includes the following steps:

[0120] providing a PERC solar cell;

[0121] forming an intermediate layer on the PERC solar cell; the intermediate layer being configured as a tunnel junction composed of a p.sup.+/n.sup.+ double-layer silicon thin film;

[0122] forming a top cell unit with a perovskite photosensitive layer on the intermediate layer;

[0123] and the top cell unit including an electron transport layer, a perovskite photosensitive layer, a hole transport layer sequentially laminated in a direction from the distance to the vicinity with respect to the intermediate layer, and a front electrode deposited on the electron transport layer.

[0124] As a further improvement of the implementation of the invention, the intermediate layer formed on the PERC solar cell is specifically formed by means of a deposition method, including PVD physical vapor deposition or RPD reactive plasma deposition.

[0125] As a further improvement of the implementation of the invention, the front and back sides of the intermediate layer are textured to produce a pyramid-shaped textured structure.

[0126] As a further improvement of the implementation of the invention, providing the PERC solar cell includes the following specific steps:

[0127] S101, texturing the front and back sides of the monocrystalline silicon wafer by using an alkaline solution to prepare a textured surface structure with the edge length of 1-10 μm of a pyramid base;

[0128] S102, performing phosphorus diffusion on the front side of the monocrystalline silicon wafer to form a front n-type emitter region;

[0129] S103, etching and polishing the rear-side of the monocrystalline silicon wafer by using an acid or alkali solution to remove a rear diffusion layer and a side conductive channel;

[0130] S104, performing thermal oxidation on the monocrystalline silicon wafer in an oxidation furnace to form a silicon oxide layer on the front and back sides;

[0131] S105, performing oxidizing and annealing on the rear-side, and depositing an aluminum oxide passivated layer on the rear-side;

[0132] S106, depositing a protective layer on the rear-side after annealing;

[0133] and S107, preparing a rear electrode.

[0134] As a further improvement of the implementation of the invention, after etching and polishing the rear-side, the method specifically includes the following steps:

[0135] depositing aluminum oxide and silicon nitride on the rear-side; carrying out laser grooving on the rear-side, and locally melting the aluminum oxide and silicon nitride layers; printing the rear-side with aluminum paste and silver paste, and sintering;

[0136] and cleaning the front side; oxidizing the front side, and forming a thin oxide layer of 1-10 nm on the front surface; depositing the front passivated contact layer to form n-type doped amorphous/polycrystalline silicon over the silicon oxide layer.

[0137] As a further improvement of the implementation of the invention, the antireflective layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, and magnesium fluoride.

[0138] As a further improvement of the implementation of the invention, the rear passivated film layer includes an aluminum oxide layer and a silicon oxide layer arranged in a laminating manner.

[0139] The invention has the beneficial effects as follows:

[0140] 1. according to the invention, the alkaline made texture with a pyramid textured surface structure is adopted on the surface of the bottom cell so that the problem of poor planar light trapping effect is overcome, and the optical performance of the cell can be greatly improved;

[0141] 2. according to the invention, the bottom cell adopts the PERC cell, and it can upgrade the industry without interruptions, and realizes low-cost mass production of the cell with a laminated structure;

[0142] 3. according to the invention, when the perovskite cell and the crystalline silicon solar cell compose the 2T laminated solar cell, the tunnel junction is adopted as the linking layer of the two cells, and the technical defects that special deposition equipment is needed or the perovskite cell prepared on the TCO is seriously uneven and poor in performance in the prior art are overcome.

[0143] All of the alternative technical solutions described above may be used in any combination to form alternative embodiments of the invention and will not be discussed in detail herein.

[0144] The above are only preferred embodiments of the invention and are not intended to limit the invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the invention shall be encompassed in the scope of the invention.