Abstract
An optoelectronic semiconductor chip comprises a semiconductor layer sequence and several semiconductor structures having in each case one active region. The active regions may be designed for the emission and/or absorption of electromagnetic radiation. The active regions of different semiconductor structures may not be connected to one another. The semiconductor structures may be designed as a nanorod or a microrod. The semiconductor structures may be embedded in the semiconductor layer sequence.
Claims
1. An optoelectronic semiconductor chip comprising: a semiconductor layer sequence; and a plurality of semiconductor structures having a plurality of active regions; wherein: the plurality of active regions are configured for the emission and/or absorption of electromagnetic radiation; the plurality of active regions are not connected to each other; and the semiconductor structures are formed as nanorods, microrods, or combinations thereof; the semiconductor structures are embedded in the semiconductor layer sequence.
2. The optoelectronic semiconductor chip according to claim 1, wherein: the semiconductor structures are conversion elements; the semiconductor layer sequence comprises an active layer configured to generate or absorb a primary radiation; the conversion elements are configured to convert the primary radiation into a secondary radiation or to convert a secondary radiation into the primary radiation.
3. The optoelectronic semiconductor chip according to claim 1, wherein the semiconductor structures are epitaxially overgrown with the semiconductor layer sequence.
4. The optoelectronic semiconductor chip according to claim 2, wherein the semiconductor structures are arranged between the active layer and a growth substrate of the semiconductor layer sequence.
5. The optoelectronic semiconductor chip according to claim 2, wherein: the semiconductor chip is free of a growth substrate of the semiconductor layer sequence; the semiconductor chip comprises a carrier on which the semiconductor layer sequence is arranged; the active layer is arranged between the carrier and the semiconductor structures.
6. The optoelectronic semiconductor chip according to claim 1, wherein the semiconductor structures each narrow along a longitudinal axis of the semiconductor structure.
7. The optoelectronic semiconductor chip according to claim 1, wherein the semiconductor chip comprises a plurality of individually and independently controllable pixels; and different semiconductor structures are assigned to different pixels.
8. The optoelectronic semiconductor chip according to claim 2, wherein the active layer comprises a plurality of elevations and each elevation is associated with a semiconductor structure.
9. A method of manufacturing an optoelectronic semiconductor chip, wherein the method comprises: providing a growth substrate having a growth side; growing semiconductor structures each having an active region on the growth side; and growing a semiconductor layer sequence on the growth side; wherein: each semiconductor structure is a nanorod or a microrod; the active regions are each configured to emit and/or absorb electromagnetic radiation; the active regions are not connected to each other; the semiconductor structures are embedded in the semiconductor layer sequence; the semiconductor structures are conversion elements; the semiconductor layer sequence comprises an active layer configured to generate or absorb a primary radiation; the conversion elements are configured to convert the primary radiation into a secondary radiation; and the active layer comprises a plurality of elevations and each elevation is associated with a semiconductor structure.
10. The method according to claim 9, wherein the growing the semiconductor layer sequence on the growth side comprises overgrowing the semiconductor structures with the semiconductor layer sequence.
11. An optoelectronic semiconductor chip comprising: a semiconductor layer sequence; and a plurality of semiconductor structures each having an active region; wherein: the active regions are configured for the emission and/or absorption of electromagnetic radiation; the active regions are not connected to each other; the semiconductor structures are formed as nanorods, microrods, or combinations thereof; the semiconductor structures are embedded in the semiconductor layer sequence; the semiconductor structures are conversion elements; the semiconductor layer sequence comprises an active layer configured to generate or absorb a primary radiation; the conversion elements are configured to convert the primary radiation into a secondary radiation or to convert a secondary radiation into the primary radiation; and the active layer comprises a plurality of elevations and each elevation is associated with a semiconductor structure.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0039] In the following, an optoelectronic semiconductor chip described herein and a method for producing an optoelectronic semiconductor chip described herein are explained in more detail with reference to drawings based on non-limiting embodiments. Identical reference signs thereby specify identical elements in the individual figures. However, no references to scale are shown; rather, individual elements may be shown exaggeratedly large for better understanding.
[0040] FIGS. 1A, 1B, 1C, 1E, 3A, 3B, 5A, 5B, 9 exemplary embodiments of the optoelectronic semiconductor chip in various views,
[0041] FIGS. 2A to 2I, 4A to 4F, 6A to 6E positions in various exemplary embodiments of the method for producing an optoelectronic semiconductor chip,
[0042] FIGS. 1D and 7 exemplary embodiments of semiconductor structures in detailed views,
[0043] FIGS. 8A to 8D positions in another exemplary embodiment of the method for producing an optoelectronic semiconductor chip, and an exemplary embodiment of an optoelectronic semiconductor chip.
DETAILED DESCRIPTION
[0044] In FIGS. 1A to 1C, a first exemplary embodiment of the optoelectronic semiconductor chip 100 is shown in perspective views and side views. The semiconductor chip 100 includes a growth substrate 3, for example, a sapphire substrate. An auxiliary layer 13 is grown on the growth substrate 3. The auxiliary layer 13 is a semiconductor layer and is based on GaN, for example. Semiconductor structures 21, 22 in the form of nanorods or microrods are grown on the auxiliary layer 13. The semiconductor structures 21, 22 are conversion elements. First semiconductor structures 21 differ from second semiconductor structures 22, for example, in terms of conversion characteristics. The semiconductor structures 21, 22 are based on a nitride compound semiconductor material, for example.
[0045] The semiconductor structures 21, 22 are overgrown with a semiconductor layer sequence 1 based, for example, on AlInGaN. The semiconductor layer sequence 1 includes a first semiconductor layer 11. The first semiconductor layer 11 is, for example, n-doped. Downstream of the first semiconductor layer 11 is an active layer 10 in the form of a multi quantum well, MQW. In turn, a second semiconductor layer 12, which is p-doped, for example, is arranged downstream of the active layer 10.
[0046] Further shown in FIGS. 1A to 1C is a first contact element 41 for contacting the first semiconductor layer 11 and a second contact element 42 for contacting the second semiconductor layer 12. Both contact elements 41, 42 are arranged on a side of the semiconductor layer sequence 1 facing away from the growth substrate 3. The first contact element 41 is arranged in a recess of the semiconductor layer sequence 1 in which the first semiconductor layer 11 is exposed. The contact elements 41, 42 can be contacted with contact wires 43 from a side opposite to the growth substrate 3. The semiconductor chip 100 of FIGS. 1A to 1C is in particular a so-called sapphire chip.
[0047] In FIG. 1D, a detailed view of a first semiconductor structure 21 is shown. It can be seen that the first semiconductor structure 21 comprises a first semiconductor section 211 in the form of a core. The first semiconductor section 211 is encased with an active region 210. The active region 210 is for absorbing and/or emitting electromagnetic radiation. The active region 210 is encased by a second semiconductor section 212 in the form of a layer. Also shown in FIG. 1 are the remnants of a mask 25 used to grow the first semiconductor structures 21.
[0048] In FIG. 1E, a second exemplary embodiment of the optoelectronic semiconductor chip 100 is shown. Again, this is a sapphire chip. In contrast to FIGS. 1A to 1C, the semiconductor structures 21, 22 formed as conversion elements are now embedded in the semiconductor layer sequence 1 on a side of the active layer 10 facing away from the growth substrate 3. A mirror 7, for example a Bragg mirror, is arranged on a side of the growth substrate 3 facing away from the semiconductor layer sequence 1. Such a mirror 7 may also be provided in the exemplary embodiment of FIGS. 1A to 1C.
[0049] In the FIGS. 2A to 2I, various positions in a first exemplary embodiment of the method for producing the optoelectronic semiconductor chip of FIGS. 1A to 1C are shown.
[0050] In FIG. 2A, a growth substrate 3 with an auxiliary layer 13 is first provided. The auxiliary layer 13 is a semiconductor layer and is epitaxially grown on a growth side 31 of the growth substrate 3.
[0051] In FIG. 2B, a first semiconductor structure 21 in the form of a nanorod or microrod is grown on the growth side 31 of the growth substrate 3. For this purpose, a mask 25 was first applied to the growth side 31. The mask 25 may be formed, for example, with an electrically insulating material, for example, with a photoresist material and/or with a silicon oxide and/or with a silicon nitride. The mask 25 was then patterned by bringing in holes in the mask 25. The size of the holes in the mask 25 thereby defines the diameter of the semiconductor structures that are later formed. The first semiconductor structures 21 were then grown within the holes. These are, for example, green conversion elements.
[0052] In FIG. 2C the mask 25 is again structured with holes. Within the additional holes, second semiconductor structures 22 have again been grown in the form of nanorods or microrods. For the second semiconductor structures 22, for example, the diameters are chosen differently than for the first semiconductor structures 21. For example, these are red conversion elements. The first semiconductor structures 21 are coated with a passivation 26, for example SiO.sub.2 or SiN. Other than shown in FIGS. 2B and 2C, the first semiconductor structures 21 and the second semiconductor structures 22 can also be grown simultaneously.
[0053] In the FIG. 2D the position of FIG. 2C is shown again in perspective view and cross-sectional view.
[0054] In the FIGS. 2E to 2G, it is shown how the semiconductor structures 21, 22 are first overgrown with a first semiconductor layer 11, then with an active layer 10 and then with a second semiconductor layer 12, so that a semiconductor layer sequence 1 is formed in which the semiconductor structures 21, 22 are embedded. The first semiconductor layer 11 may, for example, comprise or consist of a mirror layer, in particular a Bragg mirror.
[0055] In FIGS. 2H and 2I, it is shown how the semiconductor layers 11, 12 are subsequently contacted with contact elements 41, 42.
[0056] In the FIGS. 3A and 3B, exemplary embodiment of the optoelectronic semiconductor chip 100 are shown. This semiconductor chip 100 is a so-called flip chip. The contact elements 41, 42 for contacting the semiconductor layer sequence 1 are arranged on a side of the semiconductor layer sequence 1 facing away from the growth substrate 3. A contact layer 6 for contacting the second semiconductor layer 12 and a mirror 7 are arranged between the semiconductor layer sequence 1 and the contact elements 41, 42. The contact layer 6 is electrically conductively connected to a second electrode 420. The first semiconductor layer 11 is connected to a first electrode 410 by vias 411 extending through the second semiconductor layer 12 and the active layer 10. Both electrodes 410, 420 are arranged on the same side of the semiconductor layer sequence 1. An insulating layer 8 is arranged on the electrodes 410, 420. The electrodes 410, 420 are electrically conductively connected to the contact elements 41, 42 through the insulation layer 8.
[0057] In FIGS. 4A to 4F, various positions of an exemplary embodiment for producing the semiconductor chip 100 of FIGS. 3A and 3B are shown. First, for example, the method as explained in relation with FIGS. 2A to 2G is carried out. The position shown in the FIG. 4A follows the position shown in the FIG. 2G.
[0058] In the FIG. 4A, openings are brought into the semiconductor layer sequence 1 from a side of the semiconductor layer sequence 1 facing away from the growth substrate 3, which extend through the second semiconductor layer 12 and the active layer 10 into the first semiconductor layer 11 and lead into the first semiconductor layer 11. Subsequently, a contact layer 6, for example made of silver, (FIG. 4B) and a mirror 7, for example made of metal, (FIG. 4C) are deposited on the second semiconductor layer 12. The openings are filled with an electrically conductive material, such as a metal (FIG. 4C). This creates vias 411 for contacting the first semiconductor layer 11. Electrodes 410, 420 are applied to the mirror 7 (FIG. 4D). The first electrode 410 is electrically conductively connected to the vias 411. The second electrode 420 is electrically conductively connected to the contact layer 6 via holes in the mirror 7. In FIG. 4E, an insulation layer 8 is applied to the electrodes 410, 420. The insulation layer 8 comprises, for example, silicon oxide or silicon nitride. In FIG. 4F, contact elements 41, 42 are then applied to a side of the insulation layer 8 facing away from the growth substrate 3.
[0059] In the FIGS. 5A and 5B, a third embodiment of the optoelectronic semiconductor chip 100 is shown. Unlike in the previous exemplary embodiments, the growth substrate is now detached. For this purpose, a carrier 5, for example a silicon carrier, is additionally applied to a side of the second semiconductor layer 12 facing away from the active layer 10. A mirror 7, which also serves as a second electrode 420 for contacting the second semiconductor layer 12, is also provided between the second semiconductor layer 12 and the carrier 5. A first electrode 410 is applied to a side of the second electrode 420 facing away from the semiconductor layer sequence 1. The two electrodes 410, 420 are separated from each other by an insulation layer 8 and electrically insulated. The first electrode 410 is electrically conductively connected to the first semiconductor layer 11 by vias 411 which extend through the insulation layer 8, the second electrode 24, the second semiconductor layer 12 and the active layer 10 into the first semiconductor layer 11. The carrier 5 is applied to the first electrode 410.
[0060] A first contact element 41 is applied to a side of the carrier 5 facing away from the semiconductor layer sequence 1. In this case, the carrier 5 is electrically conductive.
[0061] A recess is also brought into the semiconductor layer sequence 1, which extends from a side of the semiconductor layer sequence 1 facing away from the carrier 5 to the second electrode 420. A second contact element 42 is provided in the recess for electrically contacting the second electrode 420. The second contact element 42 can be electrically contacted with a contact wire 43 from a side of the semiconductor layer sequence 1 facing away from the carrier 5 (FIG. 5B).
[0062] In the FIGS. 6A to 6B, various positions in an exemplary embodiment for producing the optoelectronic semiconductor chip according to FIGS. 5A and 5B are shown. First, for example, the method according to steps 2A to 2G was again carried out. The position of the FIG. 6A follows the position of the FIG. 2G.
[0063] In the FIG. 6A, openings are first brought into the semiconductor layer sequence 1 from a side facing away from the growth substrate 3. Also, a mirror 7, which also forms a second electrode 420, is provided on the second semiconductor layer 12. An insulating layer 8 is applied to the mirror 7 (FIG. 6B). A first electrode 410 is applied to the insulating layer 8 (FIG. 6C). Furthermore, the openings are filled with an electrically conductive material which is electrically conductively connected to the first electrode 410. As a result, vias 411 are formed in the semiconductor layer sequence 1. In FIG. 6D, a carrier 5, which is electrically conductively connected to the first electrode 410, is applied to the first electrode 410. The growth substrate 3 is then removed (FIG. 6E).
[0064] In the FIG. 7, various exemplary embodiments of the semiconductor structures are shown. The semiconductor structures may be core-shell rods that are, for example, cylindrical, pyramidal, or obelisk-shaped. The active regions 210 of the semiconductor structures may each be in the form of a multi quantum well.
[0065] FIG. 8A shows a first position in a further exemplary embodiment of the method for producing an optoelectronic semiconductor chip. A first part of a semiconductor layer sequence including an active layer 10 is grown on a growth substrate 3.
[0066] In FIG. 8B, a second position of the method is shown, in which the semiconductor layer sequence is patterned together with the active layer 10. In this case, the active layer 10 is removed in some regions. This is achieved, for example, by an etching process using an etching mask.
[0067] In the third position of FIG. 8C, semiconductor structures 21, 22 in the form of nanorods or microrods are grown on the rest of the semiconductor layer sequence. The semiconductor structures 21, 22 are conversion elements for converting the primary radiation emitted from the active layer 10. The semiconductor structures 21, 22 are grown both in the regions where the active 10 has been removed and in the remaining regions. In the regions where the active layer 10 has been removed, the semiconductor structures 21, 22 are located at the same level as the active layer 10 and, in particular, are located in a plane defined by the active layer 10.
[0068] In the FIG. 8D, a fourth position of the method, in which the semiconductor structures 21, 22 are overgrown with further semiconductor material and the semiconductor layer sequence 1 is completed, is shown. FIG. 8D simultaneously shows an exemplary embodiment of a finished optoelectronic semiconductor chip 100.
[0069] The semiconductor chip 100 of FIG. 8D comprises a segmented active layer 10. Each segment of the active layer 10 represents, for example, a pixel. These are, for example, individually and independently controllable. The primary radiation emitted by the segments of the active layer 10 is converted by semiconductor structures 21, 22 arranged above the segments. The semiconductor structures 21, 22 laterally adjacent to the segments of the active layer 10 convert the laterally emitted primary radiation.
[0070] In the FIG. 9, another exemplary embodiment of an optoelectronic semiconductor chip 100 is shown. The semiconductor chip 100 comprises only a single, continuous and uninterrupted active layer 10, but this does not extend to the lateral boundary of the semiconductor layer sequence 1, but is laterally surrounded by semiconductor structures 21, 22 which convert laterally emitted primary radiation. Above the active layer 10, on a side of the active layer 10 facing away from the growth substrate 3, further semiconductor structures 21, 22 are provided for converting the emitted primary radiation.
[0071] The invention is not limited to the exemplary embodiments by the description thereof. Rather, the invention encompasses any new feature as well as any combination of features, which in particular includes any combination of features in the patent claims, even if these features or this combination itself are not explicitly specified in the patent claims or exemplary embodiments.
LIST OF REFERENCE SIGNS
[0072] 1 semiconductor layer sequence
[0073] 3 growth substrate
[0074] 6 contact layer
[0075] 7 mirror
[0076] 8 insulation layer
[0077] 10 active layer
[0078] 11 first semiconductor layer
[0079] 12 second semiconductor layer
[0080] 13 auxiliary layer
[0081] 21 first conversion element
[0082] 22 second conversion element
[0083] 25 mask
[0084] 26 passivation
[0085] 31 growth side
[0086] 41 first contact element
[0087] 42 second contact element
[0088] 43 contact wire
[0089] 100 optoelectronic semiconductor chip
[0090] 210 active region
[0091] 211 semiconductor layer
[0092] 212 semiconductor layer
[0093] 410 first electrode
[0094] 411 via
[0095] 420 second electrode
