Circuit arrangement for combined protection of a load from temporary and transient overvoltages

Abstract

The invention relates to a circuit arrangement for combined protection of a load from temporary and transient overvoltages with emergency operation of the load in the presence of a temporary overvoltage and with integrated follow current limitation, wherein a first surge arrester, in particular a spark gap or a varistor, is provided between network-side input terminals and a second surge arrester, in particular a varistor, is provided between load-side output terminals for follow current limitation. According to the invention, at least one controlled semiconductor switch is provided in each case in the series branch between the input terminal and the output terminal and in the output-side parallel branch, wherein a mechanical switch and a series capacitance are connected in parallel with the semiconductor switch in the series branch. Furthermore, the semiconductor switch in the parallel branch is part of a series circuit comprising a parallel circuit comprising a second surge arrester and a parallel capacitance. A series inductance is provided in the series branch between the input terminal and the parallel circuit comprising the series capacitance, the controlled semiconductor switch and the mechanical switch. A microcontroller for controlling the semiconductor switches is also present, wherein the microcontroller is connected to a current detector in the series branch.

Claims

1. A circuit arrangement for combined protection of a load from temporary and transient overvoltages with emergency operation of the load in the presence of a temporary overvoltage and with integrated follow current limitation, wherein a first surge arrester (1), in particular a spark gap or a varistor, is provided between network-side input terminals (E) and a second surge arrester (2), in particular a varistor, is provided between load-side output terminals (A) for follow current limitation, characterized in that a first controlled semiconductor switch (HLLängs) is provided in the series branch between the input terminal and the output terminal (E; A) and a second controlled semiconductor switch (HLQuer) is provided in an output-side parallel branch, wherein a mechanical switch (S) and a series capacitance (CLängs) are connected in parallel with the first controlled semiconductor switch (HLLängs) in the series branch, furthermore the second controlled semiconductor switch (HLQuer) in the parallel branch is part of a series circuit comprising a parallel circuit of the second surge arrester (2) and a parallel capacitance (CQuer), with a series inductance (L) in the series branch between the input terminal (E) and the parallel circuit of the series capacitance (CLängs), the first controlled semiconductor switch (HLLängs) and the mechanical switch (S), as well as with a microcontroller (μC) for controlling the first controlled semiconductor switch and the second controlled semiconductor switch, wherein the microcontroller (μC) is connected to a current detector (SD) in the series branch.

2. The circuit arrangement according to claim 1, characterized in that for overvoltage detection, the microcontroller (μC) is connected to the input terminals (E) so as to receive the respective input voltage value.

3. The circuit arrangement according to claim 1, characterized in that a device for detecting zero crossing is provided, on the basis of which an in-phase connection of the semiconductor switches may be performed.

4. The circuit arrangement according to claim 1, characterized in that the control of the first controlled semiconductor switch (HL.sub.Längs) in the series branch is performed via a pulse transformer.

5. The circuit arrangement according to claim 1, characterized in that when a temporary overvoltage (TOV) is detected, the control of the second controlled semiconductor switch (HL.sub.Quer) in the parallel branch is performed actively by means of a pulse transformer, and when transient overvoltages are detected, the control is performed passively via TOV diodes, wherein the passive control is given as from a voltage which is above the diode voltage.

6. The circuit arrangement according to claim 1, characterized in that for detecting the output voltage, the microcontroller (μC) is connected to the output terminal (A) so as to provide a logic signal corresponding to the respective load ratio.

7. The circuit arrangement according to claim 1, characterized in that on the basis of the values obtained by the current detector (SD), an additional connection of the mechanical switch (S) is performed for avoiding the first controlled semiconductor switch in the series branch (HL.sub.Längs) to be overloaded.

8. The circuit arrangement according to claim 1, characterized in that the series and parallel capacitances (C.sub.Längs/C.sub.Quer) form a capacitive voltage divider so as to be able to continue the operation of small loads coupled to the output terminals (A) also in the case of temporary overvoltages (TOV).

Description

(1) The invention will be explained in more detail below on the basis of an exemplary embodiment and a FIGURE.

(2) The FIGURE shows a principle circuit diagram of the arrangement according to the invention for combined protection of a load from temporary and transient overvoltages with the option of the emergency operation of the load in the presence of a temporary overvoltage together with an integrated follow current limitation.

(3) As represented in the FIGURE, a first known surge arrester, in particular formed as a spark gap or a varistor, is located between the input terminals E. This quasi upstream first surge arrester takes the majority of occurring surge currents and is configured for the maximum TOV voltage to be expected. Surge currents of a smaller amplitude, however, are taken by the semiconductor switches HL.sub.Quer in the parallel branch, and namely so long until the semiconductor switches HL.sub.Längs in the series branch are switched off.

(4) A series inductance L is situated in the series branch between the input terminals and the output terminals, as well as a parallel circuit comprising the series capacitance C.sub.Längs, a mechanical switch S as well as the already mentioned semiconductor switches HL.sub.Längs in the form of, for example, two semiconductors connected in parallel. Due to the low power loss, a combination of a mechanical switch, MOSFET and IGBT is particularly advantageous here.

(5) The parallel branch that can be recognized in the FIGURE at the output terminals comprises a series circuit of semiconductor switches HL.sub.Quer as well as a parallel circuit as an integral part of the series circuit with a second surge arrester formed as a varistor 2 for follow current limitation, as well as a parallel capacitance C.sub.Quer.

(6) A microcontroller μC serves for controlling the semiconductor switches in the series branch HL.sub.Längs as well as of the semiconductor switches in the parallel branch HL.sub.Quer.

(7) Furthermore, a current detector SD is present which leads to a corresponding input of the microcontroller.

(8) Furthermore, the microcontroller has inputs serving the purpose of detecting input voltages as well as detecting output voltages.

(9) When load currents exceeding a certain set point are detected, the mechanical switch S may be connected in addition in the continuous operation with the aid of the current detector SD in order to relieve the semiconductor switch HL.sub.Längs.

(10) In order to enable an in-phase connection, zero crossing detection is provided according to the invention. This prevents too high inrush currents which otherwise would damage the employed semiconductor switches or reduce the lifetime thereof.

(11) The voltage detection at the input enables temporary but also transient voltages to be detected first and to be able to respond while referring to the microcontroller and its internal program. The control of the series semiconductors HL.sub.Längs is preferably performed via a pulse transformer arrangement, wherein switching times and the energy turnover can be reduced.

(12) In the event of temporary overvoltages, the control of the semiconductor switches in the parallel branch HL.sub.Quer is performed actively via a pulse transformer, however, in the event of transient overvoltages, passively via the use of TVS diodes. The passive control in the parallel branch is active whenever the control via the pulse transformer is deactivated and a voltage higher than the TVS diode voltage is present. This is the case in transient overvoltage events and also at the beginning of a temporary overvoltage, for example, when a temporary overvoltage is coupled into the circuit arrangement until it is detected by the microcontroller.

(13) Basically, the detection of transient overvoltage events is performed by means of the microcontroller, which, however, has a response time that can hardly be influenced. In this case, a very high current can flow through the semiconductor switch in the series direction.

(14) Via a passive TOV voltage detection by means of a diode chain which serves the purpose of detecting input voltages, an immediate control of the semiconductor switch in the series branch HL.sub.Längs may be performed quasi while bypassing the microcontroller. A faster detection and switch-off of the semiconductor switch in the series branch HL.sub.Längs allow for significantly higher surge currents to be carried.

(15) Since mechanical switches on the basis of a relay likewise have a limited response time, for example, of between 2 and 8 ms, a solution needs to be created to rapidly respond to transient overvoltage events. In this respect, the series inductance L, for example, L=20 μH, is used. This decoupling inductance limits the relay current so that damages are avoided and relieves the parallel semiconductor.

(16) The use of capacitors according to the exemplary embodiment allows an emergency operation to be ensured at a constant power. In case of, for instance, C.sub.Längs=5 μF, a 150 W load may be operated at the output even when a switch-off, i.e. a separation from the mains caused by TOV is performed.

(17) In the event of temporary overvoltages originating from a loss of neutral conductors, the load conditions in the phases must be taken in consideration.

(18) The circuit arrangement according the exemplary embodiment may in this respect also be realized to be three-phase or multi-phase. For an affective protection against transient overvoltages, switching times of the series switch HL.sub.Längs of below 500 ns are desirable.

(19) The operating modes of the presented arrangement will be briefly summarized below.

(20) During continuous operation at a load of, by way of example, <6 A and a voltage U.sub.TOV>340 V, usually only the semiconductor switch in the series branch is active so as to be able to quickly respond to a potential interruption of neutral conductors.

(21) At a load of >6 A and U.sub.TOV>340 V, the semiconductor switch HL.sub.Längs and the mechanical switch S are activated simultaneously so as to reduce the power loss in the continuous operation. The switching dynamics of the mechanical switch S may be considered at about 340 V as being sufficient for the load protection. An additional connection is only performed in the voltage zero crossing. The switching of the mechanical switch S may be realized in a currentless manner by the parallel semiconductor switch HL.sub.Längs, which increases the lifetime of the switch.

(22) When a transient overvoltage occurs, the upstream surge arrester 1 takes the majority of the surge current. Surge currents of a smaller amplitude are taken by the semiconductor switch HL.sub.Quer in the parallel branch until a switch-off takes place. Here, the following two cases must be distinguished.

(23) In the first case, only the semiconductor switch in the series branch is active. The series member may be closed rapidly, i.e. the surge arrester 1 takes the full surge current.

(24) In the second case, the semiconductor switch in the series branch and the mechanical switch are active. The mechanical switch is too slow to respond to transient events. In this case, the mentioned inductive decoupling is required, which reduces the surge current in the semiconductors to a tolerable extent.

(25) In the TOV operation, an interruption of neutral conductors may take place. U.sub.TOV is in this case <270 V and the load is >12 A. The semiconductor switches in the series branch and the mechanical switch remain active, i.e. the load can be continued to operate normally.

(26) In case of U.sub.TOV>270 V and I.sub.Last<12 A, the series switch in the parallel path is deactivated when a fault occurs. Loads of up to 150 W, for example, may further be operated via the capacitive divider C.sub.Längs and C.sub.Quer, so that the desired emergency operating feature for increasing operational safety is reached.

(27) The mentioned current threshold of, for example, >12 V represents a regulating instrument by means of which the control of the parallel and series switches becomes possible. Alternatively, a regulation to only the voltage amplitude of substantially 270 V may also be performed without any load current flow.

(28) In case of a short circuit L-N in the adjacent phase, only the semiconductor switch is active at a load I.sub.Last<6 A and can therefor quickly respond to the fault event.

(29) At a load of >6 A, the semiconductor switch and the mechanical switch in the series branch are active. The reaction time is predetermined by the mechanical switches. The voltage increases for about 2 ms, for example, to 1.33 times of a reference voltage. This short-term voltage excess represents a transient stress for loads of a level of up to 1.33 times the reference voltage and may be considered as being unproblematic. The mechanical switch is switched off in a currentless manner since the semiconductor switch in the series branch takes the full current.

(30) In the case of a short circuit L-N in the phase of the circuit arrangement itself, the semiconductor switch and the mechanical switch are activated in common until the fault is remedied by an upstream fuse.

(31) In the case of a combination of semiconductor switches and the mechanical switch in the series branch, the maximum voltage value at the load is 1.33×U.sub.REF during temporary events. During transient events, the protection level at the load is set to about 650 V.