Current signal generation useful for sampling

Abstract

Sampler circuitry, having: an input node which receives an input voltage signal; a primary current path connected between high and low voltage supply nodes; a secondary current path connected between high and low voltage supply nodes; current mirror circuitry; and load circuitry having sampler switches which sample a current signal, where the input node is defined along the primary current path, the primary current path configured to carry a primary current dependent on the input voltage signal; the current mirror circuitry includes a primary side and a secondary side, the primary side connected along the primary current path and the secondary side connected along the secondary current path so that a secondary current dependent on the primary current is caused to flow along the secondary current path; and the load circuitry is connected along the secondary current path so that the secondary current at least partly forms the current signal.

Claims

1. Sampler circuitry, comprising: an input node configured to receive an input voltage signal; a primary current path connected between high and low voltage supply nodes; a secondary current path connected between high and low voltage supply nodes; current mirror circuitry; and load circuitry comprising sampler switches operable to sample a current signal, wherein: the input node is defined along the primary current path, the primary current path configured to carry a primary current dependent on the input voltage signal; the current mirror circuitry comprises a primary side and a secondary side, the primary side connected along the primary current path and the secondary side connected along the secondary current path so that a secondary current dependent on the primary current is caused to flow along the secondary current path; and the load circuitry is connected along the secondary current path so that the secondary current at least partly forms the current signal.

2. The sampler circuitry as claimed in claim 1, further comprising a current source connected along the primary current path and configured to define a bias current flowing along that path.

3. The sampler circuitry as claimed in claim 1, wherein: the input node is located along the primary current path so as to divide the primary current path into first and second portions, the first portion of the primary current path configured to carry the primary current; and the primary side of the current mirror circuitry is connected along the first portion of the primary current path.

4. The sampler circuitry as claimed in claim 3, further comprising an impedance connected in series along the first portion of the primary current path between the input node and the primary side of the current mirror circuitry.

5. The sampler circuitry as claimed in claim 4, wherein the impedance is a second impedance, and wherein the sampler circuitry further comprises a first impedance connected in series along the second portion of the primary current path.

6. The sampler circuitry as claimed in claim 5, wherein: the first impedance is implemented as a resistor or as a resistor connected in series with an inductor; and/or the second impedance is implemented as a resistor or as a resistor connected in parallel with a capacitor.

7. The sampler circuitry as claimed in claim 1, further comprising: a third impedance connected in series along the primary current path between the high voltage supply node concerned and the primary side of the current mirror circuitry; and/or a fourth impedance connected in series along the secondary current path between the high voltage supply node concerned and the secondary side of the current mirror circuitry.

8. The sampler circuitry as claimed in claim 7, wherein: the third impedance is implemented as a resistor or as a resistor connected in series with an inductor; and/or the fourth impedance is implemented as a resistor or as a resistor connected in parallel with a capacitor.

9. The sampler circuitry as claimed in claim 1, further comprising a fifth impedance connected between the primary and secondary sides of the current mirror circuitry, optionally between gate terminals of a diode-connected transistor of the primary side and a corresponding mirror transistor of the secondary side of the current mirror circuitry, optionally wherein the fifth impedance is implemented as an inductor.

10. The sampler circuitry as claimed in claim 1, further comprising control circuitry operable to configure the current mirror circuitry so as to control a gain provided by the current mirror circuitry in the secondary current relative to the primary current.

11. The sampler circuitry as claimed in claim 10, wherein the control circuitry is configured to control one or more voltage signals applied to the gates of one or more transistors of the current mirror circuitry, optionally to switch the or those transistors on or off, to control the gain provided by the current mirror circuitry.

12. The sampler circuitry as claimed in claim 11, wherein the primary and secondary sides of the current mirror circuitry each comprise at least one cascode transistor, and wherein the voltage signals controlled by the control circuitry are voltage signals provided to the gates of cascode transistors of the current mirror circuitry, optionally to the gates of one or more cascode transistors of the secondary side of the current mirror circuitry, optionally wherein the control circuitry is configured to control one or more gate voltages of one or more cascode transistors, respectively, of the primary side of the current mirror circuitry so that the one or more cascode transistors of the primary side of the current mirror circuitry operate at or around the border of their triode and saturation regions.

13. Differential sampler circuitry comprising a first section and a second section, the first and second sections each comprising sampler circuitry as claimed in claim 1.

14. Analogue-to-digital conversion circuitry comprising the sampler circuitry of claim 1.

15. Integrated circuitry, such as an IC chip, comprising the sampler circuitry of claim 1.

Description

(1) Reference will now be made, by way of example, to the accompanying drawings, of which:

(2) FIG. 1, as mentioned above, is a schematic diagram of analogue-to-digital circuitry useful for understanding a potential application of the present invention;

(3) FIG. 2, as mentioned above, is a schematic diagram of the current-steering sampler of FIG. 1;

(4) FIG. 3, as mentioned above, is a schematic diagram of the current-steering sampler of FIG. 1 to which it is possible to apply an input differential voltage signal;

(5) FIG. 4 is a schematic diagram of sampler circuitry, as a comparative example;

(6) FIG. 5 is a schematic diagram of a first example arrangement of sampler circuitry;

(7) FIGS. 6A and 6B are graphs useful for understanding the sampler circuitry of FIG. 5;

(8) FIGS. 7A and 7B are graphs useful for understanding the sampler circuitry of FIG. 5;

(9) FIG. 8 is a graph useful for understanding the sampler circuitry of FIG. 5;

(10) FIG. 9 is a schematic diagram of a second example arrangement of sampler circuitry;

(11) FIG. 10 is a schematic diagram of a modified second example arrangement of sampler circuitry;

(12) FIGS. 11A and 11B are graphs useful for understanding the sampler circuitry of FIGS. 9 and 10;

(13) FIG. 12A is a schematic diagram of ADC circuitry; and

(14) FIG. 12B is a schematic diagram of an integrated circuit.

(15) FIG. 4 is a schematic diagram of sampler circuitry 100, as a comparative example. Similarities with the implementation 43 of sampling circuitry 42 shown in FIG. 3 will be apparent. Sampler circuitry 100 is shown in FIG. 4 as differential circuitry operable based on a differential input voltage signal. It will be apparent that sampler circuitry 100 may also be provided as single-ended circuitry operable based on a single-ended input voltage signal.

(16) Sampler circuitry 100 comprises two matching (or corresponding or complementary) sections 101 and 102 for the two differential inputs (i.e. the two input voltage signals which form the differential input voltage signal). The first section 101 comprises an input node 14.sub.A, a first impedance 20.sub.A, a second impedance 30 and a load node 16.sub.A. The input node 14.sub.A is configured to receive an input voltage signal V.sub.INP via a terminal 15A. The input node 14A and the terminal 15A as shown in FIG. 4 are denoted separately but they could be the same. The input node 14.sub.A is connected to a tail node 12 via the first impedance 20.sub.A. The tail node 12 is connected via a current source 10 to a voltage reference (power supply node, or equally voltage source node) V.sub.H whose voltage level is above that of V.sub.INP (and V.sub.INM). In particular, current source 10 supplies a constant (regulated) DC current I.sub.DC to the sampler circuitry 100. The current I.sub.DC may be referred to as a bias current and/or as a sampler current. The input node 14.sub.A is connected to the load node 16.sub.A via the second impedance 30.sub.A. The second section 102 has a corresponding arrangement (with like elements denoted with a subscript B rather than a subscript A) as shown in FIG. 4, including an input node 14.sub.B to receive an input voltage signal V.sub.INM. A detailed description of the second section 102 is therefore omitted. Input voltage signals V.sub.INP and V.sub.INM are the “plus” and “minus” components of the (differential) input voltage signal.

(17) Sampler circuitry 100 comprises load circuitry 40. As shown in FIG. 4, load circuitry 40 comprises switches 40A.sub.0 to 40A.sub.N-1 connected to the load node 16.sub.A of the first section 101, and switches 40B.sub.0 to 40B.sub.N-1 connected to the load node 16.sub.B of the second section 102. The switches 40A.sub.0 to 40A.sub.N-1 and 40B.sub.0 to 40B.sub.N-1 may be referred to as sampling switches or sampler switches. In line with FIGS. 1 to 3, these sampling switches may be the sampling switches of a current-mode sampler (in such a case the sampling switches 40A.sub.0 to 40A.sub.N-1 and 40B.sub.0 to 40B.sub.N-1 may be controlled by time-interleaved clock signals). In general, however, it will be appreciated that the load circuitry 40 may comprise any current-mode circuitry. The load circuitry 40 (or subsequent circuitry connected beyond the load circuitry 40) will of course be connected to a voltage reference (power supply node) V.sub.L whose voltage level is below that of the voltage reference V.sub.H. The voltage reference V.sub.H may be referred to as a high reference voltage and the voltage reference V.sub.L may be referred as a low voltage reference, and the potential difference between V.sub.H and V.sub.L may be referred to as the supply voltage (provided by a power supply).

(18) In overview, sampler circuitry 100 operates by receiving the input voltage signal and by employing impedances to passively convert the received input voltage signal into an equivalent input current signal. For example, a differential input current signal is received by the load circuitry between (or at) the load nodes 16.sub.A and 16.sub.B. In this regard, sampler circuitry 100 comprises voltage-to-current conversion circuitry, its output being the current signal received by the load circuitry 40 between the load nodes 16.sub.A and 16.sub.B. Further, the sampler circuitry 100 may be referred to simply as circuitry or a circuitry system.

(19) The first impedance 20.sub.A as shown in FIG. 4 comprises a resistor 21.sub.A and an inductor 22.sub.A connected together in series. The second impedance 30.sub.A as shown in FIG. 4 comprises a resistor 31.sub.A and a capacitor 33.sub.A connected together in parallel and an inductor 32.sub.A connected with the resistor 31.sub.A in series. In other arrangements the first impedance 20.sub.A and the second impedance 30.sub.A may comprise any component(s) that give rise to an impedance. The same considerations apply to the first and second impedances 20.sub.B and 30.sub.B of the second section 102.

(20) As described above, sampler circuitry 100 can also be provided as single-ended circuitry operable based on a single-ended input voltage signal and operable to output a single-ended current signal. That is, single-ended sampler circuitry may comprise the first section 101, the current source 10, the tail node 12 and load circuitry (e.g. the relevant part of the load circuitry 40). The following description of the operation of the sampler circuitry 100 will be understood to apply equally to a single-ended implementation.

(21) A brief summary of operation of sampler circuitry 100 is as follows, focusing on the first section 101 by way of example (with the understanding that sampler circuitry 100 may be single-ended and that in the case of differential sampler circuitry 100 a corresponding explanation applies for the second section 102). Ignoring for the moment the capacitor 33.sub.A (as if it were not present) and the inductors 22.sub.A and 32.sub.A (as if they were shorted), i.e. considering operation at DC, the amount of current flowing through resistor 31.sub.A is effectively a portion of the current I.sub.DC dependent in part on the value of the input voltage signal V.sub.INP (and of course the resistance impedance values). This current flows through the load circuitry 40 (the switches 40A.sub.0 to 40A.sub.N-1 in FIG. 4) and may be referred to as a load current (or a first load current for a differential implementation of sampler circuitry 100). A current I.sub.INP is drawn in at the input node 14.sub.A and is split between resistors 21.sub.A and 31.sub.A. The proportion of the current I.sub.INP which flows through each of the resistors 21.sub.A and 31.sub.A can be adjusted by appropriate selection of the resistance values of the resistors 21.sub.A and 31.sub.A. It is possible to select these resistors for each application so that the desired proportion of the current I.sub.INP flows through each of the resistors 21.sub.A and 31.sub.A. However, it is difficult to make the resistance values of the resistors 21.sub.A and 31.sub.A switchable without affecting bandwidth and input parasitic capacitance of the sampler circuitry 100. For the purpose of the following description it is assumed that sampler circuitry 100 corresponds generally to the sampler 42 of FIG. 1 and connects to the input of sub-ADC units (corresponding to the sub-ADC units 48 of FIG. 1), perhaps via demultiplexing stages (corresponding to demultiplexing stages 46 of FIG. 1), but as mentioned above the load circuitry 40 could be any current-mode circuitry.

(22) At high frequency (of the input voltage signal V.sub.INP there are two peaking mechanisms which boost the amount of current passing though the sampler switches 40A.sub.0 to 40A.sub.N-1. The first peaking mechanism is the capacitor 33.sub.A, which may be referred to as a shunting capacitor. At high frequencies (in relative terms), the effective AC resistance of the resistor 31.sub.A connected in parallel to the capacitor 33.sub.A drops, which in turn increases the amount of current injected to the sampler switches 40A.sub.0 to 40A.sub.N-1. The second peaking mechanism is the inductor 22.sub.A. At high frequencies (in relative terms), the inductor 22.sub.A increases the impedance seen looking into the first impedance 20.sub.A from the input (or branch) node 14.sub.A and so causes the proportion of the current I.sub.INP which flows through the first impedance 20.sub.A to decrease. On the other hand, the impedance seen looking into the input node 14.sub.A from the input terminal 15.sub.A increases, which in turn causes the current I.sub.INP to decrease. The amount of current drop in the proportion of the current I.sub.INP flowing through the first impedance 20.sub.A is more than the overall current drop in the current I.sub.INP. So, the overall effect of the inductor 22.sub.A is that the proportion of the current I.sub.INP flowing through the second impedance 30.sub.A (and so the current flowing through the sampler switches 40A.sub.0 to 40A.sub.N-1) increases in magnitude. Corresponding considerations apply to the second section 102 and the current flowing through the sampler switches 40B.sub.0 to 40B.sub.N-1.

(23) Due to the shunting mechanism described above with regard to the shunting capacitor 33.sub.A, the impedance seen looking into the input node 14.sub.A from the input terminal 15.sub.A changes significantly, which leads to unwanted effects. To restore some of this impedance and bring it closer to its ideal value (for example 50 ohms), the inductor 32.sub.A is added to the second impedance 30.sub.A The inductor 32.sub.A helps to bring the scattering parameter S11 (a common measure of the performance of a circuit) close to its required or desired value.

(24) It has been found that there are some disadvantages with the structure of the sampler circuitry 100 shown in FIG. 4, which are described below with reference to the first section 101 of the sampler circuitry 100 (with the same considerations applying to the second section 102).

(25) A first disadvantage is that there is a strong trade-off between the amount of gain (peaking) and the value of the S11 parameter. Gain is used here to refer to the amount of gain “peaking”, i.e. the current flowing into the load node 16.sub.A, at high frequency (of the input voltage signal V.sub.INP/M) compared to at low frequency (of the input voltage signal V.sub.INP/M), in particular the ratio of the amount of current passing through the load node 16.sub.A (and thus the sampler switches) at high input frequencies divided by the amount of current passing through the load node 16.sub.A at low input frequencies. Of course, in general the gain of the sampler circuitry 100 can be considered to be the current flowing into the load node 16.sub.A divided by the input voltage V.sub.INP, or in the differential case to be the difference between the currents flowing into the load nodes 16.sub.A and 16.sub.B divided by the difference between V.sub.INP and V.sub.INM. Gain in this latter sense could be expressed as I=G(f).Math.Vin, where Vin is the input voltage, I is the output current and Gain G(f) is a function of frequency f of the input voltage signal. Increasing the value of the inductance of the inductor 22.sub.A and/or the value of capacitance of the shunting capacitor 33.sub.A, although increasing gain peaking, takes the impedance seen looking into the input node 14.sub.A from the input terminal 15.sub.A further away from its ideal value which in turns degrades the value of the S11 parameter.

(26) A second disadvantage is a relatively low voltage headroom. That is, there is a large number of devices/components stacked on top of one another, from the current source 10 down to the load circuitry 40 (and other subsequent circuitry). The supplied voltage is “used up” by the large number of devices stacked on top of one another. This puts pressure in terms of voltage headroom on the devices (in particular, of the load circuitry 40) and makes it difficult (and up to a point, impossible) to reduce the voltage supply (which would be advantageous from a power-saving point of view).

(27) A third disadvantage is the difficulty associated with current scaling. That is, the amount of current that can be injected towards the current mode input circuit (i.e. to the load node 16.sub.A) is a portion of the current I.sub.DC. For higher resolution applications (taking the ADC application as an example) it is useful to scale the current supplied to the load node 16.sub.A (for example, in an ADC the thermal noise of the sampling capacitor is a limit and therefore a higher capacitance value for the sampling capacitor may be required which requires a much higher value of the current I.sub.DC. In order to increase the value of I.sub.DC, the voltage drop of the resistors 21.sub.A and 31.sub.A must be reduced. This will result in a lower characteristic impedance seen looking into the input node 14.sub.A from the input terminal 15.sub.A (e.g. less than a desired 50 Ohm). This makes the shunting capacitor 33.sub.A much less effective. That is, to achieve a reasonable effect using the shunting capacitor 33.sub.A in view of the lower characteristic impedance, the shunting capacitor 33.sub.A would need to be very large, which is not feasible in practice since such a large capacitor 33.sub.A would give rise to much more parasitic capacitance and thereby degrade the bandwidth of the sampler circuitry 100, which is not desirable. Moreover, the stacking of the devices in the sampler circuit 100 would be much more difficult with higher currents.

(28) To overcome some of these disadvantages (among others), two example arrangements are disclosed herein.

(29) FIG. 5 is a schematic diagram of a first example arrangement 200 of sampler circuitry.

(30) Sampler circuitry 200 is shown in FIG. 5 as differential circuitry operable based on a differential input voltage signal. Sampler circuitry 200 can also be provided as single-ended circuitry operable based on a single-ended input voltage signal.

(31) It will become apparent that the sampler circuitry 200 is similar to the circuitry 100, but uses a current mirror approach to address the above-mentioned problems. The current mirror enables the circuit to have a “folded” structure. As explained in more detail below, the current mirror also provides additional gain. Further, the various impedances impact the operation to provide gain boosting at high frequencies as compared to at low frequencies.

(32) Sampler circuitry 200 comprises two matching (or corresponding or complementary) sections 201 and 202 for the two differential inputs, similar to the circuitry 100.

(33) The first section 201 comprises an input node 214.sub.A, a mirror node 218.sub.A, a first impedance 220.sub.A, a second impedance 230.sub.A, a third impedance 270.sub.A, a fourth impedance 280.sub.A, current mirror circuitry 265.sub.A, a primary reference node 290.sub.A, a secondary reference node 292.sub.A, a load node 216.sub.A and load circuitry 240.sub.A.

(34) The input node 214.sub.A is configured to receive an input voltage signal V.sub.INP via a terminal 215.sub.A. The input node 214.sub.A and the terminal 215.sub.A as shown in FIG. 5 are provided separately but they could be the same. The input node 214.sub.A is connected to a tail node 212 via the first impedance 220A. The tail node 212 is connected via a current source 210 to a voltage reference (power supply node) V.sub.L whose voltage level is below that of V.sub.INP (and V.sub.INM). In particular, current source 210 supplies a constant DC current I.sub.DC to the sampler circuitry 200. The current I.sub.DC may be referred to as a bias current or as a sampler current in some examples. The input node 214.sub.A is connected to the mirror node 218.sub.A via the second impedance 230.sub.A. The mirror circuitry 265.sub.A comprises a primary side 250.sub.A connected between the mirror node 218.sub.A and the third impedance 270.sub.A, and a secondary side 260.sub.A connected between the load node 216.sub.A and the fourth impedance 280.sub.A. The primary side 250.sub.A is connected to the primary reference node 290.sub.A via the third impedance 270.sub.A. The secondary side 260.sub.A is connected to the secondary reference node 292.sub.A via the fourth impedance 280.sub.A. The load circuitry 240.sub.A is connected to the load node 216.sub.A.

(35) The primary and secondary reference nodes 290.sub.A and 292.sub.A are connected to voltage references (power supply nodes). Here it is assumed that the references nodes (power supply nodes) 290.sub.A and 292.sub.A are connected to the same voltage reference (power supply node) V.sub.H which may be referred to as a high voltage reference. The load circuitry 240.sub.A (or subsequent circuitry connected beyond the load circuitry 240) will of course be connected to a voltage reference (power supply node) V.sub.L2 whose voltage level is below that of the voltage reference (power supply node) V.sub.H and which may be referred to as a low voltage reference. Here it is assumed that the voltage references (power supply nodes) V.sub.L1 and V.sub.L2 are connected to the same voltage reference (power supply node) V.sub.L which may be referred to as the low voltage reference (e.g. GND), although different voltage levels for V.sub.L1 and V.sub.L2 could be provided.

(36) The first section 201 can be described as comprising a primary current path 201.sub.1 connected between high and low voltage references V.sub.H and V.sub.L1 and a secondary current path 201.sub.2 connected between high and low voltage references V.sub.H and V.sub.L2. The input node 214.sub.A, the mirror node 218.sub.A, the first impedance 220.sub.A, the second impedance 230.sub.A, the third impedance 270.sub.A, and the primary side 250.sub.A of the current mirror circuitry 265.sub.A are connected along the primary current path 201.sub.1. The fourth impedance 280.sub.A, the secondary side 260.sub.A of the current mirror circuitry 265.sub.A, the load node 216.sub.A and the load circuitry 240.sub.A are connected along the secondary current path 201.sub.2. The primary current path 201.sub.1 is configured to carry a primary current dependent on the input voltage signal V.sub.INP. The current mirror circuitry 265.sub.A is connected to receive the primary current at its primary side 250.sub.A and to output a secondary current at its secondary side 260.sub.A (that is, a secondary current dependent upon the primary current is caused to flow along the secondary current path 201.sub.2). The tail node 212 and the current source 210 may be considered connected along the primary current path 201.sub.1 and the current source 210 configured to define a bias current flowing along that path. The input node 214.sub.A may be considered located along the primary current path 201.sub.1 so as to divide the primary current path into first and second portions, the first portion of the primary current path 201.sub.1 configured to carry the primary current, the primary side 250.sub.A of the current mirror circuitry 265.sub.A connected along the first portion of the primary current path 201.sub.1, and the first impedance 220.sub.A connected along the second portion of the primary current path 201.sub.1.

(37) The second section 202 has a corresponding arrangement (with like elements denoted with a subscript B rather than a subscript A) as shown in FIG. 5, including an input node 214.sub.B to receive an input voltage signal V.sub.INM. A detailed description of the second section 202 is therefore omitted. Input voltage signals V.sub.INP and V.sub.INM are the “plus” and “minus” components of the (differential) input voltage signal.

(38) Sampler circuitry 200 comprises load circuitry 240. As shown in FIG. 5, load circuitry 240 corresponds closely to the load circuitry 40 in FIG. 4, and equivalent considerations apply. That is, the switches 240A.sub.0 to 240A.sub.N-1 and 240B.sub.0 to 240B.sub.N-1 may be referred to as sampling switches or sampler switches; these sampling switches may be the sampling switches of a current-mode sampler corresponding to sampler 42 (in such a case the sampling switches 240A.sub.0 to 240A.sub.N-1 and 240B.sub.0 to 240B.sub.N-1 may be controlled by time-interleaved clock signals). The load circuitry 240 comprises the load circuitry 240.sub.A of the first section 201 and the load circuitry 240B of the second section 202 as shown in FIG. 5. The load circuitry 240 as depicted in FIG. 5 is however an example and in general may comprise any current-mode circuitry.

(39) Sampler circuitry 200 basically works in a similar way to the sampler circuitry 100: by receiving the input voltage signal and by employing impedances to passively convert the received input voltage signal into an equivalent input current signal. For example, a current signal is received by the load circuitry 240.sub.A at the load node 216.sub.A. The secondary current at least partly forms the current signal. In a differential implementation, for example, a differential current signal is received by the load circuitry at the load nodes 216.sub.A and 216.sub.8 (and the secondary currents output by the secondary sides 260.sub.A and 260.sub.B of the current mirror circuitry 265.sub.A and 265.sub.B, respectively, at least partly form the differential current signal). In this regard, sampler circuitry 200 may be considered to comprise voltage-to-current conversion circuitry, with its output being the current signal received by the load circuitry 240 between or at the load nodes 216.sub.A and 216.sub.E. Further, the sampler circuitry 200 may be referred to simply as circuitry or a circuitry system. In the following description it is assumed for convenience that the current signal received by the load circuitry 240.sub.A is the same as the secondary current (and this may be referred to as a load current), with an equivalent assumption holding for the second section 202.

(40) The first to fourth impedances 220.sub.A, 230.sub.A, 270.sub.A and 280.sub.A are shown in FIG. 5 as comprising particular combinations of resistor, capacitor and/or inductor. However, as discussed above with regard to the first and second impedances 20.sub.A and 30.sub.A of sampler circuitry 100, any component(s) giving rise to an impedance may be used to implement the first to fourth impedances 220.sub.A, 230.sub.A, 270.sub.A and 280.sub.A. Further, the third and fourth impedances 270.sub.A and 280.sub.A are not essential. Equivalent considerations apply to the first to fourth impedances 220.sub.B, 230.sub.B, 270.sub.B and 280.sub.B of the second section 202.

(41) The primary and secondary reference nodes 290.sub.A and 292.sub.A of the first section 201 and the primary and secondary reference nodes 290.sub.B and 292.sub.B of the second section 202 as shown in FIG. 5 are all connected to the same voltage reference (power supply node) V.sub.H (AVD). However, the reference nodes 290.sub.A, 292.sub.A, 290.sub.B and 292.sub.B may each be connected to voltage references (power supply nodes) different to or the same as any other reference node 290.sub.A, 292.sub.A, 290.sub.B and 292.sub.B.

(42) As described above, sampler circuitry 200 can also be provided as single-ended circuitry operable based on a single-ended input voltage signal and operable to output a single-ended current signal (load current). That is, single-ended sampler circuitry may comprise the first section 201, the current source 210, the tail node 212 and load circuitry (e.g. the load circuitry 240.sub.A), i.e. without the second section 202. The following description of the operation of the sampler circuitry 200 will be understood to apply equally to a single-ended implementation.

(43) A brief summary of the operation of sampler circuitry 200 is as follows, focusing on the first section 201 by way of example (a corresponding explanation applies for the second section 202). Further, the following description is mainly focused on the differences between this first example arrangement 200 and sampler circuitry 100 shown in FIG. 4. The current generated with the second impedance 230.sub.A (the primary current) is injected to the (advantageously wide swing) current mirror circuitry 265.sub.A at its primary side 250.sub.A and is multiplied and copied and at its secondary side 260.sub.A. In other words, the secondary current is caused to flow along the secondary current path 201.sub.2. The gain of the secondary current compared to the primary current is defined as G. The maximum value of G is n/m, where n and m are the number of unit devices (transistors, such as field-effect transistors) on the secondary and primary sides 260.sub.A and 250.sub.A of the current mirror circuitry 265.sub.A, respectively. On the primary side 250.sub.A, transistor 252.sub.A is the diode connected device and transistor 251.sub.A is the cascode for the primary side 250.sub.A. On the secondary side 260.sub.A, the transistor 262.sub.A is the mirror device and transistor 261.sub.A is the cascode for the secondary side 260.sub.A.

(44) Ignoring the third and fourth impedances 270.sub.A and 280.sub.A and the inductor 255.sub.A, the devices 251.sub.A, 252.sub.A, 261.sub.A and 262.sub.A form a wide swing current mirror which mirrors the input-dependent current (the primary current) with the gain of G to form the secondary current. In the sampler circuitry 200, both the DC and the AC amplitude of the primary current is multiplied with the same factor. This is appropriate for the example in which the load circuitry 240 comprises sampler switches constituting an ADC front-end where the output load is defined by the sub-ADC sampling capacitance. This ability to amplify the primary current solves the problem associated with the third disadvantage described above. That is, the amount of current at the load node 216.sub.A can be increased without the need to increase the current generated at the current source 210 (i.e. the bias current I.sub.Dc), and therefore the values of the first and second impedances 220.sub.A, 230.sub.A do not need to be changed to account for a change in the current I.sub.DC. Thereby a larger secondary current is achieved with an advantageous S11 value and bandwidth.

(45) The sampler circuitry 200 also solves the problem associated with the second disadvantage mentioned above. In particular, the splitting of the stacking into the primary and secondary current paths 201.sub.1 and 201.sub.2 (i.e. “folding”) solves this problem. As mentioned above, the primary current path 201.sub.1 comprises the input node 214.sub.A, the mirror node 218.sub.A, the first impedance 220.sub.A, the second impedance 230.sub.A, the third impedance 270.sub.A, and the primary side 250.sub.A of the current mirror circuitry 265.sub.A, each connected therealong. For example with a 1.8 V supply voltage (i.e. AVD=1.8 V), this part of the sampler circuitry 200 (the primary current path 201.sub.1) can be designed without any voltage headroom problem. This design relaxation is such that the bias current I.sub.DC can be generated (by current source 210) using a simple current mirror without the need for a DC control loop, for example. As mentioned above, the secondary current path 201.sub.2 comprises the fourth impedance 280.sub.A, the secondary side 260.sub.A of the current mirror circuitry 265.sub.A, the load node 216.sub.A and the load circuitry 240.sub.A, each connected therealong. The secondary current path 201.sub.2 may also effectively comprise any subsequent circuitry connected beyond the load circuitry 240.sub.A, for example (sub-) ADC circuitry. Importantly, the secondary current path 201.sub.2 need not (and does not) comprise elements of the primary current path 201.sub.1 such as the first impedance 220.sub.A, the second impedance 230.sub.A, and the current source 210.

(46) A mirror voltage signal V.sub.P input at the gate of transistor 251.sub.A may be generated with a DC control loop circuit (not shown) and controls the transistor 251.sub.A so that it is on the border of triode and saturation. This guarantees a high resolution operation of the current mirror circuitry 265.sub.A and therefore of the sampler circuitry 200. The transistor 261.sub.A is controlled by the register 295 as shown in FIG. 5. The register 295 generates either a supply voltage (e.g. having the same value, AVD, as V.sub.H) or a defined bias voltage (which may also be generated by a control loop circuit, not shown in FIG. 5) for input at the gate of transistor 261.sub.A. When the register 295 (depending on a value it stores) generates the supply voltage at the gate of transistor 261.sub.A, the transistor 261.sub.A is OFF, and when the register 295 generates a bias voltage at the gate of transistor 261.sub.A, the transistor 261.sub.A is ON (to a defined level). The amount of gain G of the current mirror circuitry 265.sub.A varies accordingly (assuming transistor 261.sub.A is implemented as a plurality of devices which can be controlled separately as mentioned below). Although not shown in FIG. 5, it will be understood that the voltages supplied from the register 295 to the transistors 261A and 261B could be different from one another, i.e. optimised for the relevant circuit section 201, 202. The register 295 may be referred to as or form part of control circuitry. Control circuitry may comprise the register 295 as well as any DC control loops described above.

(47) It will be appreciated that any of transistors 251.sub.A, 252.sub.A, 261.sub.A and 262.sub.A may correspond to a plurality of transistors/devices. In particular, transistor 261.sub.A may correspond to a plurality of transistors/devices, in which case the register 295 controls individual transistors/devices as described above (i.e. generating a supply voltage or a bias voltage at the gates of individual transistors/devices to switch some or all of them OFF and some or all of them ON) in order to vary the gain G of the current mirror circuitry 265.sub.A. This control of the gain G of the current mirror circuitry 265.sub.A brings programmability to the sampler circuitry 200. With such programmability of the sampler circuitry 200, programmability can be removed from (or simplified in) the current-mode circuitry being driven (i.e. the load circuitry), including any subsequent circuitry, for example, a (sub-) ADC. This enables the design of the current-mode circuitry being driven to be more compact and efficient, especially for higher resolution applications. Moreover, the amount of current at the load node 216.sub.A (i.e. the magnitude of the secondary/load current) can be adjusted to compensate for loss due to parasitic capacitance and any other effects which might degrade the signal level supplied to, for example, a (sub-) ADO front-end (i.e. load circuitry 240.sub.A and subsequent circuitry). That is, calibration can be performed to tune out parasitic capacitances and other effects that reduce the magnitude of or otherwise degrade the secondary/load current.

(48) The function of the first and second impedances 220.sub.A and 230.sub.A (in particular the inductor 222.sub.A and the capacitor 233.sub.A) is substantially the same as that of the first and second impedances 20.sub.A and 30.sub.A described above with reference to FIG. 4. A detailed description of the operation of the first and second impedances 220.sub.A and 230.sub.A is therefore omitted. In addition to the gain that can be added (in the sense of boosting the gain at high frequencies relative to at low frequencies) by the configuration of the first and second impedances 220.sub.A and 230.sub.A as shown in FIG. 5, more gain can be added (in the sense of high-frequency boosting) by using the configuration of the third and fourth impedances 270.sub.A and 280.sub.A shown in FIG. 5, and also by using the inductor 255.sub.A in the current mirror circuitry 265.sub.A, as follows.

(49) The inductor 255.sub.A between the gates of transistors 252.sub.A and 262.sub.A (and preferably using as the inductor 255.sub.A a fairly high-Q inductor with a small inductance) provides a mid-frequency resonance with the gate-source capacitance of the transistor 262.sub.A. In other words, the inductor 255.sub.A “tunes out” the gate-source capacitance of the transistor 262.sub.A. This results in peaking in the secondary current, and also compensates for the low frequency operation of the current mirror circuitry 265.sub.A. Thus the inductor 255.sub.A extends the bandwidth of the current mirror circuitry 265.sub.A.

(50) The inductor 272.sub.A connected between the source of the transistor 252.sub.A and the primary reference node 290.sub.A (and preferably using as the inductor 272.sub.A a medium-sized inductor (relatively speaking)) provides high frequency source degeneration which boosts the gate voltage of the transistor 262.sub.A (and also the gate voltage of transistor 252.sub.A since the gates of transistors 262.sub.A and 252.sub.A are connected together via the inductor 255.sub.A). This also provides some gain boosting at high frequency (i.e. boosting of the gain at high frequencies relative to at low frequencies) in the secondary current depending on the size of the inductor 272.sub.A.

(51) The resistors 271.sub.A and 281.sub.A connected between the source of the transistor 252.sub.A and the primary reference node 290.sub.A, and between the source of the transistor 262.sub.A and the secondary reference node 292.sub.A, respectively (preferably small (high current) resistors), act as degeneration resistors. The resistor 281.sub.A on the secondary side 201.sub.2 is shunted with the capacitor 283.sub.A connected in parallel with the resistor 281.sub.A (preferably the capacitor 283.sub.A is a small capacitor, relatively speaking). At high frequency (of the input voltage signal V.sub.INP), the shunting capacitor 283.sub.A removes the degeneration in the source of the transistor 262.sub.A which in turn increases the gain of the current mirror circuitry 265.sub.A. Preferably, the resistance values of the resistors 271.sub.A and 281.sub.A are scaled so that the resistance value of the resistor 281.sub.A is smaller than the resistance value of the resistor 271.sub.A by a factor of G (the gain of the current mirror circuitry 265.sub.A), for example to provide improved matching and to stabilise the gain. Using the resistors 271.sub.A and 281.sub.A to boost the gain (at high frequencies relative to at low frequencies) does consume some voltage headroom which could be noticeable, especially in the secondary current path 201.sub.2. Further, when the sampler circuitry 200 is operated with a high current, low resistance value and high current resistors are required for the resistors 271.sub.A and 281.sub.A—which can be difficult to implement in some practical arrangements.

(52) For some implementations the resistors 271.sub.A and 281.sub.A are not employed. In other words, the inductors 255.sub.A and 272.sub.A may add sufficient gain to the current mirror circuitry 265.sub.A. As mentioned above, the first to fourth impedances 220.sub.A, 230.sub.A, 270.sub.A and 280.sub.A may have configurations other than those depicted in FIG. 5, and the sampler circuitry 200 may not comprise the third and fourth impedances 270.sub.A and 280.sub.A.

(53) In terms of the S11 parameter, the inductor 272.sub.A increases the impedance seen at high frequencies from the drain of the transistor 251.sub.A. This increase compensates for the impedance decrease seen at high frequencies due to the shunting capacitor 233.sub.A (the description of which is analogous to that of the shunting capacitor 33.sub.A above), and therefore the inductor 272.sub.A provides improved matching and thereby improves the S11 parameter. At the same time, due to source degeneration as described above, the inductor 272.sub.A increases the gain boosting at high frequencies (i.e. boosting of the gain at high frequencies relative to at low frequencies). Therefore, the inductor 272.sub.A can improve both the gain profile and S11 parameter. This relaxes the above mentioned S11-gain trade-off (the first disadvantage described above of the sampler circuitry 100). Moreover, in the sampler circuitry 200 the load circuitry 240, is connected to the secondary side 260.sub.A of the current mirror 265.sub.A (along the secondary current path 201.sub.2) which makes the S11 parameter independent of effects from the load circuitry 240.sub.A (e.g. the g.sub.m (transconductance) of the sampling switches 240.sub.A0 to 240.sub.AN-1). This relaxes the conditions for ensuring a good S11 parameter.

(54) As described above, an advantage of the sampler circuitry 200 (compared to the sampler circuitry 100) is the extra amount of gain. This additional gain improves the bandwidth of the sampler circuitry 200, and the bandwidth can be brought towards the Nyquist rate at high ADC sample rates.

(55) FIG. 6A is a graph showing the peaking in the secondary/load current for an implementation of the sampler circuitry 100 (not folded) and for an implementation of the first example arrangement of sampler circuitry 200 (folded) for a 128 GSa/s ADC design example (i.e. with the load circuitry 240 configured as a sampler with a 128 GSa/s sample rate). As can be seen, more than 4 dB of gain is added into the signal path in the sampler circuitry 200 compared to the sampler circuitry 100 in these implementations.

(56) FIG. 6B is a graph showing the bandwidth of an implementation of the sampler circuitry 100 (not folded) and for an implementation of the first example arrangement of sampler circuitry 200 (folded) for the 128 GSa/s design example. It is apparent from FIG. 6B (considering e.g. the −3 dB level) that the bandwidth of the sampler circuitry 200 is improved compared to that of the sampler circuitry 100 (it can be seen that the bandwidth is improved by at least 4 GHz for these example implementations).

(57) The gain provided in the first example arrangement 200 allows the input voltage level to be reduced (whilst achieving the same output level) compared to the sampler circuitry 100. This reduces the amount of harmonics injected ultimately into the current signal that is to be provided to the load circuitry 240 (i.e. the secondary/load current) which in turn improves the effective resolution of the sampler circuitry 200 (in particular of the sampler implemented by way of the load circuitry 240). This is appropriate for low speed (low bandwidth) applications where a higher effective number of bits (ENOB) is normally required.

(58) FIG. 7A is a graph showing the ENOB of an implementation of the sampler circuitry 100 (not folded) and of an implementation of the first example arrangement of sampler circuitry 200 (folded) in a 56 GSa/s ADC design example in which the output is kept at −3 dBFS (3 dB lower than full scale). As can be seen in FIG. 7A, the first example arrangement 200 provides an improved ENOB compared to the sampler circuitry 100 across a wide range of input frequencies. In particular, at low (lower) input frequencies, the ENOB provided by the first example arrangement 200 is around 2.5 bits higher than the ENOB provided by the sampler circuitry 100 for these example implementations. In this implementation of the first example arrangement 200, the gain of the current mirror circuitry 265.sub.A is set to G=2.5 dB.

(59) FIG. 7B is a graph showing the ENOB of an implementation of the sampler circuitry 100 (not folded) and of an implementation of the first example arrangement of sampler circuitry 200 (folded) in a 56 GSa/s ADC design example in which the output is kept at −1 dBFS (1 dB lower than full scale). In this implementation of the first example arrangement 200, the gain of the current mirror circuitry 265.sub.A is set to G=6 dB. As can be seen in FIG. 7B, the ENOB improvement provided by the example arrangement 200 compared to the sampler circuitry 100 is better than that provided by the example arrangement 200 as implemented for FIG. 7A, due to the higher gain G of the current mirror circuitry 265.sub.A. In this implementation of the first example arrangement 200, at low (lower) frequencies, the ENOB provided is enhanced by around 4 bits compared to the ENOB provided by the sampler circuitry 100.

(60) FIG. 8 is a graph showing the current output signal level of an implementation of the first example arrangement of sampler circuitry 200 in a 56 GSa/s ADC design example in which (as an extreme example to illustrate the ENOB enhancement) the gain of the current mirror circuitry 265.sub.A is increased to G=9.5 dB. This allows the input signal level V.sub.INP/M to be reduced by more than 9 dB. As can be seen in FIG. 8, this practically pushes the harmonics (i.e., mainly the third harmonic) lower than the clock spurs (shown at fs/4+fin, fs/4-fin and fs/2-fin, where fs is the sampling frequency and fin is the frequency of the input signal, and the Nyquist frequency fs/2=28 GHz). This corresponds to a sampler design with no or negligible harmonic distortion.

(61) In summary, some of the advantages of the first example arrangement 200 (which may be referred to as an ultra high frequency, programmable equalizer, folded structure with high linearity) compared to, for example, the sampler circuitry 100 are as follows. Gain enhancement. The current mirror circuitry 265.sub.A can provide gain. Also, other components (e.g. impedances) can provide gain boosting at high frequencies without affecting the S11 parameter due to solving the problem of trade-off between gain and S11 by using the primary and secondary current paths 201.sub.1 and 201.sub.2. Improved linearity. Due to the improved gain the input voltage level V.sub.INP/M can be reduced whilst still achieving a sufficient output current signal level, so that there is less distortion in the output signal level. Therefore the linearity in the secondary/load current and therefore in the current signal input to load circuitry 240.sub.A is improved. Programmability. The current mirror circuitry 265.sub.A can be controlled as described above in order to adjust the gain G. This adjustment can be used to compensate for loss due to parasitic capacitance and any other effects which might degrade the output signal level. Sample frequency tuning. Due to the programmability of the current mirror circuitry 265.sub.A, the gain G of the current mirror circuitry 265.sub.A can be adjusted according to the sample frequency. Considering an example in which the load circuitry corresponds to sampling switches of a sub-ADC, without this programmability the capacitance value of the sub-ADC sampling capacitor would need to be adjusted according to the sample frequency (higher sample frequencies mean lower integration time and so a lower capacitance value of the sub-ADC sampling capacitor would be required, e.g. to achieve the same input voltage swing). However due to the programmability of the gain G of the current mirror circuitry 265.sub.A, the capacitance value of the sub-ADC sampling capacitor (considering an example in which the load circuitry corresponds to sampling switches of a sub-ADC) can be fixed and instead the gain of the current mirror circuitry 265.sub.A can be adjusted according to the sample frequency. Bandwidth extension. The bandwidth can be extended due to the improved gain profile (i.e. the added gain, and the boosting of gain at high frequencies relative to at low frequencies) and due to the improved S11 parameter. Decoupling of S11 performance from the load circuitry 240. Due to the “folding” of the first example arrangement (i.e. the current mirror circuitry 265.sub.A, giving rise to the first and second current paths 201.sub.1 and 201.sub.2), the S11 parameter is not affected by the load circuitry 240.sub.A and subsequent circuitry which is connected along the secondary current path (201.sub.2). This relaxes the conditions for ensuring a good S11 parameter,

(62) FIG. 9 is a schematic diagram of a second example arrangement 300 of sampler circuitry.

(63) Sampler circuitry 300 is differential circuitry operable based on a differential input voltage signal. Sampler circuitry 300 comprises control circuitry 395 and two matching (or corresponding or complementary) sections 301 and 302 for the two differential inputs, similar to the circuitry 100.

(64) The first section 301 comprises an input node 314.sub.A, an intermediate node 316.sub.A, a tail node 312.sub.A, an input-connection impedance 330.sub.A, a supply-connection impedance 320.sub.A, a measurement impedance 350.sub.A and load circuitry 340.sub.A. The intermediate node 316.sub.A as shown in FIG. 9 may be referred to as a load node.

(65) The input node 314.sub.A is configured to receive an input voltage signal V.sub.INP via a terminal 315.sub.A. The input node 314.sub.A and the terminal 315.sub.A as shown in FIG. 9 are provided separately but they could be the same as one another. The intermediate node 316.sub.A is connected to the tail node 312.sub.A via the supply-connection impedance 320.sub.A. The input node 314.sub.A is connected to the intermediate node 316.sub.A via the input-connection impedance 330.sub.A. The intermediate node 316.sub.A is connected to a measurement node 318 via the measurement impedance 350.sub.A.

(66) The input-connection, supply-connection, and measurement impedances 330.sub.A, 320.sub.A and 350.sub.A are shown in FIG. 9 as comprising particular combinations of resistor, capacitor and/or inductor. Similarly as discussed above with regard to the sampler circuitry 100 and 200, any component(s) giving rise to an impedance may be used to implement the impedances 320.sub.A, 330.sub.A and 350.sub.A. In particular, the input-connection impedance 330.sub.A may comprise a capacitor (not shown) connected in parallel with the resistor.

(67) The second section 302 has a corresponding arrangement as shown in FIG. 9, the measurement node 318 being shared between the first and second sections 301 and 302. A detailed description of the second section 302 is therefore omitted. Input voltage signals V.sub.INP and V.sub.INM are the “plus” and “minus” components of the (differential) input voltage signal.

(68) The nodes 314.sub.A, 316.sub.A and 312.sub.A, the impedances 320.sub.A, 330.sub.A and 350.sub.A, and the load circuitry 340.sub.A of the first section 301 may be labelled with the prefix “first” and nodes 314.sub.B, 316.sub.B and 312.sub.B, impedances 320.sub.B, 330.sub.B and 350.sub.B, and load circuitry 340.sub.B of the second section 302 may be labelled with the prefix “second” to distinguish elements of the first and second sections 301 and 302 from each other. The first and second tail nodes 312.sub.A and 312.sub.B may be connected to the same voltage reference or power supply node V.sub.H (e.g. AVD as shown in FIG. 9) and thereby may be referred to together as a tail node 312. First and second load circuitry 340.sub.A and 340.sub.B may be referred together as load circuitry 340. Load circuitry 340 comprises a biasing node 342. The load circuitry 340 (or subsequent circuitry connected beyond the load circuitry 340) will of course be connected to a voltage reference (power supply node) V.sub.L whose voltage level is below that of the voltage reference (power supply node) V.sub.H. The voltage reference (power supply node) V.sub.H may be referred to as a high voltage reference and the voltage reference (power supply node) V.sub.L may be referred as a low voltage reference, and the potential difference between V.sub.H and V.sub.L may be referred to as the supply voltage.

(69) The first section 301 can be described as comprising a first current path 300.sub.A extending from the tail node 312 via the first intermediate node 316.sub.A to a first load node (which as shown in FIG. 9 is the same as the first intermediate node 316.sub.A but may be provided separately from the first intermediate node 316A) to provide a first load current at the first intermediate (or load) node 316.sub.A for use by the load circuitry 340, wherein the first supply-connection impedance 320.sub.A is connected along the first current path 300.sub.A between the tail node 312 and the first intermediate node 316.sub.A.

(70) The second section 302 can be described as comprising a second current path 300.sub.B extending from the tail node 312 via the second intermediate node 316.sub.B to a second load node (which as shown in FIG. 9 is the same as the second intermediate node 316.sub.B but may well be provided separately from the second intermediate node 316.sub.B) to provide a second load current at the second intermediate (or load) node 316.sub.B for use by the load circuitry 340, wherein the second supply-connection impedance 320.sub.B is connected along the second current path 300.sub.B between the tail node 312 and the second intermediate node 316.sub.B. The first and second load currents define a differential current signal upon which the load circuitry 340 is configured to operate. The first and second input nodes 314.sub.A and 314.sub.8 are connected to the first and second intermediate nodes 316.sub.A and 316.sub.B via the first and second input-connection impedances 330.sub.A and 330.sub.B, respectively, so that the differential current signal is dependent on the differential input voltage signal. The first and second load currents comprise respective DC bias current components (defined by the first and second supply-connection impedances 320.sub.A and 320.sub.B, respectively, the voltage level of the voltage reference (power supply node) V.sub.H, and a common-mode voltage indicative of a common mode between voltages at the first and second intermediate nodes 316.sub.A and 316.sub.B), and also respective AC current components dependent on the differential input voltage signal (V.sub.INP and V.sub.INM).

(71) The control circuitry 395 is configured, based on measurement of the common mode voltage indicative of the common mode between voltages at the first and second intermediate nodes 316.sub.A and 316.sub.B, to control a biasing signal S.sub.B provided to the biasing node 342 of the load circuitry 340 to regulate the common mode voltage. Effectively, the biasing signal S.sub.B biases (regulates) operation (e.g. an operating point) of the load circuitry 340 which in turn affects (regulates) the common mode voltage. A common mode control loop is thus implemented. Thereby, the DC bias current components of the first and second load currents are regulated, respectively. The control circuitry 395 may comprise the first and second measurement impedances 350.sub.A and 350.sub.B.

(72) The load circuitry 340 as shown in FIG. 9 corresponds closely to the load circuitry 40 in FIG. 4 and the load circuitry 240 in FIG. 5, and equivalent considerations apply. That is, the switches 340A.sub.0 to 340A.sub.N-1 and 340B.sub.0 to 340B.sub.N-1 may be referred to as sampling switches or sampler switches; these sampling switches may be the sampling switches of a current-mode sampler corresponding to sampler 42 (in such a case the sampling switches 340A.sub.0 to 340A.sub.N-1 and 340B.sub.0 to 340B.sub.N-1 may be controlled by time-interleaved clock signals). The load circuitry 340 of the sampler circuitry 300 may comprise any current-mode circuitry capable of receiving a biasing signal (e.g. the biasing signal S.sub.B). The load circuitry 340 comprises the load circuitry 340.sub.A of the first section 301 and the load circuitry 340.sub.B of the second section 302 as shown in FIG. 9.

(73) Sampler circuitry 300 basically works in a similar way to the sampler circuitry 100 and 200: by receiving the (differential) input voltage signal and by employing impedances to passively convert the received input voltage signal into an equivalent input current signal. For example, the input current signal is received by the load circuitry 340 between the load nodes 316.sub.A and 316.sub.B (and the input current signal may be referred to as a load current or as a differential current signal). In this regard, sampler circuitry 300 may be considered to comprise voltage-to-current conversion circuitry, its output being the current signal received by the load circuitry 340 between the load nodes 316.sub.A and 316.sub.B (the load current). Further, the sampler circuitry 300 may be referred to simply as circuitry or a circuitry system (for example, where the load circuitry 340 is current-mode circuitry other than sampler circuitry).

(74) To describe in further detail the operation of the second example arrangement 300, reference is first made back to the sampler circuitry 100 of FIG. 4. In the following description, the shunting capacitors 33.sub.A and 33.sub.B of FIG. 4 are ignored for simplicity.

(75) The current at the input node 14.sub.A due to the input voltage signal V.sub.INP may be referred to as I.sub.INP. Considering the first section 101 of the sampler circuitry 100 (with the understanding that the sampler circuitry 100 may be single-ended or differential and in the case of differential sampler circuitry 100 equivalent analysis applies to the second section 102), the proportion of the current I.sub.INP through the first and second impedances 20A and 30.sub.A can be adjusted by appropriate selection of the first and second impedances 20.sub.A and 30.sub.A (in particular of the resistors 21.sub.A and 31.sub.A). It is possible to select these impedances (resistors) for each application but difficult to make them switchable without affecting the bandwidth of the sampler circuitry 100 and parasitic capacitance (particularly at the input node). For the purpose of the following description it is assumed that the sampler circuitry 100 connects to the input of sub-ADC units (i.e. that the load circuitry 40 is a front-end sampler whose transistors serve as sampler switches which provide current pulse samples to sub-ADC units). It will be appreciated that a similar analysis could be applied for any current-mode circuit.

(76) At low frequency of the (differential) input voltage signal, the portion I.sub.2L of the current I.sub.INP that flows towards the sampler switches (i.e. the input-dependent current at low frequency) can be calculated/approximated as (Equation 1):
I.sub.2L=(R.sub.2/(R.sub.2+R.sub.1+1/g.sub.m))×I.sub.INP
where R.sub.1 and R.sub.2 are the resistance values of the resistors 31.sub.A and 21.sub.A, respectively, and is the transconductance of the sampler switches.

(77) At high frequency of the (differential) input voltage signal, ignoring the frequency response of the sampler switches, the portion I.sub.2H of the current I.sub.INP that flows towards the sampler switches (i.e. the input-dependent current at high frequency) can be calculated/approximated as (Equation 2):
I.sub.2L=((R.sub.2+L.sub.1×ω)/(R.sub.2+L.sub.1×ω+R.sub.1+1/g.sub.m))×I.sub.INP
where L.sub.1 is the inductance value of the inductor 22.sub.A and ω=2πfin, where fin is the input frequency, i.e. of the input voltage signal V.sub.INP.

(78) Assuming that at sufficiently high input frequencies (ω=2πfin), L.sub.1 is large enough such that (Equation 3):
R.sub.2+L.sub.1×ω>>R.sub.1+1/g.sub.m,
then Equation 2 can be approximated as follows (Equation 4):

(79) The amount of high frequency gain achievable (i.e. the input-dependent current at high frequency compared to the input-dependent current at low frequency), taking into account the approximation (Equation 3) is Equation 4 divided by Equation 1. Therefore the amount of high frequency gain achievable G.sub.MAX is (Equation 5):
G.sub.MAX=1+R.sub.1/R.sub.2+1/g.sub.mR.sub.2

(80) Equation 5 shows the maximum gain achievable (i.e. the input-dependent current at high frequency compared to at low frequency) with the sampler circuitry 100. In practice the amount of gain achievable is limited by the desire for a good S11 parameter. A similar analysis can be carried out for S11 parameter calculation as follows. At low frequencies, the impedance Z.sub.INL (L for low frequency) seen looking into the input node 14.sub.A from the input terminal 15.sub.A can be calculated/approximated as (Equation 6):
Z.sub.INL=(R.sub.1+1/g.sub.m)∥R.sub.2=Z.sub.0
where ∥ means in parallel with, and where Z.sub.0 (ohms) is the characteristic impedance of the system, such as an RF system, to be connected at the input (e.g. 50 ohm). At high frequencies, using the approximation of Equation 3, the impedance Z.sub.INH (H for high frequency) seen looking into the input node 14.sub.A from the input terminal 15.sub.A can be calculated/approximated as (Equation 7):
Z.sub.INH=(R.sub.1+1/g.sub.m)∥(R.sub.2+L.sub.1×ω)˜(R.sub.1+1/g.sub.m)

(81) Using Equation 6 in Equation 7, the high frequency impedance Z.sub.INH can be calculated/approximated as (Equation 8):
Z.sub.INH=Z.sub.0×R.sub.2/(R.sub.2−Z.sub.0)

(82) Therefore the reflection coefficient (S11 parameter) can be calculated as (Equation 9):
S11=(Z.sub.INH−Z.sub.0)/(Z.sub.INH+Z.sub.0)=Z.sub.0/(2R.sub.2−Z.sub.0)

(83) As an example, R.sub.1=50Ω, R.sub.2=100Ω and 1/g.sub.m=50Ω. In this case, the maximum AC gain (i.e. amount of high frequency gain achievable) according to Equation 5 is (Equation 10):
G.sub.MAX=1+50/100+50/100=2˜6 dB
(for completeness, in Equation 10, G.sub.MAX=2 is unit-less; in logarithmic scale it corresponds to 20*log.sub.10(2) which is ˜6 dB). Further, the S11 parameter (in decibels) in this case can be calculated according to Equation 9 as (Equation 11);
S11=20×log(50/(200−50))=−9.5 dB

(84) Reference is now made again to the second example arrangement 300 shown in FIG. 9.

(85) Operation of sampler circuitry 300 will now be described, focusing sometimes on only the first section 301 with the understanding that corresponding considerations apply for the second section 302. Comparing the sampler circuitry 300 to the sampler circuitry 100, it is apparent that (among other differences) the current source 10 (which generates the sampler or bias current I.sub.DC) is absent from the sampler circuitry 300, whereas it is present in the sampler circuitry 100. Another difference is that in the sampler circuitry 300 the input-connection impedance 330.sub.A (which can be considered to correspond with the second impedance 30.sub.A of the sampler circuitry 100) is outside of the first current path 300.sub.A (in other words, outside the stack, the stack meaning the stack of elements along the first current path 300.sub.A), whereas in the sampler circuitry 100 the second impedance 30.sub.A is connected along a current path from the tail node 12 to the load node 16.sub.A (in other words, within the stack, the stack meaning the stack of elements along the current path from V.sub.1-1 (AVD) via the tail node 12 to the load node 16.sub.A).

(86) The first and second measurement impedances 350.sub.A and 350.sub.B are used to sense the common mode voltage indicative of the common mode between voltages at the first and second intermediate nodes 316.sub.A and 316.sub.B. The first and second measurement impedances 350.sub.A and 350.sub.B are shown in FIG. 9 as resistors by way of example but may be implemented as complex impedances. Preferably, the first and second measurement impedances 350.sub.A and 350.sub.B are large (relatively speaking) resistors (i.e. resistors having a large resistance value).

(87) The control circuitry 395 receives a measurement signal S.sub.CM indicative of the common mode voltage from the measurement node 318. The control circuitry 395 controls the biasing signal S.sub.B which is provided to the biasing node 342 in order to regulate the common mode voltage. That is, the control circuitry 395 controls the biasing signal S.sub.B to bring the measurement signal S.sub.CM to or towards a target value corresponding to a target common mode voltage. Thereby, the control circuitry 395 controls or regulates (i.e. brings to or towards a target value) the DC bias current components of the first and second load currents, respectively, because the DC voltage drops over the impedances 320.sub.A and 320.sub.B are then controlled/regulated. The control circuitry 395 may thus be considered the control element of a common mode control loop.

(88) The load circuitry 340 shown in FIG. 9 comprises switches 340A.sub.0 to 340A.sub.N-1 and 340B.sub.0 to 340B.sub.N-1 equivalent to the corresponding switches shown in FIGS. 4 and 5. The switches 340A.sub.0 to 340B.sub.N-1 are shown in FIG. 9 as switching transistors, and may also be referred to as sampling switches or sampler switches. As described above, the load circuitry 340 may however in general be any current-mode circuitry.

(89) In an example in which the load circuitry 340 comprises the switches 340A.sub.0 to 340A.sub.N-1 and 340B.sub.0 to 340B.sub.N-1, the biasing signal S.sub.B may control the DC level of gate-control switching signals provided to gate terminals to the switching transistors 340A.sub.0 to 340B.sub.N-1. For example, the biasing signal may comprise one or more individual signals for one or more switching transistors 340A.sub.0 to 340B.sub.N-1.

(90) In the following description of the operation of sampler circuitry 300, it is assumed that the load circuitry 340 is as shown in FIG. 9 and that the biasing signal S.sub.B controls the DC level of gate-control switching signals provided to gate terminals of the switching transistors 340A.sub.0 to 340B.sub.N-1. In other words, a feedback loop is used to set the DC voltage of the gates of the sampler switches such that a DC component of the current which flows through the first and second supply-connection impedances 320.sub.A and 320.sub.6 is constant or regulated over PVT (process, voltage, temperature). In this case (and considering the first current path 300.sub.A), the control circuitry 395 controls the biasing signal S.sub.B so that the common mode voltage V.sub.CM satisfies the following (Equation 12):
AVD=V.sub.OM+R.sub.2×I.sub.SAMP/2
where AVD is the voltage reference V.sub.H, R.sub.2 is the resistance value of the impedance 320.sub.A, I.sub.SAMP is the desired current drawn from AVD by the sampler circuitry 300 (corresponding to I.sub.DC in FIG. 4), and the impedances 320.sub.A and 320.sub.B are the same as one another.

(91) Comparing the sampler circuitry 300 to the sampler circuitry 100, an amount of additional voltage headroom of the sampler circuitry 300 can be determined by calculating the voltage headroom used up by the second impedance 30.sub.A and the current source 10 in the sampler circuitry 100 (because the current source 10 is not required in the sampler circuitry 300 and because the second impedance 30.sub.A corresponds to the input-connection impedance 330A which is not in the stack).

(92) This additional voltage headroom ΔAVD can be calculated as (Equation 13):
ΔAVD=R.sub.1×I.sub.SAMP/2+V.sub.OD,SAMP
where V.sub.OD,SAMP is the overdrive voltage of the current source 10 and R.sub.1×I.sub.SAMP/2 is the voltage drop across the second impedance 30.sub.A of the sampler circuitry 100.

(93) Due to this additional voltage headroom of the sampler circuitry 300 compared to the sampler circuitry 100, the supply voltage can be reduced (i.e. the difference between the high and low voltage references reduced). That is, ΔAVD may be considered an amount of supply voltage drop achievable using the sampler circuitry 300 compared to the sampler circuitry 100.

(94) Continuing the example assuming that the load circuitry 340 comprises the sampling switches as shown in FIG. 9, at low frequencies (L for low frequency) the current I.sub.2L sampled by the sampler switches (the input-dependent current) from the first current path 300.sub.A can be calculated as (Equation 14):
I.sub.2L=(R.sub.2/(R.sub.2+1/g.sub.m))×I.sub.INP
where I.sub.INP is the current drawn in at the input node 314.sub.A, R.sub.2 is again the resistance value of the impedance 320.sub.A, and g.sub.m is the transconductance of the sampler switches. At high frequencies the current I.sub.2H (H for high frequency) sampled by the sampler switches (the input-dependent current) from the first current path 300.sub.A can be calculated as (Equation 15):
I.sub.2H=((R.sub.2+L.sub.1×ω)/(R.sub.2+L.sub.1×ω+1/g.sub.m))×I.sub.INP
where L.sub.1 is the inductance value of the supply-connection impedance 320.sub.A and ω=2πfin, where fin is the input frequency, i.e. of the input voltage signal V.sub.INP. Assuming that (Equation 16):
R.sub.2+L.sub.1×ω>>1/g.sub.m
then Equation 15 can be approximated as follows (Equation 17):
I.sub.2H˜I.sub.INP

(95) Similar to Equation 5 above, the amount of high frequency gain achievable (i.e. the input-dependent current at high frequency compared to the input-dependent current at low frequency) of sampler circuitry 300 can be calculated/approximated by dividing Equation 17 by Equation 14. Therefore the amount of high frequency gain achievable G.sub.MAX is (Equation 18):
G.sub.MAX=1+1/g.sub.mR.sub.2

(96) Similar to Equations 6 to 9 above, the reflection coefficient (S11 parameter) can be calculated as follows. At low frequencies, the impedance Z.sub.INL seen looking into the input node 314A from the input terminal 315A can be calculated/approximated as (Equation 19):
Z.sub.INL=R.sub.1+1/g.sub.m∥R.sub.2=Z.sub.0
where R.sub.1 is the resistance value of the input-connection impedance 330A. At high frequencies, the impedance Z.sub.INH (H for high frequency) seen looking into the input node 314.sub.A from the input terminal 315.sub.A can be calculated/approximated as (Equation 20):
Z.sub.INH=R.sub.1+1/g.sub.m∥(R.sub.2+L.sub.1×ω)˜(R.sub.1+1/g.sub.m)

(97) Using Equation 19 in Equation 20, the high frequency impedance Z.sub.INH can be calculated/approximated as (Equation 21):
Z.sub.INH=Z.sub.0+(1/g.sub.m)/(1+g.sub.m×R.sub.2)

(98) Therefore the reflection coefficient (S11 parameter) can be calculated as (Equation 22):
S11=1/(1+2g.sub.m×Z.sub.0×(1+g.sub.m×R.sub.2))

(99) A comparison can now be made between the sampler circuitry 100 and the sampler circuitry 300.

(100) Both sampler circuitry 100 and sampler circuitry 300 provide similar high frequency gain. As an example, R.sub.1=25Ω, R.sub.2=50Ω and 1/g.sub.m=50Ω. In this case, the maximum AC gain (i.e. amount of high frequency gain achievable) according to Equation 18 is (Equation 23):
G.sub.MAX=1+50/50=2˜6 dB

(101) This is similar to the gain G.sub.MAX calculated for the sampler circuitry 100.

(102) The S11 parameter (in dB) for the sampler circuitry 300 can be calculated using Equation 22 as (Equation 24):
S11=1/(1+(2/50)×50×(1+50/50))=1/5˜−14 dB

(103) Comparing the gain and the S11 parameter for the above examples (i.e. Equations 10, 11, 23 and 24), it is apparent that the sampler circuitry 300 can provide a similar gain compared to the sampler circuitry 100 whilst providing improved S11 performance (S11 scattering parameter value).

(104) Due to the additional voltage headroom of the sampler circuitry 300 compared to the sampler circuitry 100, the supply voltage can be lowered (i.e. the difference between the high and low voltage references V.sub.H and V.sub.L can be reduced) which is advantageous from a power-saving point of view. Another advantage is that the additional voltage headroom can be used in the load circuitry and/or subsequent circuitry.

(105) FIG. 10 is a schematic diagram of a modified second example arrangement 400 of sampler circuitry.

(106) Sampler circuitry 400 comprises first and second matching (or corresponding or complementary) sections 401 and 402 for the two differential inputs, the first and second sections 401 and 402 corresponding closely with the first and second sections 301 and 302 of sampler circuitry 300. Each element of the sampler circuitry 400 in common with sampler circuitry 300 has the same reference numeral as the corresponding element of the sampler circuitry 300. The principle of operation of the sampler circuitry 400 is substantially the same as that of the sampler circuitry 300 and duplicate description of elements common to sampler circuitry 300 and sampler circuitry 400 is omitted.

(107) The sampler circuitry 400 additionally comprises an auxiliary current path 403 connected between the first and second input nodes 314.sub.A and 314.sub.6, and having an auxiliary impedance 370 connected therealong. The auxiliary impedance 370 as shown in FIG. 10 comprises two resistors 371 and 375 and two inductors 372 and 374. In brief, the auxiliary current path 403 provides an additional AC signal path for the input current and consequently, another gain factor (i.e. gain boosting at high frequencies, relative to at low frequencies) at frequencies when the inductors 372 and 374 begin to dominate. The auxiliary impedance 370 can of course have other arrangements comprising any element(s) giving rise to an impedance, for example a single resistor and a single inductor.

(108) Similar calculations as for the sampler circuitry 300 can be applied to the sampler circuitry 400 as follows, focusing on the first section 401 with the understanding that equivalent analysis can be carried out for the second section 402. At low frequencies (of the input voltage signal V.sub.INP) the current I.sub.2L sampled by the sampler switches (the input-dependent current) from the first current path 300.sub.A, and including a contribution from the auxiliary current path 403, can be calculated as (Equation 25):
I.sub.2L=(R.sub.3/(R.sub.3+R.sub.1+R.sub.2∥(1/g.sub.m)))×(R.sub.2/(R.sub.2+1/g.sub.m))×I.sub.INP
where R.sub.3 is the resistance value of the auxiliary impedance 370A and the other quantities are as described with reference to the sampler circuitry 300. At high frequency, the inductance values of the supply-connection impedance 330.sub.A and of the auxiliary impedance 370.sub.A become large and (substantially) all the input current I.sub.INP goes into the sampler switches. Therefore at high frequency the current I.sub.2H sampled by the sampler switches (the input-dependent current) from the first current path 300A, and including a contribution from the auxiliary current path 403, can be calculated as (Equation 26):
I.sub.2H˜I.sub.INP

(109) The amount of high frequency gain achievable or AC gain (i.e. the input-dependent current at high frequency compared to the input-dependent current at low frequency) is Equation 26 divided by Equation 25. Therefore the amount of high frequency gain achievable G.sub.MAX is (Equation 27):
G.sub.MAX=(1+R.sub.1/R.sub.3+(R.sub.2∥1/g.sub.m)/R.sub.3)×(1+1/g.sub.mR.sub.2)

(110) Comparing the amount of high frequency gain achievable (or AC gain) for the sampler circuitry 400 to that for the sampler circuitry 300 (i.e. comparing equations 18 and 27), it is apparent that the amount of extra gain achieved due to the auxiliary current path 403 is (Equation 28):
G.sub.boost=1+R.sub.1/R.sub.3+(R.sub.2∥1/g.sub.m)/R.sub.3

(111) As an example for the sampler circuitry 400, R.sub.1=50Ω, R.sub.2=50Ω, R.sub.3=150Ω and 1/g.sub.m=50Ω. According to Equation 28, the extra gain of the sampler circuitry 400 compared to the sampler circuitry 300 is (Equation 29):
G.sub.boost=(1+50/150+(50∥50)/150)=1.5˜3.5 dB

(112) Referring to Equation 23, this means that the total amount of high frequency gain achievable (i.e. the input-dependent current at high frequency compared to the input-dependent current at low frequency) for the sampler circuitry 400 is approximately (Equation 30):
G.sub.MAX=6 dB+3.5 dB=9.5 dB

(113) Therefore, the sampler circuitry 400 provides a very large gain with which, when the load circuitry 340 is for example a front-end of a (sub-) ADC, near Nyquist rate bandwidth ADC operation can be achieved.

(114) Continuing the analysis of the sampler circuitry 400, at high frequency the inductance values of the inductors 332.sub.A and 372 (and 374) become very large so that the impedance Z.sub.INH seen looking into the input node 314.sub.A from the input terminal 315.sub.A can be calculated/approximated as (Equation 31):
Z.sub.INH˜(R.sub.1+1/g.sub.m)

(115) It is apparent that this high frequency impedance is similar to the high frequency impedance for the sampler circuitry 100 calculated in Equation 7. Using the example parameter values above, the S11 parameter (reflection coefficient) can be calculated (using Equation 9) as (Equation 32):
S11=(100−50)/(100+50)=1/3˜−9.5 dB

(116) This value for the S11 parameter is similar to the S11 parameter for the sampler circuitry 100 (Equation 11). Therefore the sampler circuitry 400 can operate with much higher AC gain (i.e. the amount of high frequency gain achievable G.sub.MAX, Equation 30) than the sampler circuitry 100 but with similar S11 performance (i.e. Equation 32), whilst there is the additional advantage that the supply voltage (i.e. the difference between the high and low voltage references) can be dropped compared to the sampler circuitry 100 for example by the amount calculated in (13).

(117) To demonstrate the advantages associated with the second example arrangement 300 and the modified second example arrangement 400, circuitry has been designed (in particular a 77 GSa/s sampler) and simulated using the sampler circuitry 100, the second example arrangement 300 and the modified second example arrangement 400.

(118) FIG. 11A is a graph showing the signal level of the reconstructed signal at the output of the designed and simulated 77 GSa/s sampler with respect to the input signal (V.sub.INP/M) frequency for the sampler circuitry 100 (without control), the second example arrangement 300 (with control) and the modified second example arrangement 400 (with control (boosted)). Also marked on the graph in FIG. 11A is the frequency at 0.3 fs bandwidth, which is a useful example frequency to consider (for example, in current-mode ADCs such as disclosed in EP2211468, a “sine effect” due to the integration of charge/current can theoretically limit the bandwidth of the system to a value more than 0.3 fs but less than the Nyquist bandwidth), and the Nyquist bandwidth.

(119) It is apparent from FIG. 11A that the second example arrangement 300 provides improved bandwidth compared to the sampler circuitry 100 and that the modified second example arrangement 400 provides improved bandwidth compared to the sampler circuitry 100 and to the second example arrangement 300. In the simulation on which the graph in FIG. 11A is based, the sampler circuitry 100 was implemented with a 1.8 V supply voltage (i.e. difference between high and low reference voltages) while the second example arrangement 300 and the modified second example arrangement 400 were implemented with a 1.5 V supply voltage, demonstrating the advantage of supply voltage reduction. The second example arrangement 300 and the modified second example arrangement 400 can work with supply voltages less than 1.5 V.

(120) FIG. 11B is a graph showing the S11 parameter value profile of the designed and simulated 77 GSa/s sampler for the sampler circuitry 100 (without control), the second example arrangement 300 (with control) and the modified second example arrangement 400 (with control (boosted)). Also marked on the graph in FIG. 11B with a dotted line is an example S11 specification. In the simulation on which the graph in FIG. 11B is based, the sampler circuitry 100 was implemented with a 1.8 V supply voltage (i.e. difference between high and low reference voltages) while the second example arrangement 300 and the modified second example arrangement 400 were implemented with a 1.5 V supply voltage, demonstrating the advantage of supply voltage reduction. The second example arrangement 300 and the modified second example arrangement 400 can work with supply voltages less than 1.5 V.

(121) It is apparent from FIG. 11B that the second example arrangement 300 provides the best S11 performance while the modified second example arrangement 400 provides similar S11 performance to the sampler circuitry 100 as predicted in Equation 32, but the modified second example arrangement 400 provides more gain compared to the sampler circuitry 100 and to the second example arrangement 300.

(122) In summary, some of the advantages of the second example arrangement 300 and the modified second example arrangement 400 (both of which may be referred to as a low voltage, gain boosted current mode sampler) compared to, for example, the sampler circuitry 100 are as follows. Removal of current source (i.e. current source 10 in sampler circuitry 100) from the stack. The current source (as a separate element) is not required in either of the first and second current paths 300.sub.A and 300.sub.B. This results in additional voltage headroom. The removal of the current source from the stack is advantageous from a power-saving point of view. Removal of matching network from stack. That is, the input-connection impedances 330.sub.A and 330.sub.B are outside the first and second current paths 300.sub.A and 300.sub.B, respectively. This results in improved S11 performance, relaxed requirements concerning ensuring good S11 performance, and improved voltage headroom. Reduction in supply voltage. Due to the additional voltage headroom, the supply voltage can be reduced. This is advantageous from a power-saving point of view. Improved S11 (input matching) performance. The S11 performance of the sampler circuitry 300 and 400 is better than (or at least as good as) the S11 performance of the sampler circuitry 100, whilst at the same time a better gain “profile” and improved voltage headroom can be provided by the sampler circuitry 300 and 400. Addition of gain (high frequency compared to low frequency) into the signal path without affecting the S11 parameter, in the sense of (relative) boosting at high frequencies (i.e. sacrificing gain at low frequencies so that it appears better at high frequencies—i.e. to affect the gain profile but without adding overall DC to high frequency gain, such as active-device gain). As described above, sampler circuitry 300 provides improved gain (high frequency gain boosting) compared to the sampler circuitry 100 and the sampler circuitry 400 provides improved gain (high frequency gain boosting) compared to the sampler circuitry 100 and 300. At the same time, the sampler circuitry 300 and 400 can provide improved (or at least as good) S11 performance and also improved voltage headroom. Bandwidth extension. The bandwidth can be extended due to the improved gain “profile” and due to the improved S11 parameter.

(123) Sampler circuitry 100, 200, 300 and 400 are shown in the Figures as comprising P-channel devices (in this case, field-effect transistors). N-channel devices may also be used in place of P-channel devices, i.e. by providing the circuitry the “other way up”.

(124) It will be appreciated that sampler circuitry 200, 300, 400 could be provided along with mixed-signal circuitry such as ADC circuitry (or, in some arrangements, DAC circuitry). As illustrated in FIG. 12A, for example, sampler circuitry 200, 300, 400 disclosed herein could be provided along with or as part of ADC circuitry 1.

(125) Circuitry of the present invention may be implemented as integrated circuitry, for example on an IC chip such as a flip chip. FIG. 12B is a schematic diagram of an integrated circuit 2 comprising the ADC circuitry 1. An integrated circuit comprising the sampler circuitry 200, 300 and/or 400 could also be provided.

(126) The present invention extends to integrated circuitry and IC chips as mentioned above, circuit boards comprising such IC chips, and communication networks (for example, internet fiber-optic networks and wireless networks) and network equipment of such networks, comprising such circuit boards. Circuitry of the present invention may also be implemented with discrete components provided on circuit boards. Circuitry of the present invention may be implemented alone (as a standalone circuit) or together with other circuitry.

(127) In any of the above method aspects (for example, control of values stored in the register 295 or control of the control unit 395), the various features as appropriate may be implemented in hardware, or as software modules running on one or more processors. Features of one aspect may be applied to any of the other aspects.

(128) The invention also provides a computer program or a computer program product for carrying out any of the methods described herein, and a computer readable medium having stored thereon a program for carrying out any of the methods described herein. A computer program embodying the invention may be stored on a computer-readable medium, or it could, for example, be in the form of a signal such as a downloadable data signal provided from an Internet website, or it could be in any other form.

(129) Further embodiments may be provided within the spirit and scope of the present invention as disclosed herein.