Method for operating a computer system

Abstract

A method for operating a computer system including identical first and second processors operated in parallel and having at least two processor cores each, includes operating one processor core of each processor securely based on a secure operating system achieving or exceeding a specified security level, each executing at least one application program securely by achieving the specified security level. The processor cores securely execute the same application program or programs. Remaining processor cores of the first processor are switched off or operated securely, based on the secure operating system or one or more other secure operating systems under the secure execution of the same and/or other application programs. At least one processor core in the second processor is operated nonsecurely based on a nonsecure operating system not achieving the specified security level and executes at least one application program nonsecurely, falling short of the specified security level.

Claims

1. A method for operating a computer system, the method comprising: providing the computer system with at least first and second identical processors being operated in parallel providing the first processor of the computer system with at least first, second and third selected processor cores, and providing the second processor of the computer system with at least fourth, fifth and sixth processor cores; securely operating the first selected processor core with a secure operating system achieving or exceeding a specified security level and securely executing a first application program by achieving the specified security level; operating the second selected processor core with the secure operating system or another secure operating system and securely executing a second application program; and switching off the third selected processor core; securely operating the fourth processor core with a secure operating system identical to the second processor core and securely executing the second application program; operating the fifth processor core with a secure operating system identical to the first processor core and securely executing the first application program; and non-securely operating the sixth processor core with a non-secure operating system not achieving the specified security level and non-securely executing at least one application program by falling short of the specified security level.

2. The method according to claim 1, which further comprises comparing memory contents of the two identically operated processor cores and concluding a faulty reaction of the non-securely operated processor core of the second processor to the securely operated processor core of the second processor when the memory contents differ from one another in whole or in part or with regard to operating data of the secure application program, in the two securely operated processor cores or differ from one another beyond a specified extent.

3. The method according to claim 1, which further comprises: relative to a processor structure, providing the fifth processor core as a different processor core than the first processor core in the first processor and locating the fifth processor core elsewhere within the second processor from the first processor core in the first processor; and relative to the processor structure, providing the fourth processor core as a different processor core than the second processor core in the first processor and locating the fourth processor core elsewhere within the second processor from the second processor core in the first processor.

4. The method according to claim 1, which further comprises comparing working results of the securely operated application program or application programs of the first processor with working results of a corresponding securely operated application program or application programs of the second processor, and generating a warning signal when the working results differ or differ from one another beyond a specified extent.

5. The method according to claim 1, which further comprises comparing memory contents of the first and fifth processor cores and memory contents of the second and fourth processor cores with one another and concluding a faulty reaction of the non-securely operated processor core of the second processor to the securely operated processor cores of the second processor when the memory contents differ from one another in whole or in part or with regard to operating data of the secure application programs, or differ from one another beyond a specified extent.

6. The method according to claim 1, which further comprises: switching off at least one processor core of the first processor and operating at least one processor core of the first processor, and only securely operating all of the operated processor cores of the first processor; assigning each operated processor core of the first processor to precisely one processor core of the second processor operating with a secure operating system identical to the assigned processor core of the first processor and executing an application program or application programs identical to the assigned processor core of the first processor; and operating at least one processor core in the second processor with a non-secure operating system not achieving the specified security level, and non-securely executing an application program falling short of the specified security level.

7. The method according to claim 6, which further comprises relative to a processor structure, spatially locating the securely operated processor cores of the second processor elsewhere within the second processor from the assigned processor cores in the first processor.

8. The method according to claim 1, which further comprises using the computer system to operate a technical system or a rail-vehicle-side component of a rail vehicle or a trackside component or a control center or signal box.

9. A computer system, comprising: at least first and second identical processors being operated in parallel, the first processor having at least first, second and third selected processor cores, and the second processor having at least fourth, fifth and sixth processor cores; the first selected processor core being operated securely based on a secure operating system achieving or exceeding a specified security level and each securely executing at least one application program achieving the specified security level; the second selected processor core being operated with the secure operating system or another secure operating system and securely executing a second application program; third selected processor core being switched off; the fourth processor core being operated with a secure operating system identical to the second processor core and securely executing the second application program; the fifth processor core being operated with a secure operating system identical to the first processor core and securely executing the first application program; and the sixth processor core being non-securely operated based on a non-secure operating system not achieving the specified security level and non-securely executing at least one application program falling short of the specified security level.

10. The computer system according to claim 9, which further comprises a comparison facility comparing memory contents of said identically operated processor cores with one another and concluding a faulty reaction of said non-securely operated processor core to said securely operated processor core of said second processor when said memory contents differ from one another in whole or in part or with regard to operating data of said secure application program, in said two securely operated processor cores or differ beyond a specified extent.

11. The computer system according to claim 9, wherein: relative to a processor structure, said fourth processor core is a different processor core than said second processor core in said first processor and is located elsewhere within said second processor from said second processor core in said first processor; and relative to said processor structure, said fifth processor core is a different processor core than said first processor core in said first processor and is located elsewhere within said second processor from said first processor core in said first processor.

12. The computer system according to claim 9, wherein: at least one of said processor cores of said first processor is switched off and at least one of said processor cores of said first processor is operated, and all of said operated processor cores of said first processor are only operated securely; each operated processor core of said first processor is assigned precisely one respective processor core of said second processor being operated identically with a secure operating system identical to said assigned processor core of said first processor and executes an application program or application programs identical to said assigned processor core of said first processor; at least one of said processor cores in said second processor is operated with a non-secure operating system not achieving the specified security level and non-securely executes at least one application program falling short of the specified security level; and relative to the processor structure, said securely operated processor cores of said second processor are spatially located elsewhere within said second processor from said assigned processor cores in said first processor.

13. A component for a technical system, the component comprising a computer system according to claim 9.

14. The component according to claim 13, wherein: the component is a vehicle-side component or a control device of a vehicle or of a rail vehicle, or the component is a trackside component or a control center computer of a control center of a railway track system or a signal box computer of a signal box of a railway track system.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

(1) FIG. 1 An exemplary embodiment of a computer system according to the invention, in which two processors each have three processor cores, wherein an exemplary embodiment of the method according to the invention is explained with reference to the exemplary embodiment according to FIG. 1,

(2) FIG. 2 A further exemplary embodiment of a computer system according to the invention, in which two processors each have four processor cores, wherein a further exemplary embodiment of the method according to the invention is explained with reference to the exemplary embodiment according to FIG. 2, and

(3) FIG. 3 An exemplary embodiment of a railway track system and an exemplary embodiment of a rail vehicle equipped with computer systems according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

(4) For the sake of clarity, the same reference characters are always used for identical or comparable components in the figures.

(5) FIG. 1 shows a computer system 5 comprising six processor cores, namely a first processor core 11, a second processor core 12, a third processor core 13, a fourth processor core 14, a fifth processor core 15 and a sixth processor core 16.

(6) The three processor cores 11, 12 and 13 are located in a first processor 10 of the computer system 5 and the processor cores 14, 15 and 16 are located in a second processor 20 of the computer system 5.

(7) The two processors 10 and 20 are identical and each have a semiconductor chip 100. The semiconductor chips 100 comprise chip sections K1, K2 and K3, in each of which a processor core is arranged.

(8) In the exemplary embodiment according to FIG. 1, the chip section K1 is located at the same point—relative to the processor structure and relative to the semiconductor chip 100—as the chip section K1 in the second processor 20. In a corresponding manner, the chip sections K2 and K3 in the semiconductor chip 100 of the first processor 10 are in each case located at the same point as the corresponding chip sections K2 and K3 in the semiconductor chip 100 of the second processor 20.

(9) The two processors 10 and 20 each execute a first application program APP1 and a second application program APP2 securely using a secure operating system SOS. The “secure” execution of an application program is here understood to mean, by way of example, an application program which complies with the standards EN50128 and EN50129. “Secure” operating systems SOS are here likewise understood to mean, by way of example, those operating systems which comply with the standards EN50128 and EN50129.

(10) The application programs APP1 and APP2 are executed in the two processors 10 and 20 in different chip sections or in various processor cores. Thus, it can be seen in FIG. 1 that the first application program APP1 is executed in the first processor core 11, here that is to say in the first chip section K1 of the first processor, while the first application program APP1 is executed in the second processor 20 of the fifth processor core 15, here that is to say in the second chip section K2. The first application program APP1 is therefore executed in different chip sections K1 and K2 of the semiconductor chips 100 of the two processors 10 and 20.

(11) In a corresponding manner, the second application program APP2 is also executed in different chip sections. It can thus be seen that the second application program APP2 is executed by the first processor 10 in the second chip section K2 and thus by the second processor core 12; the second application program APP2 is executed by the second processor 20 in the first chip section K1 and thus by the fourth processor core 14.

(12) By executing the application programs APP1 and APP2 in different chip sections K1 and K2 of the processors 10 and 20 in each case, it is possible for any hardware errors or hardware discrepancies in the semiconductor chips 100 to be easily detected, for example, by comparing working results and/or memory contents of the application programs APP1 and APP2 across processors.

(13) FIG. 1 also shows that the second processor 20 has a non-secure application program APP 3 executed in its chip section K3, that is to say by the sixth processor core 16, using a non-secure operating system OS. Such a non-secure application program APP3 is not executed by the first processor 10; the third chip section K3 is therefore not operated by the first processor 10 and is securely switched off.

(14) By virtue of the division of labor provided in the two processors 10 and 20 in such a way that the first processor 10 is only operated with secure application programs APP1 and APP2 and non-secure application programs, here APP3, are only permitted in the second processor 20, it is possible for any error to be determined in a simple manner by the non-secure application program APP3 or also by the non-secure operating system OS. If the operation of the non-secure application program APP3 in the second processor 20 is faulty and influences the mode of operation of the securely operated processor cores 14 and 15, this can be established by a comparison of the memory contents and/or the working results of the securely operated processor cores 14 and 15 of the second processor 20 with the memory contents and/or working results of the securely operated processor cores 12 and 11 of the solely securely operated first processor 10.

(15) In the exemplary embodiment according to FIG. 1, each processor 10 is in each case assigned a memory 50 which can be integrated in the respective semiconductor chip 100 of the respective processor 10 or 20 or, alternatively, can be formed by a separate component which is assigned to the respective semiconductor chip 100 or the respective processor.

(16) The two memories 50 of the two processors 10 and 20 each have memory areas which are individually assigned to processor cores. Thus, the memory area SP11 of the memory 50 of the first processor 10 is assigned to the first processor core 11 and thereby to the chip section K1 of the first processor 10; the memory areas SP12 and SP13 are assigned to the second processor core 12 or the third processor core 13.

(17) In a corresponding manner, memory areas SP14, SP15 and SP16 of the memory 50 in the second processor 20 are assigned to the fourth processor core 14, the fifth processor core 15 and the sixth processor core 16.

(18) Working results of the application program of the respective processor core can in each case be stored in the memory areas SP11 to SP16, for example, operating data of a technical system which is controlled or managed by the application programs APP1 to APP3. If the technical system is, for example, a railway track system (see FIG. 3), corresponding operating data relating to railway technology, for example, occupied indications, release information, train numbers, train speeds, timetable data, etc. can be stored as memory contents in the memory areas SP11 to SP16.

(19) It is advantageous if the computer system 5 has a comparison facility which enables a comparison of the memory contents of the memory areas. Such a comparison facility can, for example, compare the memory contents of the memory area SP11, which is assigned to the first processor core 11 and thereby to the first application program APP1, with the memory area SP15, which is assigned to the fifth processor core 15 and thereby likewise to the first application program APP1 in the second processor 20, and in the event of a discrepancy between the memory contents, output a warning or error signal.

(20) In a corresponding manner, such a comparison facility can compare the memory contents SP12 and SP14 with one another, in which the working results, for example, operating data, of the second application program APP2 are stored in the two processors 10 and 20.

(21) Such a comparison facility can be implemented by a separate hardware component or by a comparison functionality implemented by means of software which is executed by the securely operated processor cores themselves.

(22) In summary, in the exemplary embodiment according to FIG. 1, an error disclosure of a faulty mode of operation of the non-secure application program APP3 is possible in a very simple way if the latter produces a faulty reaction in the securely operated application programs APP1 and APP2 in the second processor 20 because such a faulty reaction can be detected namely through a comparison with the working results and the mode of operation of the corresponding securely operated application programs APP1 and APP2 of the first processor 10. The error disclosure is based specifically on the idea that in the first processor 10 the processor cores are either operated securely or not at all, and non-secure application programs are only permitted in the second processor 20 so that errors of non-secure application programs simply cannot occur in the first processor 10.

(23) The assignment of the first processor core 11, which executes the first application program APP1, to the chip section K1 of the first processor 10, the assignment of the second processor core 12, which executes the second application program APP2, to the chip section K2 of the first processor 10, the assignment of the fourth processor core 14, which executes the second application program APP2, to the chip section K1 of the second processor 20 and the assignment of the fifth processor core 15, which executes the first application program APP1, to the chip section K2 of the second processor 20 are to be understood here only by way of example; said processor cores or application programs can also be assigned to other chip sections and be differently distributed on the semiconductor chips; this is to be explained by way of example hereinafter with reference to FIG. 2.

(24) FIG. 2 shows a second exemplary embodiment of a computer system 5 which is equipped with two processors 10 and 20. Unlike the exemplary embodiment according to FIG. 1, each of the processors 10 and 20 has four processor cores respectively, that is to say two more than in the exemplary embodiment according to FIG. 1. The two additional processor cores are indicated by the reference characters 17 and 18 in FIG. 2.

(25) The second processor 20 is operated with two non-secure application programs APP3 and APP4 which are executed in the processor cores 16 and 18. Accordingly, two of the processor cores, for example, the processor cores 13 and 17, remain unused in the first processor 10.

(26) Assignment to the chip sections is as follows in FIG. 2, for example: The so-called first processor core 11, which executes the first application program APP1, is assigned to the chip section K4 of the first processor 10, the so-called second processor core 12, which executes the second application program APP2, is assigned to the chip section K2 of the first processor 10, the so-called fourth processor core 14, which executes the second application program APP2, is assigned to the chip section K1 of the second processor 20 and the so-called fifth processor core 15, which executes the first application program APP1, is assigned to the chip section K3 of the second processor 20. The non-secure application programs APP3 and APP4 run in the chip sections K2 and K4 of the second processor 20.

(27) Otherwise, the above explanations apply accordingly in connection with FIG. 1.

(28) FIG. 3 shows an exemplary embodiment of a railway track system 300 on which a rail vehicle 310 is traveling.

(29) The rail vehicle 310 has a control device 310a comprising a computer system 5 according to FIGS. 1 and 2.

(30) The railway track system 300 comprises a trackside component in the form of a signal box computer 320a of a signal box 320. The signal box computer 320a has a computer system 5 according to FIGS. 1 and 2.

(31) With regard to the mode of operation of the control device 310a and the signal box computer 320a, reference is made to the above embodiments in connection with the computer system 5 according to FIGS. 1 and 2.

(32) Although the invention has been illustrated and described in more detail by means of preferred exemplary embodiments, the invention is not limited by the disclosed examples, and other variations may be derived therefrom by a person skilled in the art without departing from the scope of the invention.