HYBRID CONTROL ARCHITECTURE FOR LOAD-ADAPTIVE POWER CONVERTER

Abstract

A pulse width modulated power converter is presented with load-adaptive power transistor scaling scheme using analog-digital hybrid control. The coarse digital control generates an approximate duty cycle necessary for driving a given load and selects an appropriate width of power transistors to minimize redundant power dissipation. The fine analog control provides the final tuning of the duty cycle to compensate for the error from the coarse digital control. The mode switching between the analog and digital controls is accomplished by a mode arbiter which estimates the average duty cycle for the given load condition from limit cycle oscillations induced by the coarse adjustments.

Claims

1. A power converter system, comprising: a power converter configured to receive an input voltage and generate an output voltage that supplies a load, wherein the power converter is comprised of an array of converter circuits coupled in parallel to each other, each converter circuit includes at least one power transistor that regulates the magnitude of the output voltage; and a controller configured to receive an indicator of the output voltage and interfaced with each power transistor in the array of converter circuits, wherein the controller selectively controls conductance through the power transistors in the array of converter circuits such that number of power transistors passing current to the load is proportional to magnitude of the load.

2. The power converter system of claim 1 wherein the controller determines an error signal by comparing the indicator of the output voltage with a reference voltage and generates drive signals for the power transistors in the array of converter circuits in accordance with one of a coarse control scheme or a fine control scheme, wherein the controller, during the coarse control scheme, determines the number of power transistors passing current to the load in accordance with the error signal and selectively controls conductance through the power transistors in the array of converter circuits in accordance with this determination.

3. The power converter system of claim 2 wherein the controller implements the coarse control scheme using a compensator circuit configured to receive the error signal and compute a duty cycle for the power converter in accordance with the error signal; and a plurality of delay circuits configured to receive a pulsed input signal and output the drive signals for each power transistor in the array of converter circuits, wherein each delay circuit corresponds to one of the power transistors and adjusts duty cycle of a drive signal for a corresponding power transistor in accordance with the computed duty cycle for the power converter.

4. The power converter system of claim 3 further comprises a mode arbiter configured to receive a signal indicative of the output voltage and extract information regarding the load using oscillation in the signal indicative of the output voltage.

5. The power converter system of claim 4 wherein the mode arbiter monitors magnitude of oscillation in the signal indicative of the output voltage and, in response to a determination that the magnitude of oscillation falls outside a predefined variance of the reference voltage, interacts with the controller to implement the coarse control scheme.

6. The power converter system of claim 5 wherein the mode arbiter, in response to a determination that the magnitude of oscillation falls within the predefined variance of the reference voltage, interacts with the controller to implement the fine control scheme.

7. The power converter system of claim 6 wherein the mode arbiter, in accordance with the fine control scheme, determines frequency of oscillations in the signal indicative of the output voltage during a fixed time period and computes an average duty cycle from the frequency of oscillations in the signal indicative of the output voltage.

8. The power converter system of claim 7 wherein the mode arbiter determines the frequency of oscillations by counting crossings of the reference voltage by the signal indicative of the output voltage.

9. The power converter system of claim 6 wherein the controller implements the fine coarse control scheme using an emulator configured to receive the input voltage and the output voltage, wherein the emulator generates driving currents for the plurality of delay circuits and adjusts the driving currents for one of the plurality of delay circuits in accordance with the fine control scheme.

10. The power converter system of claim 1 wherein the power converter is implemented as a buck converter.

11. A power converter system, comprising: a power converter configured to receive an input voltage and generate an output voltage that supplies a load, wherein the power converter includes an array of converter circuits coupled in parallel to each other, each converter circuit includes two power transistors electrically coupled in series between the input voltage and electrical ground; a controller is electrically coupled to each power transistor in the array of converter circuits and generates drive signals for each of the power transistors in the array of converter circuits in accordance with one of a coarse control scheme or a fine control scheme; and a mode arbiter configured to receive a signal indicative of the output voltage and determine magnitude of oscillation in the signal indicative of the output voltage, wherein the mode arbiter, in response to a determination that the magnitude of oscillation falls outside a predefined variance of the reference voltage, interacts with the controller to implement the coarse control scheme, and the mode arbiter, in response to a determination that the magnitude of oscillation falls within the predefined variance of the reference voltage, interacts with the controller to implement the fine control scheme.

12. The power converter system of claim 11 wherein the controller determines an error signal by comparing the indicator of the output voltage with a reference voltage and, during the coarse control scheme, determines the number of power transistors passing current to the load in accordance with the error signal and selectively controls conductance through the power transistors in the array of converter circuits in accordance with this determination.

13. The power converter system of claim 12 wherein the controller implements the coarse control scheme using a compensator circuit configured to receive the error signal and compute a duty cycle for the power converter in accordance with the error signal; and a plurality of delay circuits configured to receive a pulsed input signal and output the drive signals for each power transistor in the array of converter circuits, wherein each delay circuit corresponds to one of the power transistors and adjusts duty cycle of a drive signal for a corresponding power transistor in accordance with the computed duty cycle for the power converter.

14. The power converter system of claim 11 wherein the mode arbiter, in accordance with the fine control scheme, determines frequency of oscillations in the signal indicative of the output voltage during a fixed time period and computes an average duty cycle from the frequency of oscillations in the signal indicative of the output voltage.

15. The power converter system of claim 14 wherein the mode arbiter determines the frequency of oscillations by counting crossings of the reference voltage by the signal indicative of the output voltage.

16. The power converter system of claim 11 wherein the power converter is implemented as a buck converter.

17. The power converter system of claim 11 wherein the power converter is implemented as a boost converter.

18. The power converter system of claim 11 wherein each converter circuit includes an upper power transistor with a p-type channel and a lower power transistor with an n-type channel, where drain of the upper transistor is electrically coupled at a node to drain of the lower transistor.

19. The power converter system of claim 11 wherein the array of converter circuits has sixteen converter circuits coupled in parallel to each other.

20. A power converter system, comprising: a power converter configured to receive an input voltage and an output voltage and generate an output voltage that supplies a load, wherein the power converter includes an array of sixteen converter circuits coupled in parallel to each other, each converter circuit includes two power transistors electrically coupled in series between the input voltage and electrical ground; a controller is configured to receive a signal indicative of the output voltage and a reference voltage and is electrically coupled to each power transistor in the array of converter circuits, wherein the controller computes an error signal by comparing the signal indicative of the output voltage with the reference voltage, determines the number of power transistors passing current to the load in accordance with the error signal and selectively controls conductance through the power transistors in the array of converter circuits in accordance with one of a coarse control scheme or a fine control scheme; and a mode arbiter configured to receive a signal indicative of the output voltage and determine magnitude of oscillation in the signal indicative of the output voltage, wherein the mode arbiter, in response to a determination that the magnitude of oscillation falls outside a predefined variance of the reference voltage, interacts with the controller to implement the coarse control scheme, and the mode arbiter, in response to a determination that the magnitude of oscillation falls within the predefined variance of the reference voltage, interacts with the controller to implement the fine control scheme.

Description

DRAWINGS

[0012] The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure.

[0013] FIGS. 1A and 1B are graphs illustrating peak power consumption and daily energy consumption, respectively, of an implantable biomedical systems;

[0014] FIG. 2A is a graph illustrating power dissipation of a power converter consisting of a pair of power transistors with size optimal for the maximum load current as shown in FIG. 2B;

[0015] FIG. 3A is a graph illustrating power dissipation of power converter having sixteen pairs of power transistors as shown in FIG. 3B;

[0016] FIG. 4 is a graph illustrating duty cycle for a discontinuous conduction mode buck operation;

[0017] FIG. 5 is a block diagram depicting an example analog-digital hybrid control architecture;

[0018] FIGS. 6A and 6B are schematics of a buck converter and a boost converter, respectively;

[0019] FIG. 7 is a block diagram depicting the coarse digital control scheme;

[0020] FIGS. 8A and 8B is an example inductor current emulator connected to delay lines and the two V/I converters inside of the emulator, respectively;

[0021] FIGS. 9A and 9B depict the operation of the proposed coarse digital control and the corresponding waveforms, respectively;

[0022] FIGS. 10A and 10B depict a single tap circuit diagram of the variable delay DPWM and a schematic of a single delay cell, respectively;

[0023] FIG. 11 is a functional block diagram of the coarse digital control scheme;

[0024] FIGS. 12A and 12B are graphs depicting a typical waveform of limit cycle oscillations and the extracted absolute amplitude, respectively;

[0025] FIG. 13 is a schematic of an example implementation of the mode arbiter;

[0026] FIGS. 14A and 14B illustrate operation sequence and phase diagram of the mode arbiter, respectively;

[0027] FIG. 15 is a block diagram depicting the analog fine control scheme;

[0028] FIGS. 16A and 16B depict the operation of the proposed fine control and the corresponding waveforms, respectively;

[0029] FIGS. 17A and 17B depict the half circuit of the delay cell located inside the last tap of the variable delay DPWM and the variation of delay by adjusting I.sub.E;

[0030] FIG. 18 is a graph illustrating transient response for load current change;

[0031] FIG. 19 is a graph illustrating measured steady-state response of VOUT and VX;

[0032] FIG. 20 is a graph illustrating power dissipation of analog and digital block; and

[0033] FIG. 21 is a graph illustrating measured power consumption efficiency at V.sub.OUT=1 volt from V.sub.IN=3.3 volt and f.sub.SW=0.96 MHz.

[0034] Corresponding reference numerals indicate corresponding parts throughout the several views of the drawings.

DETAILED DESCRIPTION

[0035] Example embodiments will now be described more fully with reference to the accompanying drawings.

[0036] First, different types of power loss related to the loading conditions of a PWM inductive power converter, particularly in a PWM buck converter (step-down converter) are explored as well as how to minimize the dominant power loss to enhance the power conversion efficiency. For this discussion, all design parameters such as switching frequency, values of passives, and sizes of power transistors are assumed to be well-designed to minimize the total power loss of the converter. As the converter's load current varies over its full range, the relative contribution of the different types of power loss varies as well. Without loss of generality, the total power loss can be decomposed into four different categories: AC loss and DC conduction loss coming from Ohmic loss of the power transistors, overlap (OV) loss resulting from the imperfect switching timing of the NMOS and PMOS transistors, and switching (SW) loss dissipated for the charging of the gate capacitances of the power transistors. The four different losses and the total power conversion efficiency with varying load current from 30 μA to 5 mA are illustrated in FIG. 2A for a converter shown in FIG. 2B. For illustration purposes, the converter steps a 3.3V supply down to generate 1 V while operating at 1 MHz fixed switching frequency with a 6.8 μH inductor and 1.2 μF capacitor. The parasitic resistance of the passive components are assumed to be 10. As shown in FIG. 2A, while the overlap loss and AC/DC conduction loss are monotonically increased from 30 μA to 5 mA, the switching loss is independent of the change of the load currents and remains constant (˜80 μW) due to the fixed size of the power transistors. Specifically, the switching loss dominates all of the other three losses at less than 1 mA loads, which make this PWM power converter exhibit poor power conversion efficiency at the light load conditions.

[0037] In order to improve the power conversion efficiency at such light loads, therefore the switching loss should be reduced without large increase of other losses or additional loss. The switching loss of a power converter is given as

[00001]$\begin{array}{cc}{W}_{\mathrm{OPT}}\propto \frac{P_{\mathrm{OUT}}}{\sqrt{f_{\mathrm{SW}}}}=\frac{V_{\mathrm{OUT}}.Math.I_{\mathrm{OUT}}}{\sqrt{f_{\mathrm{SW}}}}& \left(2\right)\end{array}$

where P.sub.OUT and f.sub.SW are the output power and switching frequency of the given power converter, respectively. As shown in equation (2), W.sub.OPT is proportional to the load current when the operating frequency and the output voltage (V.sub.OUT) are constant. Another numerical calculation is performed using equation (2) and is illustrated in FIG. 3 where the width of the power transistors is divided amongst a fixed number of units (e.g., 16) but the other conditions except for the width remain the same as in FIG. 2. Even though the AC and DC conduction loss and overlap loss are also affected by the size of the power transistors, their increases are minimal due to the small load currents. On the other hand, as the effective gate capacitance becomes smaller the switching loss is decreased significantly, and correspondingly the overall power conversion efficiency is improved from less than 40% to over 80% even at the extreme light load conditions, 35 μA. Consequently, if one can realize the load-adaptive scaling of the power transistors scheme satisfying equation (2), that is the load-adaptive power gating while consuming small additional power (much less than the switching loss at light loads) and exhibiting low complexity, the overall power conversion efficiency will be enhanced.

[0038] Most of the recent works must have the dedicated controllers and sensors to realize load-adaptive power gating. In one example, the parasitic resistance of the inductor and active RC low pass filters are used for the estimation of the current loading condition and accommodates the finites state machine (FSM) to calculate the necessary size of the power transistor. In another example, the dedicated ADC for this purpose was implemented on chip. However, in the proposed architecture, the load-adaptive power gating is realized by reusing the existing blocks without any dedicated sensors and estimators.

[0039] With the given design parameters and light load conditions, the PWM power converter operate in discontinuous conduction mode (DCM). In DCM mode of operation, the duty cycle is calculated as follows

[00002]$\begin{array}{cc}M=\frac{2}{1+\sqrt{1+\frac{4.Math.K}{D^2}}}& \left(3\right)\end{array}$

where M, K, and D are the VCR, critical value (K=2Lf.sub.S/R and R is load), and duty cycle, respectively. Using equation (3), the required duty cycles for both of two different VCR (0.3 and 0.7, equivalent to V.sub.OUT=1 V from V.sub.IN=2.5 and 3.3 V) are shown in FIG. 4. Since the required duty is proportional to the output current (i.e., I.sub.OUT in the DCM mode), it can be used for the selection of the number of the power transistors, N. Even though this is not an optimal control following (2) precisely (the ideal case for M=0.7 is indicated by the dashed line in FIG. 4), the additional power loss from the deviation is not significant. For instance, the additional power dissipation at the 35 μA by the deviation from the ideal is calculated as about 1.2 μW which is only 5% of total power dissipation at this load condition. In addition, another advantage of this control comes from the realization of it. The selection of the number of transistor is discrete, thus a digital controller might be favorable. In this case, no digital-to-analog conversion (DAC) which is usually implemented with a power consuming ramp generator in the conventional digitally controlled converters is necessary because the selection of the power transistors itself performs the DAC function.

[0040] FIG. 5 depicts an example analog-digital hybrid control architecture 50 in the context of a PWM power converter 51. The power converter 51 is configured to receive an input voltage V.sub.IN and generate an output voltage V.sub.OUT that supplies a load. V.sub.REF, V.sub.REFH, and V.sub.REFL are the reference voltages as will be further described below. For load-adaptive scaling of the width of the power transistors, the power converter 51 includes an array of converter circuits 52 coupled in parallel to each other and each converter circuit includes at least one power transistor 53 that regulates the magnitude of the output voltage. In the example embodiment, the array of converter circuits 52 is comprised of sixteen (16) unit-sized power transistors although more or less power transistors may be used to form the array.

[0041] In one embodiment, the power converter 51 is implemented as a buck converter as seen in FIG. 6A. In another embodiment, the power converter 51 is implemented as a boost converter as seen in FIG. 6B. In either case, each converter circuit 52 is formed by a pair of power transistors: an upper transistor 53A with a p-type channel and a lower transistor 53B with an n-type channel, where drain of the upper transistor is electrically coupled at a node to drain of the lower transistor although other arrangements for the converter circuits are contemplated by this disclosure. While reference is made primarily to a buck converter throughout this disclosure, it is readily understood that the proposed control scheme is applicable to a boost converter as well as other types of power converters.

[0042] To achieve high power conversion efficiency at light loads, the sizing of the unit power transistor is one of the most important issues in the proposed converter. For the design of the unit-sized power transistors, two major design criteria were considered. First, the sum of the widths of all unit power transistors (the maximum size of the power transistors) was designed by considering the Ohmic loss (AC/DC conduction loss) to be less than half of the total power dissipation at maximum current (4 mA), and consequently the switching loss and overlap loss can occupy the other half of the total allowable power loss. The reason why this standard is set is that the portion of both conduction losses become dominant as the output current increases and reaches more than half of the total power loss as shown in FIG. 3A. Second, once the switching loss is confined into the certain value to guarantee the target power conversion efficiency (>80%) for the minimum load current, the other losses can be ignored because the other loss will be much smaller than the switching loss due to the tiny load current. However, another constant loss comes from the analog blocks should be included in this procedure. To guarantee over 80% efficiency at the lightest load condition (35 μW), the switching loss are set to be less than 5 μW considering 6.5 μW constant power consumption from the analog blocks. When a single PMOS and NMOS power transistor are selected, C.sub.TOT (total capacitance at node V.sub.X in FIG. 3B) should be less than 600 fF at f.sub.SW=1 MHz and V.sub.SW=3.3 V. The gate capacitance (C.sub.GS) and overlap capacitance (C.sub.GD) of a single PMOS and NMOS are 90 fF and 90 fF, and 0.95 fF and 1.2 fF, respectively. Thus, C.sub.TOT equals to be 550 fF. For maximum current, the power dissipation from the Ohmic loss (AC/DC conduction loss) becomes about 170 μW by the 1.15 and 0.90 on-resistance of the 120 μm and 75 μm widths of PMOS and NMOS transistors.

[0043] With continued reference to FIG. 5, a controller 55 is interfaced with each power transistor 53 in the array of converter circuits 52 and selectively controls conductance through the power transistors in the array of converter circuits 52 such that number of power transistors passing current to the load is proportional to magnitude of the load. During operation, the controller 55 has two different modes: digital (coarse) control and analog (fine) control. The controller 55 generates drive signals for the power transistors in the array of converter circuits 52 in accordance with one of a coarse control scheme or a fine control scheme as will be further described below.

[0044] In the digital control mode, overall operation is similar to a conventional digital controller. That is, the controller 55 is configured to receive an indicator of the output voltage, V.sub.OUT, and determines an error signal by comparing the indicator of the output voltage with a reference voltage V.sub.REF. The controller 55 in turn determines the number of power transistors passing current to the load in accordance with the error signal. In the example embodiment, the digital control is implemented by a variable-delay digital pulse width modulation (variable delay DPWM) 61, a digital compensator 62, an inductor current emulator 63, and an analog-to-digital converter (ADC) 64 as will be further described below. Other implementations also fall within the broader scope of this disclosure.

[0045] In the analog control mode, the overall operation is performed within the error bounds from the coarse digital control while reusing the functional blocks of the digital control. The bounded error from the coarse digital control is amplified and delivered to the variable delay DWPM for the final tuning. Since the converter has two control modes, there should be a functional block to make a decision for which mode should be used.

[0046] A mode arbiter 56 governs the control mode. The mode arbiter 56 not only governs the mode of controls but also extract the current control information of the converter based on the limit cycle oscillations (LCO) from the oversimplified digital control. On the whole, LCOs are the phenomena which should be avoided for the stable output control. The LCOs, however, are exploited for the control of the converter in the proposed architecture.

[0047] During operation, the mode arbiter 56 is configured to receive a signal indicative of the output voltage and extract information regarding the load using the oscillation in the signal indicative of the output voltage. More specifically, the mode arbiter 56 monitors the magnitude of oscillation. In response to a determination that the magnitude of oscillation falls outside the predefined variance of the reference voltage, the mode arbiter 56 interacts with the controller 55 to implement the coarse control scheme. In response to a determination that the magnitude of oscillation falls within a predefined variance of the reference voltage, the mode arbiter 56 interacts with the controller 55 to implement the fine control scheme. The arbitration scheme is described in further detail below.

[0048] FIG. 7 further illustrates the coarse digital control scheme. The error voltage between the target output (V.sub.REF) and the actual output (V.sub.OUT) is quantized by a 1b-ADC 64 and integrated through a 16b-counter 62 to control the number of delay cells in the DPWM block 61. The variable delay DPWM block 61 consists of an array of delay lines and unit-sized NMOS and PMOS drivers, which will be turned on or off based upon the output of the counter 62. The counter 62 estimates the necessary duty cycle (D) with the given load. The PMOS and NMOS driving signals are denoted as V.sub.P and V.sub.N, respectively, in FIG. 7. The variable delay DPWM 61 can adaptively perform power gating by choosing the necessary amount of unit-size transistor pairs for a specific load condition without requiring any additional control blocks. The forward and reverse delay cells, D.sub.F and D.sub.R, in the DPWM 61 are controlled by the inductor current emulator block 63 (I.sub.L emulator) where the driving current, I.sub.F and I.sub.R, are generated for the delay cells. In nominal 3.3 V input and 1 V output, D.sub.F and D.sub.R are 4.5 ns and 16.5 ns, respectively.

[0049] The I.sub.L emulator 63 performs two functions. First, it provides necessary current for the variable-delay DPWM 61 in accordance with the input supply variation from 2.5-3.3 V. As shown in FIG. 8A, the I.sub.L emulator 61 consists of two voltage-to-current (V/I) converters that generate driving currents for the variable-delay DPWM, I.sub.F and I.sub.R, using V.sub.IN−V.sub.OUT and V.sub.OUT, respectively. The schematics of the two V/I converters are also depicted in FIG. 8B. The generated I.sub.F and I.sub.R are copied and transferred to the forward and reverse delay lines in the variable-delay DPWM block. V.sub.F and V.sub.R in FIG. 8B are the nodes that connected to the forward and reverse delay cells in the variable-delay DPWM 61. Since the delays are inversely proportional to the input current (I.sub.F and I.sub.R), D.sub.F and D.sub.R will be also inversely proportional to V.sub.IN−V.sub.OUT and V.sub.OUT, respectively (I is proportional to V in the V/I converters). According to the equation (3), the necessary duty cycle (D) should increase when the input supply (V.sub.IN) decreases with the given V.sub.OUT. In the I.sub.L emulator, once V.sub.IN decreases, I.sub.F will decrease, and thus D.sub.F will also increase accordingly. D.sub.R is changed by V.sub.OUT with the similar principle with D.sub.F. This is how the coarse digital control can adapt its operation for input supply variation.

[0050] The other function that the IL emulator 63 provides is indirect zero current detection (ZCD). The ratio of D.sub.F to D.sub.R is critical in order to prevent the reverse I.sub.L generation which may occur in the DCM operation. In the DCM with synchronous design, it is mandatory to implement the ZCD function for detection and elimination of any possible generation of reverse inductor current, especially for low power operation. In the proposed architecture, the necessary condition for ZCD is satisfied simply by generating D.sub.F and D.sub.R according to equation (4). For perfect ZCD in a buck converter, equation (4) below should be met where D.sub.1 and D.sub.2 are on-times of PMOS and NMOS transistors, respectively, and L is the inductance.

[00003]$\begin{array}{cc}\frac{V_{\mathrm{OUT}}-V_{\mathrm{IN}}}{L}.Math.D_1=\frac{V_{\mathrm{OUT}}}{L}.Math.D_2& \left(4\right)\end{array}$

As shown in FIG. 8B, the driving currents, I.sub.F are I.sub.R, for the forward and reverse delays are formed through the two transconductors having V.sub.IN, V.sub.OUT, and GND as their inputs in a way that I.sub.F and I.sub.R are proportional to V.sub.IN−V.sub.OUT and V.sub.OUT, respectively. Since the delays are inversely proportional to the driving current, D.sub.F and D.sub.R are also inversely proportional to V.sub.IN−V.sub.OUT and V.sub.OUT, respectively. Consequently, the condition of equation (4) is satisfied because the total delays in forward and reverse propagation (D.sub.1 and D.sub.2) are nD.sub.F and nD.sub.R, respectively, when n is assumed to be the selected delay cells. Thus, the ZCD function can be automatically achieved. In nominal condition, where V.sub.IN=3.3 V and V.sub.OUT=1 V, the ratio of D.sub.1 to D.sub.2 is 2.3 in an ideal case. In the proposed design, this ratio is close to the ideal value, by generating adequate delays in D.sub.F and D.sub.R.

[0051] The operation of the coarse digital control is conceptually shown in FIG. 9A. If ‘n’ is assumed to be a calculated value from the counter, the clock (CLK) propagates toward the n-th tap of the forward delay (D.sub.F delay line from left to right), turning on the unit-sized PMOS power transistors sequentially. Once CLK reaches to the n-th tap, it turns off all the turned-on PMOS power transistors at once, then CLK propagates backward to the starting point. At the beginning of backward traveling, the ‘n’ number of NMOS power transistors are turned-on at once and then turned off sequentially while the clock is travelling through the D.sub.R delay line. FIG. 9B depicts the corresponding waveforms of CLK, PMOS and NMOS transistor driving signals (V.sub.P, V.sub.N), and inductor current (I.sub.L). As the rising edge of CLK arrives, each VP goes to logic ‘H’ one by one, turning on the PMOS transistors sequentially. As a result, IL increases monotonically as in FIG. 9B. Once CLK reaches to the designated tap (n-th tap), all V.sub.P signals go back to logic L, and all V.sub.N signals are switched to logic ‘H’ after a fixed dead-time (the dead time is not shown in FIG. 9). As CLK travels back, each V.sub.N goes back to logic 1′ one by one, turning off the NMOS transistors. As a result, I.sub.L decreases as CLK propagates backward. In the example embodiment, the variable-delay DPWM block consists of 16 pairs of delay cells of D.sub.F and D.sub.R and logics that do not consume static power. FIG. 10A shows the circuit implementation of a single delay tap including single forward/reverse delay cell and logics. It is noted that CLK propagation path with the dotted line assuming the tap is selected by the counter. The delay cell (shown in FIG. 10B) has a fully-differential CMOS thyristor adopted, for example from *** insert cite ***. The differential delay cell provides fast state flipping due to positive feedback from M.sub.1 and M.sub.2 when asserted by CLK signals. This guarantees robust operation as to any supply voltage variation; the delay cells are not affected by the supply variation and delays (D.sub.F and D.sub.R) are only controlled by I.sub.L emulator. The delay varies less than 5% for the nominal input voltage at 3.3 V. The transistor M3 provides the reference current (I.sub.F or I.sub.R) and the additional current can be added or subtracted at node V.sub.c to adjust the delay (also denoted as I.sub.E in FIG. 10B). At 3.3V nominal supply voltage, D.sub.F, D.sub.R, and D.sub.T are 6.5 ns, 14.5 ns, and 2 ns, respectively. The single delay cell consumes about 0.5 μW at 3.3 V with 1 MHz clock.

[0052] One of important requirements in digitally controlled power converters is that it should provide minimal oscillation in the output voltage around V.sub.REF in steady state. Those oscillations are generated by nonlinear quantization effects in ADC and/or DPWM. Generally speaking, when the resolution of DPWM is not high enough, as compared to that of the ADC, the quantized DPWM output cannot provide steady-state output. This is known as limit cycle oscillation (LCO). In the proposed scheme, LCOs come from the coarse digital control; i.e., the 1b-ADC toggles and thus gives no steady state condition. Although undesirable for steady-state operation, the LCO contains useful information for controlling the system. For example, the amplitude and frequency of LCOs can be extracted and used to tune the coefficient of the proportional-integral-derivative (PID) controller. In the proposed architecture, the average duty (D.sub.avg) is extracted from the oscillation at V.sub.OUT and used for analog fine-tuning control. The digital control block can be modeled as a 1st-order 1-bit incremental ΔΣ modulator as shown in FIG. 11, where Δ modulation is performed in the power converter itself and Σ modulation is accomplished in the digital counter (compensator). A filter block, F(n), takes outputs from the counter and gives the average (Davg). The output of F(n) provides the estimated duty necessary for control. If enough time is allowed for calculation of D.sub.avg, the resolution (N) of D.sub.avg can be given by (5) where M is the number of data points to be used for average calculation.

N=log.sub.2M  (5)

[0053] In order to calculate D.sub.avg with enough resolution (enough number of data points, M), the frequency of LCOs should be known in advance. In addition, the amplitude information of LCOs should be provided in order to capture them. Unfortunately, the analytical equation for LCOs is hard to get and presumes the assumption of sinusoidal waveforms since LCOs are usually non-sinusoids. Instead of analytical description, numerical simulations were performed to extract the characteristics of LCOs for the given design parameters such as V.sub.IN, V.sub.OUT, f.sub.SW, L, and C. FIG. 12A shows a typical waveform of LCOs, while FIG. 12B shows the extracted absolute amplitude (|A.sub.LCO|) and period (T.sub.LCO) for various load current conditions from 30 ρA to 5 mA. As shown in FIG. 12B, the amplitude and frequency of LCOs are bounded within 3˜24 mV and 25˜125 KHz, respectively, with the given load specifications. From the known T.sub.LCO, M can be set at 96-480 points for calculation of D.sub.avg. This guarantees the resolution of D.sub.avg to be at least 6.5 bit. The estimated |A.sub.LCO| can be used to distinguish the onset of LCOs from other typical transient responses of V.sub.OUT. This is important for reliable operation of the mode arbiter.

[0054] FIG. 13 depicts an example embodiment for the mode arbiter 56. The mode arbiter 56 governs the transition between the coarse digital control and the fine-tuning analog control, and provides D.sub.avg. Based on the extracted |A.sub.LCO| and T.sub.LCO, the time window is set to be up to 480 μs (typically set <200ρ), and the voltage window to observe and calculate D.sub.avg from LCOs is set to be 100 mV, respectively. These parameters may vary in other embodiments. When the output converges to the designated voltage window (V.sub.REFH−V.sub.REFL), N.sub.1-bit counter starts counting the number of zero-crossings of the output. Until the number of zero-crossings reaches a threshold, the average filter is inactive by stop command from the N.sub.1-bit counter and waits for stabilization of LCOs. After zero crossings are more than N.sub.1 times, the average filter is initiated and takes the output of the digital compensator, n, and generates D.sub.avg (N) during N.sub.2−N.sub.1 counts. FIGS. 14A and 14B conceptually illustrate the operation of the mode arbiter 56. When the output stays outside the voltage window (from A to B in FIG. 14A), the two counters are frozen. After the output converges into the window, the N.sub.1- and N.sub.2-bit counters start counting up to their values. The average filter starts calculating from C and stops at D. At D, the duty cycle is fixed into ‘N’ from the average filter and then the analog fine control is initiated. For flexibility of operation, N.sub.1 and N.sub.2 are programmable to be 2˜4 and 6˜12, respectively.

[0055] Once the mode arbiter 56 estimates D.sub.avg (N), the operation of ADC and variable delay DPWM are frozen, and the analog control is initiated for fine adjustment. FIG. 15 shows the block diagram for the analog fine-tuning control. In this mode, the finite error (V.sub.E) is amplified and converted into error current (I.sub.E) through the error amplifier (transconductor, g.sub.m). I.sub.E is added/subtracted from I.sub.F and I.sub.R, which are generated by the I.sub.L emulator, to adjust an appropriate delay in the last tap. Thus, the forward and reverse delays in the last tap are inversely proportional to I.sub.F±I.sub.E and I.sub.R±I.sub.E, respectively. The dynamic range of delays in the last tap is designed as ±1.5 D.sub.F and ±1.5 D.sub.R to fully cover the error from the coarse digital control as well as the rounding error occurred in the digital average filter. FIG. 16A shows the operation of the analog fine control. CLK propagates back and forth through ‘N’ taps in the same way as for the coarse digital control during the transient mode. FIG. 16B also illustrates the waveforms of CLK, V.sub.P, V.sub.N, and I.sub.L. The difference in operation from the coarse digital control is that only the delay of the last (N-th) tap is adjusted not only by the I.sub.L emulator 63 but also by VE. Consequently I.sub.L is changed to I.sub.L±ΔI.sub.L to compensate the error voltage of V.sub.E. FIG. 17A shows the half circuit of a delay cell (the half circuit of FIG. 10B) where D.sub.F or D.sub.R is modulated by V.sub.E. Output of the error amplifier is expressed as transconductance (g.sub.m) times V.sub.E, or g.sub.mV.sub.E. After the mode arbiter finishes its estimation of D.sub.avg, it generates V.sub.LOCK to connect the error amplifier to the last tap. Then, the delay is adjusted by I.sub.E to compensate for V.sub.E, as shown in FIG. 17B.

[0056] In an example embodiment, the proposed PWM converter was fabricated in 0.18 μm standard CMOS processes with 1P6M. The chip is implemented in a core area of 1250 μm×300 μm, or 0.375 mm2, using only 3.3V I/O transistors. The converter operates at 1 MHz frequency and the nominal V.sub.OUT is 1 V. Majority of the silicon area is occupied by the implementation of an array of power transistors and their gate drivers.

[0057] The transient response of V.sub.OUT by an abrupt output current change from 50 ρA to 4 mA is shown in FIG. 18. Once the output is out of the voltage window, the mode arbiter unlocks the analog control, which is indicated with the mode arbiter start signal (lower trace in FIG. 18). As shown in the enlarged view in FIG. 18, the LCO is initially observed. After the mode arbiter kicks in, the LCO is suppressed and there is no oscillation in steady state. In the maximum current transient, the drop of V.sub.OUT is measured as about 240 mV. FIG. 19 shows the measured waveforms of inductor voltage (V.sub.X), CLK, and V.sub.OUT when the converter is in steady state (governed by the fine analog control). The converter provides 900 μA output current from 3.3 V input supply. Again no steady state oscillation (LCO) has been observed in V.sub.OUT. The on-times of the selected PMOS and NMOS transistors are 39 and 77 ns, respectively, and the ratio of two values is about 1.97. This number deviates from the ideal value of 2.3. However, we have not observed any significant power loss by reverse I.sub.L. This is mainly because indirect ZCD is inherent in our architecture.

[0058] FIG. 20 shows the measured power dissipation for analog and digital blocks, respectively, while sweeping the output current from 35 μA to 4.1 mA. The digital block only consumes about 6 μW at the lightest load (I.sub.OUT=35 μA) which is larger than our initial estimation (˜3 μW). For comparison, 80 μW horizontal line is drawn which is equivalent to the estimated SW loss when the size of power transistors is fixed at the maximum value (W.sub.P=1.92 mm and W.sub.N=1.2 mm). By adaptively adjusting the power transistor size, we can significantly reduce analog power consumption from 80 μW to 6 μW in the lightest loads. The improvement of PCE at the lightest load is estimated as 37%. The overall PCE is also measured from 3.3V nominal supply while sweeping the full range of I.sub.OUT as shown in FIG. 21. The measured PCE is 71% at 35 μA load current, however, it recovers and reaches to over 80% at 45 μA load current. The maximum PCE of 86.3% has been measured at 1.4 mA load current.

[0059] In this disclosure, a 1 MHz PWM buck converter is presented with the load-adaptive scaling of power transistors for implantable biomedical applications. For light loads, the size of power transistors has been dynamically adjusted by digital coarse control to prevent overdrive and enhance the efficiency. The error arising from the coarse adjustment is effectively compensated by analog fine control. The proposed buck converter is able to achieve a high PCE of larger than 80% in light loads of less than 100 μA, which is critical to elongate the lifetime of battery in implantable devices. Furthermore, due to its constant switching frequency, it does not generate any unpredictable output spurs. The fabricated buck converter has shown 71% efficiency at the minimum load of 35 μA and 86.3% peak efficiency at 1.4 mA. From 45 μA to 4.1 mA load conditions, it has achieved over 80% efficiency, generating 1 V output from a 3.3 V single supply. The converter occupies 0.375 mm2 in the active area using 0.18 μm standard CMOS processes. It only requires an external capacitor of 1.2 μF and an inductor of 6.8 μH. The proposed converter is suitable for implantable biomedical systems as well as other application that consume small currents most of time while requiring high energy efficiency and robust signal integrity.

[0060] The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.