Self-oscillating resonant power converter

Abstract

Resonant power converters and inverters comprising a self-oscillating feedback loop coupled from a switch output to a control input of a switching network comprising one or more semiconductor switches (S1, S2). The self-oscillating feedback loop sets a switching frequency of the power converter (100) and comprises a first intrinsic switch capacitance (CGD) coupled between a switch output and a control input of the switching network and a first inductor (LG). The first inductor (LG) is coupled in-between a first bias voltage source and the control input of the switching network and has a substantially fixed inductance. The first bias voltage source is configured to generate an adjustable bias voltage (VBias) applied to the first inductor (LG). The output voltage (V0UT) of the power converter (100) is controlled in a flexible and rapid manner by controlling the adjustable bias voltage (VBias).

Claims

1. A resonant power converter comprising: an input terminal for receipt of an input voltage; a switching network comprising a first semiconductor switch controlled by a control input; the switching network comprising a switch input operatively coupled to the input terminal for receipt of the input voltage and a switch output operatively coupled to an input of a resonant network of the resonant power converter; the resonant network comprising a predetermined resonance frequency (fR) and an output operatively coupled to a converter output terminal; and a self-oscillating, feedback loop coupled from the switch output to a control input of the switching network to set a switching frequency of the power converter, the self-oscillating feedback loop further comprising: a first intrinsic switch capacitance coupled between the switch output and the control input of the switching network; a first bias voltage source configured to generate a first adjustable bias voltage; a first inductor with substantially fixed inductance coupled in-between the first bias voltage source and the control input of the switching network; and a voltage regulation loop configured to control an output voltage of the power converter by controlling the first adjustable bias voltage applied to the first inductor, wherein the substantially fixed inductance of the first inductor is set such that a peak voltage at the control input of the switching network exceeds a threshold voltage of the first semiconductor switch of the switching network.

2. The resonant power converter according to claim 1, further comprising: an input inductor coupled between the input terminal and the switch input and wherein the control terminal of the first semiconductor switch is coupled to the control input of the switching network and an output terminal of the first semiconductor switch is coupled to the switch input and to the switch output.

3. The resonant power converter according to claim 2, wherein the input inductor and the first inductor are magnetically coupled with a predetermined magnetic coupling coefficient.

4. The resonant power converter according to claim 1, wherein the first semiconductor switch is coupled between the switch output and a voltage supply rail of the resonant power converter and the control terminal of the first semiconductor switch is coupled to the control input of the switching network, a second semiconductor switch coupled between the switch output and the input terminal; and wherein a control terminal of the second semiconductor switch is coupled to a second bias voltage source through a cascade of a second inductor with substantially fixed inductance and a third inductor with substantially fixed inductance, and wherein a feedback capacitor is coupled between the switch output and an intermediate node between the second and third inductors.

5. The resonant power converter according to claim 4, wherein the first inductor and the third inductor are magnetically coupled with a predetermined magnetic coupling coefficient.

6. The resonant power converter according to claim 1, wherein the voltage regulation loop comprises: a reference voltage generator supplying a reference DC or AC voltage to a first input of a comparator, a second input of the comparator being coupled to the converter output voltage, an output of the of the comparator operatively coupled to a control input of the first bias voltage source.

7. The resonant power converter according to claim 1, wherein the first inductor has an inductance between 1 nH and 10 μH.

8. A resonant power converter according to claim 1, wherein the substantially fixed inductance of the first inductor is selected such that a peak-peak voltage swing at the control input of the switching network is approximately equal to a numerical value of the threshold voltage of the at least one of the semiconductor switches of the switching network.

9. The resonant power converter according to claim 1, wherein the self-oscillating feedback loop further comprises: a first series resonant circuit coupled in-between the control input of the first semiconductor switch and fixed electric potential of the converter, and a second series resonant circuit coupled in-between the control input of the first semiconductor switch and the switch output.

10. The resonant power converter according to claim 1, wherein the self-oscillating feedback loop further comprises: a parallel resonant circuit coupled in series with the first inductor in-between the first adjustable bias voltage and the first inductor.

11. The resonant power converter according to claim 1, further comprising: a rectifier coupled between the output of the resonant network and the converter output terminal to provide a rectified DC output voltage.

12. The resonant power converter according to claim 11, wherein the rectifier comprises a synchronous rectifier.

13. The resonant power converter according to claim 12, wherein the synchronous rectifier comprises: a rectification semiconductor switch configured to rectify an output voltage of the resonant network in accordance with a rectifier control input of the rectification semiconductor switch, a first rectification inductor with a substantially fixed inductance coupled in-between a fixed or adjustable rectifier bias voltage and the rectifier control input.

14. A resonant power converter according to claim 13, wherein the fixed or adjustable rectifier bias voltage is coupled to a fixed DC bias voltage source or to the rectified DC output voltage through a resistive or capacitive voltage divider.

15. A resonant power converter assembly comprising: a resonant power converter according claim 1, a carrier substrate having at least the switching network and the resonant circuit integrated thereon, an electrical trace pattern of the carrier substrate forming the first inductor.

16. The resonant power converter assembly according to claim 12, wherein the carrier substrate comprises a semiconductor die.

17. The resonant power converter according to claim 1, wherein the first inductor has an inductance between 1 nH and 50 nH.

18. A resonant power converter comprising: an input terminal for receipt of an input voltage; a switching network comprising a first semiconductor switch controlled by a control input; the switching network comprising a switch input operatively coupled to the input terminal for receipt of the input voltage and a switch output operatively coupled to an input of a resonant network of the resonant power converter; the resonant network comprising a predetermined resonance frequency (fR) and an output operatively coupled to a converter output terminal; a self-oscillating feedback loop coupled from the switch output to a control input of the switching network to set a switching frequency of the power converter, the self-oscillating feedback loop further comprising: a first intrinsic switch capacitance coupled between the switch output and the control input of the switching network; a first bias voltage source configured to generate a first adjustable bias voltage; a first inductor with substantially fixed inductance coupled in-between the first bias voltage source and the control input of the switching network; and a voltage regulation loop configured to control an output voltage of the power converter by controlling the first adjustable bias voltage applied to the first inductor, wherein the first semiconductor switch is coupled between the switch output and a voltage supply rail of the resonant power converter and a control terminal of the first semiconductor switch is coupled to the control input of the switching network; and a second semiconductor switch coupled between the switch output and the input terminal; wherein a control terminal of the second semiconductor switch is coupled to a second bias voltage source through a cascade of a second inductor with substantially fixed inductance and a third inductor with substantially fixed inductance, and wherein a feedback capacitor is coupled between the switch output and an intermediate node between the second and third inductors.

19. The resonant power converter according to claim 18, wherein the substantially fixed inductance of the first inductor is set such that a peak voltage at the control input of the switching network exceeds a threshold voltage of the first semiconductor switch of the switching network.

20. The resonant power converter according to claim 18, wherein the first inductor and the third inductor are magnetically coupled with a predetermined magnetic coupling coefficient.

21. The resonant power converter according to claim 18, wherein the voltage regulation loop comprises: a reference voltage generator supplying a reference DC or AC voltage to a first input of a comparator, a second input of the comparator being coupled to the converter output voltage, an output of the of the comparator operatively coupled to a control input of the first bias voltage source.

22. The resonant power converter according to claim 18, wherein the first inductor has an inductance between 1 nH and 10 μH.

23. The resonant power converter according to claim 18, wherein the substantially fixed inductance of the first inductor is selected such that a peak-peak voltage swing at the control input of the switching network is approximately equal to a numerical value of the threshold voltage of the at least one of the semiconductor switches of the switching network.

24. The resonant power converter according to claim 18, wherein the self-oscillating feedback loop further comprises: a first series resonant circuit coupled in-between the control input of the first semiconductor switch and fixed electric potential of the converter, and a second series resonant circuit coupled in-between the control input of the first semiconductor switch and the switch output.

25. The resonant power converter according to claim 18, wherein the self-oscillating feedback loop further comprises: a parallel resonant circuit coupled in series with the first inductor in-between the first adjustable bias voltage and the first inductor.

26. The resonant power converter according to claim 18, further comprising: a rectifier coupled between the output of the resonant network and the converter output terminal to provide a rectified DC output voltage.

27. The resonant power converter according to claim 26, wherein the rectifier comprises a synchronous rectifier.

28. The resonant power converter according to claim 27, wherein the synchronous rectifier comprises: a rectification semiconductor switch configured to rectify an output voltage of the resonant network in accordance with a rectifier control input of the rectification semiconductor switch, a first rectification inductor with a substantially fixed inductance coupled in-between a fixed or adjustable rectifier bias voltage and the rectifier control input.

29. The resonant power converter according to claim 28, wherein the fixed or adjustable rectifier bias voltage is coupled to a fixed DC bias voltage source or to the rectified DC output voltage through a resistive or capacitive voltage divider.

30. A resonant power converter assembly comprising: a resonant power converter according claim 18, a carrier substrate having at least the switching network and the resonant circuit integrated thereon, an electrical trace pattern of the carrier substrate forming the first inductor.

31. The resonant power converter assembly according to claim 30, wherein the carrier substrate comprises a semiconductor die.

32. The resonant power converter according to claim 18, wherein the first inductor has an inductance between 1 nH and 50 nH.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) A preferred embodiment of the invention will be described in more detail in connection with the appended drawings, in which:

(2) FIG. 1A) is an electrical circuit diagram of a class E resonant power converter in accordance with a first embodiment of the invention,

(3) FIG. 1B) is an electrical circuit diagram of a class E resonant power converter comprising a pair of magnetically inductors in accordance with a second embodiment of the invention,

(4) FIG. 2A) is an electrical circuit diagram of a class E resonant power converter comprising a series resonant circuit in accordance with a third embodiment of the invention,

(5) FIG. 2B) is an electrical circuit diagram of a class E resonant power converter comprising a series resonant circuit in accordance with a fourth embodiment of the invention,

(6) FIG. 2C) is an electrical circuit diagram of a gate drive circuit for class E and DE resonant power converters comprising a plurality of series resonant circuits,

(7) FIG. 2D) shows a plurality of magnitude and phase response curves of transfer functions of a MOSFET switch of the class E resonant power converter in accordance with the third embodiment of the invention,

(8) FIG. 2E) shows a plurality of control input signal waveforms of the MOSFET switch of the class E resonant power converter in accordance with the third embodiment of the invention,

(9) FIG. 3A) is an electrical circuit diagram of a class DE resonant power converter in accordance with a fifth embodiment of the invention,

(10) FIG. 3B) is an electrical circuit diagram of a class DE resonant power converter comprising a pair of magnetically coupled inductors in accordance with a sixth embodiment of the invention,

(11) FIG. 4 is an electrical circuit diagram of an exemplary DC-DC power converter based on the class E resonant power converter in accordance with the first embodiment of the invention,

(12) FIG. 5 shows a series of graphs illustrating voltage waveforms at the output of a switching network of the class E resonant power converter of the first embodiment for different bias voltage levels applied to the control input of the switching network,

(13) FIG. 6 is a circuit simulation model of a second exemplary DC-DC power converter based on the first embodiment of the class E resonant power converter,

(14) FIG. 7 shows a series of graphs illustrating various simulated voltage waveforms of the second DC-DC power converter for four different DC bias voltage levels of an adjustable bias voltage; and

(15) FIG. 8 is an electrical circuit diagram of a third DC-DC power converter with synchronous rectification on the output side based on the class E resonant power converter in accordance with the first embodiment of the invention

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(16) FIG. 1A) is a simplified electrical circuit diagram of a class E resonant power converter 100 in accordance with a first embodiment of the invention. The present class E resonant power converter is particularly well-adapted for operation in the VHF frequency range for example at switching frequencies above 10 MHz or even higher such as between 30 and 300 MHz due to, amongst other factors, low switching losses in connection with the operation of a self-oscillating feedback loop connected around a transistor switch element S.sub.1 as explained in further detail below.

(17) The class E resonant power inverter or converter 100 comprises an input pad or terminal 102 for receipt of a DC input voltage V.sub.IN from a DC power supply 104. The DC voltage level may vary considerably according to requirements of any particular conversion application such as lying between 1 V and 500 V for example between 10 V and 230 V. A switching network comprises a single switch transistor S.sub.1. The skilled person will understand that the switch transistor S.sub.1 can comprise different types of semiconductor transistors such as MOSFETs and IGBTs. The skilled person will likewise understand that the switch transistor S.sub.1 in practice can be formed by a plurality of parallel separate transistors e.g. to distribute operational currents between multiple devices. In one embodiment of the invention, S.sub.1 is formed by an IRF5802 power MOSFET available from the manufacturer International Rectifier. A gate terminal V.sub.GS of the switch transistor S.sub.1 forms a control input of the switching network allowing S.sub.1 to be switched between a conducting state or on-state with low resistance between the drain and source terminals and a non-conducting state or off-state with very large resistance between the drain and source terminals. A drain terminal V.sub.DS of the switch transistor S.sub.1 forms both a switch input and a switch output of the switching network in the present embodiment based on a single switch transistor. The drain terminal V.sub.DS is at one side coupled to the DC input voltage through an input inductor L.sub.IN (108). The drain terminal V.sub.DS is also coupled to a first side of a series resonant network comprising resonant capacitor C.sub.R and resonant inductor L.sub.R. The input inductor L.sub.IN, resonant capacitor C.sub.R, an intrinsic drain-source capacitance C.sub.DS of the MOSFET S.sub.1 and the resonant inductor L.sub.R (112) form in conjunction a resonant network of the power converter 100. A second and opposite side of the series resonant network is operatively coupled to an output terminal 114 or node of the class E resonant power converter 100 either directly as illustrated or through a suitable rectification circuit as illustrated in detail below. An inverter load is schematically indicated by a load resistor R.sub.LOAD connected to the converter at the output terminal 114 and may generally exhibit inductive, capacitive or resistive impedance. The resonant network is designed with a resonance frequency (f.sub.R) of about 50 MHz in the present implementation, but the resonance frequency may vary depending on requirements of the application in question. In practice, the respective values of the resonant capacitor C.sub.R and resonant inductor L.sub.R may be selected such that a target output power at the converter output is reached for a particular load impedance. Thereafter, the value of the input inductor L.sub.IN is selected such that a desired or target value of the predetermined resonance frequency (f.sub.R) is reached in view of the intrinsic drain-source capacitance C.sub.DS for the selected switch transistor.

(18) The present class E resonant power converter 100 comprises a self-oscillating feedback loop arranged around the transistor switch S.sub.1 such that the oscillation frequency of the loop sets the switching or operational frequency of the power converter 100 as briefly mentioned above. The self-oscillating feedback loop comprises an intrinsic gate-drain capacitance C.sub.GD of the transistor switch S.sub.1 which transmits a 180 degree phase shifted portion of the switch output signal at the drain terminal V.sub.DS back to the gate terminal of the transistor switch S.sub.1. Additional loop phase shift is introduced by the gate inductor L.sub.G which preferably comprises a substantially fixed inductance. The gate inductor L.sub.G is coupled in-between a variable bias voltage V.sub.Bias and the gate terminal of the transistor switch S.sub.1. The variable bias voltage V.sub.Bias is generated by a bias voltage generator or source with a design explained in further detail below in connection with FIG. 4. However, the adjustable bias voltage V.sub.Bias applied to the gate terminal of transistor switch S.sub.1 through the gate inductor L.sub.G provides an advantageous mechanism for controlling the converter output voltage V.sub.OUT. This mechanism exploits that the time period of the cycle time, the cycle time being the reciprocal of the oscillation frequency of the feedback loop, during which S.sub.1 remains in a non-conducting state is controlled by the previously mentioned components of the resonant network defining the resonance frequency (f.sub.R). The latter frequency controls when the voltage at the switch output at V.sub.DS reaches ground or zero volts, being the lower power supply rail of the converter in the present embodiment, and thereby allowing S.sub.1 to be turned on again without introducing switching losses to discharge the intrinsic drain-source capacitance C.sub.DS. This operation mechanism where the resonant circuit is used to discharge the intrinsic semiconductor switch capacitance until the voltage across the semiconductor switch reaches approximately zero is normally denoted zero voltage switching (ZVS) operation.

(19) Conversely, the time period of the cycle time during which S.sub.1 remains conducting, or in its on-state, can be controlled by the level of the adjustable bias voltage. This property allows a duty cycle, and hence the oscillation frequency of the self-oscillating loop, to be adjusted. This is explained in further detail in connection with FIG. 5 below. Since the switch output at V.sub.DS is coupled directly to the DC input voltage through the input inductor L.sub.IN the average voltage at the switch output V.sub.DS is forced to equal the DC input voltage. The integral of a half-period sine waveform of frequency (f.sub.R) equals the sine amplitude divided by pi times the resonance frequency (f.sub.R). Furthermore, when S.sub.1 is conducting the voltage across S.sub.1 is essentially zero such that the voltage at the switch output V.sub.DS becomes substantially zero. These circumstances lead to the following equation for a peak voltage, V.sub.DS,PEAK, across S.sub.1:

(20) $\begin{array}{cc}{V}_{\mathrm{DS},\mathrm{PEAK}}=\frac{V_{\mathrm{IN}}*\pi *f_R}{f_S};& \left(1\right)\end{array}$

(21) wherein f.sub.S=The oscillation frequency of the self-oscillation loop which equals the switching frequency of the power converter.

(22) Equation (1) reveals that a decreasing oscillation frequency leads to increasing switch output voltage V.sub.DS as illustrated below by switch output voltages V.sub.DS of FIG. 5.

(23) The voltage waveforms, duty cycle control and oscillation frequency control discussed above are illustrated on the graphs 500, 510 and 520 of FIG. 5 for three different levels of the adjustable bias voltage V.sub.Bias applied to the substantially fixed inductance gate inductor L.sub.G. The scale on the y-axis of all graphs indicates voltage in volts while the x-axis scale indicates time in steps of 10 ns such that the entire x-axis spans over about 100 ns. As mentioned above, L.sub.G is coupled to the control input or gate V.sub.GS of the transistor switch S.sub.1. In graph 500, the adjustable bias voltage V.sub.Bias has been adjusted to a level which results in a duty cycle of approximately 0.5 in the switch output voltage V.sub.DS. Waveform 501 shows the switch output voltage V.sub.DS while waveform 503 shows the corresponding gate-source voltage applied to the gate V.sub.GS of S.sub.1. It is evident that the cycle time of the switch output voltage V.sub.DS is about 10 s corresponding to an oscillation frequency of about 100 MHz.

(24) In practice, the substantially fixed inductance of the gate inductor L.sub.G may be selected such that a desired voltage amplitude of the (oscillating) gate-source voltage waveform is achieved. The voltage amplitude is preferably adjusted such that a suitable peak voltage at the gate terminal of MOSFET switch S.sub.1 is reached in view of its threshold voltage and its gate break-down voltage. This means that the peak voltage at the gate terminal should be sufficiently large to exceed the threshold voltage of the chosen semiconductor switch, e.g. V.sub.TH of MOSFET switch S.sub.1. The oscillation frequency f.sub.S of the self-oscillation loop will inherently lie close to the resonance frequency (f.sub.R) of the resonant network if the bias voltage is adjusted approximately to the threshold voltage of the MOSFET switch S.sub.1. If the adjustable bias voltage V.sub.Bias is increased above the threshold voltage, the on-period of the MOSFET switch S.sub.1 increases and leads to increase of the duty cycle of the oscillating switch output voltage waveform. This leads to a decreasing oscillation frequency or switching frequency of the power converter. The decrease of the oscillation frequency leads to an increase of the peak voltage V.sub.DS,PEAK at the switch output as explained above in connection with equation (1), and a corresponding increase of the peak voltage across the series resonant network comprising resonant capacitor C.sub.R and resonant inductor L.sub.R due to its coupling to the switch output voltage V.sub.DS. Furthermore, because the series resonant network exhibits inductive impedance, the decreasing oscillation frequency of the switch output voltage waveform leads to a decrease of the impedance of the series resonant network. The decrease of impedance leads in turn to increasing current and power through the series resonant network and through the load resistor R.sub.LOAD—in effect increasing the converter output voltage V.sub.OUT.

(25) Consequently, the converter output voltage V.sub.OUT can be controlled by appropriately controlling the adjustable bias voltage V.sub.Bias applied to the substantially fixed inductance gate inductor L.sub.G. This feature provides a highly flexible and fast way of controlling the converter output voltage V.sub.OUT compared to prior art mechanism based on adjustable inductances and/or capacitances. In particular, the range of adjustment of the adjustable bias voltage V.sub.Bias can be very wide compared to the possible regulation range of the adjustable inductances and/or capacitances.

(26) In graph 510, the adjustable bias voltage V.sub.Bias has been increased to a level which results in a duty cycle of approximately 0.7 in the switch output voltage V.sub.DS. Waveform 511 shows the switch output voltage V.sub.DS while waveform 513 shows the corresponding gate-source voltage applied to the gate V.sub.GS of S.sub.1. As illustrated, the switch output voltage V.sub.DS has increased from a peak level of approximately 30 volt for the 0.5 duty cycle condition depicted above to approximately 50 volt. It is evident that the cycle time of the switch output voltage V.sub.DS has decreased to about 18 ns corresponding to an oscillation frequency of about 55 MHz. Finally, in graph 520, the adjustable bias voltage V.sub.Bias has been further increased to a level which results in a duty cycle of approximately 0.9 in the switch output voltage V.sub.DS. Waveform 521 shows the switch output voltage V.sub.DS while waveform 523 shows the corresponding gate-source voltage applied to the gate V.sub.GS of S.sub.1. As illustrated, the switch output voltage V.sub.DS has further increased from a peak level of approximately 50 volt for the 0.7 duty cycle condition depicted above to approximately 150 volt. It is evident that the cycle time of the switch output voltage V.sub.DS has further decreased to about 50 ns corresponding to an oscillation frequency of about 20 MHz.

(27) FIG. 1B) is an electrical circuit diagram of a class E resonant power converter 100b comprising a pair of magnetically coupled inductors in accordance with a second embodiment of the invention. The skilled person will appreciate that the above discussed features, functions and components of the first embodiment of the class E resonant power converter 100 may apply to the present embodiment as well. Likewise, corresponding components in the first and second embodiments of the present class E resonant power converter have been provided with corresponding reference numerals to ease comparison. The main difference between the first and second embodiments is that the previously discussed separate and substantially uncoupled input inductor L.sub.IN and gate inductor L.sub.G have been replaced by the pair of magnetically coupled inductors L.sub.In and L.sub.G where the respective functions in the present class E resonant power converter 100b are similar to those of the first embodiment.

(28) The skilled person will appreciate that magnetic coupling between the input inductor L.sub.in and gate inductor L.sub.G may be achieved in numerous ways for example by a closely spaced arrangement of the inductors e.g. coaxially arranged. The magnetic coupling provides a number of advantages over the first embodiment such as improved phase response between the control input and switch output of the MOSFET switch S.sub.1 and larger and more constant gain. The magnetic coupling ensures that the respective inductor currents of the input inductor L.sub.in and gate inductor L.sub.G are out of phase. Consequently, the phase shift between control input of the switch S.sub.1 and the switch output is very close to 180 degrees. Furthermore, the magnetically coupled input inductor L.sub.in and gate inductor L.sub.G may be configured such that the magnetic coupling is substantially constant across a wide frequency range to provide a more constant level of the first adjustable bias voltage when the output voltage V.sub.OUT of the power converter is regulated.

(29) The magnetic coupling between the magnetically coupled input inductor L.sub.in and gate inductor L.sub.G may also be accomplished by a transformer structure as schematically indicated on FIG. 1B). The input inductor L.sub.in and gate inductor L.sub.G may for example be wound around a common magnetically permeable member or core. The latter embodiment has the advantage of a stronger coupling of magnetic fields between the input inductor L.sub.in and gate inductor L.sub.G. This forces a phase shift even closer to 180 degrees between the control input of the switch S.sub.1 (i.e. gate voltage of switch S.sub.1) and the switch output (i.e. drain voltage of the switch S.sub.1).

(30) The magnetically coupled input inductor L.sub.in and gate inductor L.sub.G may be configured to possess a magnetic coupling which is sufficient to ensure that inductor current forced in L.sub.G by L.sub.IN is sufficiently large to drive the control input of the switch S.sub.1. In this case the gate drive can also be used to drive cascode coupled transistors where the intrinsic capacitance C.sub.GD is small or non-existent.

(31) FIG. 2A) is a simplified electrical circuit diagram of a class E resonant power converter 200 in accordance with a third embodiment of the invention. The present power converter is of similar topology to the above discussed power converter based on a single switch transistor S.sub.1. The skilled person will appreciate that the above discussed features, functions and components of the first embodiment may apply to the present embodiment as well. Likewise, corresponding components in the first and second embodiments of the present class E resonant power converter have been provided with corresponding reference numerals to ease comparison. The main difference between the first and second embodiments lies in an addition of a series resonant circuit, comprising a cascade of capacitor C.sub.MR and inductor L.sub.MR, connected between the gate node or terminal V.sub.GS of switch transistor S.sub.1 and the negative supply rail e.g. ground. The function of the series resonant circuit is to introduce additional uneven frequency components, by attenuating one or more even harmonic frequency components, to the fundamental frequency component of the oscillating gate voltage waveform of the switch transistor S.sub.1. This leads to a trapezoidal waveform shape of the gate voltage of switch transistor S.sub.1 leading to faster switch turn-on and turn-off times. This is beneficial because it reduces the conduction losses, as the switch MOSFET S.sub.1 will have relatively high resistance when the gate voltage is just above the threshold voltage. FIG. 2C) shows generally applicable embodiments of a series resonant network 201 a coupled to the control input, e.g. a gate terminal, of a switch transistor or a switching network of a class E or DE resonant power converter such as the class E and DE resonant power converters depicted on FIGS. 1A)-1B), FIG. 2A), FIGS. 3A)-3B), FIG. 4 and FIG. 8. The series resonant network 201 comprises a plurality of series resonant circuits of which one or more may be included in particular design of the class E or DE resonant power converter.

(32) If a transistor switch like a MOSFET is driven by a sine wave the gate signal will be right above the threshold voltage of the MOSFET in a beginning and end of a conduction period of the MOSFET. This causes the on resistance to be very high in these periods as the MOSFET is only fully turned on when the gate signal is larger than around twice the threshold voltage. In many resonant power converters these time periods are also where the largest currents are running through the MOSFET. Hence a lot of power is dissipated in these time periods. In order to improve the turn on speed of the MOSFET, higher order harmonics can be added to the fundamental sine wave leading to a more trapezoidal gate signal as mentioned above. This can be achieved by adding one or more series resonant circuits, each preferably comprising an LC circuit, between the control input, i.e. the gate of the present MOSFET switch, and a drain or source of the MOSFET as illustrated on FIG. 2C). Here the capacitor, C.sub.GDext, is optional and may be used to increase overall gain of the gate signal as shown in FIG. 2D). In the same way capacitor, C.sub.GSext, can optionally be used to lower the gain. The first and second LC based series resonant circuits C.sub.4HI and L.sub.4HI and C.sub.2HI and L.sub.2HI, respectively, are both connected to drain of MOSSFET switch S.sub.1 and will cause higher harmonics to be in phase with the switch output voltage at the switch output, V.sub.DS. The third and fourth LC based series resonant circuits C.sub.4HO and L.sub.4HO and C.sub.2HO and L.sub.2HO, respectively, connected to the ground will cause the harmonics to be out of phase with V.sub.DS as illustrated in FIG. 2D). The magnitude response curve 250 of graph 245 of FIG. 2D) illustrates how a LC circuit with a resonance at the second harmonic of the switching frequency of the power converter causes a peak in the gain at the third harmonic and that it is in phase with the switch output V.sub.DS. It can be shown that a 3.sup.rd harmonic in phase will be desirable for a duty cycle of 25%, but for a duty cycle of 50% it would be more desirable to have the signal out of phase as this would increase the signal right after and turn on of the MOSFET and just before turn off of the MOSFET. This feature can be achieved by setting a LC series resonant circuit with resonant frequency at the 2.sup.nd harmonic to ground instead as indicated by the third and fourth series resonant circuits C.sub.4HO and L.sub.4HO and C.sub.2HO and L.sub.2HO, respectively, of FIG. 2C). By this connection, the magnitude response curve 252 of FIG. 2D) is achieved. Here a zero is seen at the 2.sup.nd harmonic of the switching frequency and again a peak at the 3.sup.rd harmonic, but this time with a phase shift of nearly 180 degrees (please refer to curve 252 of the phase graph 246). The skilled person will understand that the number of harmonics to include in a given power converter design will depend on several parameters as price, complexity, efficiency etc. Adding higher order harmonics will in general increase the performance of the power converter, but it is important to consider which harmonics to include and the magnitude of those harmonics compared to the fundamental. Graphs 247 and 248 of FIG. 2E) show the fundamental and the 3.sup.rd and 5.sup.th harmonics of the switching frequency are in and out of phase with the switch output signal for the duty cycle D set to 25% and 50%. Note that the symbol * indicates that the depicted signal is in phase with the switch output signal V.sub.DS. By comparing, the gate drive signal waveforms with the indicated ideal (rectangular) waveform shape of the same, it is clear that it is desirable to place the fundamental out of phase with the switch output signal, but for the 3.sup.rd and 5.sup.th harmonic it depends on the duty cycle and the current waveform. Exemplary gate drive waveforms that can be achieved by adding harmonics by the above-described series resonant networks are shown in the graphs 247 and 248 of FIG. 2E).

(33) FIG. 2B) is an electrical circuit diagram of a class E resonant power converter 200b comprising a series resonant circuit in accordance with a fourth embodiment of the invention. The skilled person will appreciate that the above discussed features, functions and components of the third embodiment of the class E resonant power converter 200 may apply to the present embodiment as well. Likewise, corresponding components in the third and fourth embodiments of the present class E resonant power converter have been provided with corresponding reference numerals to ease comparison. The main difference between the third and fourth embodiments is that the previously discussed a series resonant circuit, comprising the cascade of capacitor C.sub.MR and inductor L.sub.MR, connected between the gate node or terminal V.sub.GS of switch transistor S.sub.1 and ground have been replaced by another type of resonant circuit comprising the parallelly coupled capacitor C.sub.MR and inductor L.sub.MR. The parallelly coupled capacitor C.sub.MR and inductor L.sub.MR are connected between the adjustable bias voltage V.sub.Bias and the gate inductor L.sub.g. This connection with the parallelly coupled capacitor C.sub.MR and inductor L.sub.MR provides the same advantages as the series resonant circuit employed in the third embodiment, but with much smaller inductances of inductors L.sub.g and L.sub.MR leading to a significant reduction in costs and size.

(34) FIG. 3A) is a simplified electrical circuit diagram of a class DE resonant power converter or inverter 300 in accordance with a fifth embodiment of the invention. The present resonant power inverter 300 is based on a switching network which comprises a half-bridge semiconductor topology. The present DE resonant power converter 300 provides several important advantages. One of the biggest challenges when designing resonant power converters is a huge voltage stress imposed on the switch element in the single switch power converter topology described above in connection with the first, second, third and fourth embodiments of the invention. This voltage stress may reach 3-4 times the level of the DC input voltage. Using a half bridge switch topology instead limits a peak voltage across the each of the semiconductor switches S.sub.1 and S.sub.2 to a level of the input voltage. However, this requires a fast and efficient high side driver which can pose a significant advantage if an operating frequency or switching frequency above approximately 5 MHz is desired. The present generation of the first adjustable bias voltage solves this problem as it can also be used as a high side drive (V.sub.Bias1) at several tens of megahertz. The half-bridge comprises a cascade of the first semiconductor switch S.sub.1 coupled between a switch output terminal 311 and ground and a second semiconductor switch S.sub.2 coupled between the switch output terminal 311 and a DC input voltage rail supplied through power input terminal 302 from an external DC voltage source or generator 304. A coupling or mid-point node interconnecting the first and second semiconductor switches S.sub.1 and S.sub.2 form the switch output terminal 311. This switch output terminal 311 is the drain terminal of the first semiconductor switch S.sub.1. This switch output terminal or node 311 is coupled to a first side of a series resonant network comprising resonant capacitor C.sub.R and resonant inductor L.sub.R. A drain node of the transistor switch S.sub.2, coupled to the DC input voltage, comprises the switch input terminal of the present half-bridge switch. Each of semiconductor switches S.sub.1 and S.sub.2 may comprise a NMOS power transistor as illustrated by the switch symbol. Intrinsic drain-gate, gate-source and drain-source capacitances of the first NMOS transistor switch S.sub.1 are depicted as C.sub.GD2, C.sub.GS2 and C.sub.DS2 and likewise as C.sub.GD1, C.sub.GS1 and C.sub.DS1 for NMOS transistor switch S.sub.2.

(35) The resonant capacitor C.sub.R, intrinsic drain-source capacitances of switches S.sub.1 and S.sub.2, C.sub.DS1 and C.sub.DS2, respectively, and the resonant inductor L.sub.R in conjunction form a resonant network of the power converter 300. A second and opposite side of the series resonant network is coupled to an output terminal 314 or node of the power converter 300. A converter load is schematically illustrated by a load resistor R.sub.LOAD connected to the converter at the output terminal 314 and may generally exhibit inductive, capacitive or resistive impedance. The class DE resonant power inverter 300 furthermore includes a self-oscillating feedback loop arranged around the transistor switch S.sub.1 such that an oscillation frequency of the loop sets the switching or operational frequency of the power converter in a manner similar to the one discussed in detail above in connection with the first embodiment of the invention. The self-oscillating feedback loop comprises an intrinsic gate-drain capacitance C.sub.GD2 of the transistor switch S.sub.1 and a first gate inductor L.sub.G2 which preferably comprises a substantially fixed inductance as discussed above. The gate inductor L.sub.G2 is coupled in-between a variable bias voltage V.sub.Bias2 and the gate terminal V.sub.GS2 of the transistor switch S.sub.1. The variable bias voltage V.sub.Bias2 may be generated in numerous ways by a suitably configured bias voltage generator or source for example as explained in further detail below in connection with FIG. 4. In addition to the circuitry forming the self-oscillating feedback loop arranged around transistor switch S.sub.1, the current power inverter 300 comprises a second or high side adjustable bias voltage V.sub.Bias1 that is coupled to the gate terminal of the second semiconductor switch S.sub.2 through a cascade of a second substantially fixed inductance L.sub.H and a third substantially fixed inductance L.sub.G1. The inductances of the gate inductors L.sub.G2 and L.sub.G1 may be substantially identical. A feedback capacitor C.sub.G1 is coupled between the switch output node 311 and an intermediate node between the second and third substantially fixed inductances L.sub.H and L.sub.G1. The feedback capacitor C.sub.G1 serves as a bootstrap device which raises the voltage level supplied to the upper transistor switch S.sub.2 and facilitates use of a N-channel MOSFET transistor as switch device. The inductor L.sub.H serves as a high impedance signal path at the oscillation frequency allowing passage of a relatively slowly varying bias voltage component generated by the second adjustable bias voltage V.sub.Bias1, but blocking passage of a relatively high frequency voltage component supplied through the bootstrap capacitor or feedback capacitor C.sub.G1. Consequently, combining the bias voltage components from L.sub.H and C.sub.G1, the gate control voltage at the gate terminal of the second switch S.sub.2 is level shifted. In this manner, the gate control voltage is referred to the switch output node 311 instead of ground. The self-oscillation loop ensures that each of the semiconductor switches S.sub.1 and S.sub.2 is alternately switched between conducting and non-conducting states in opposite phase in a non-overlapping manner. Thereby, the switch output node 311 becomes alternatingly clamped to the DC input voltage V.sub.IN and ground through the semiconductor switches S.sub.1 and S.sub.2 at a frequency defined by the oscillation frequency of the self-oscillating loop.

(36) The duty cycle of the switch output voltage waveforms and hence the converter output voltage at V.sub.out can once again be controlled by synchronously controlling the respective bias voltages supplied by the first and second adjustable bias voltages V.sub.Bias2 and V.sub.Bias1.

(37) FIG. 3B) is an electrical circuit diagram of a class DE resonant power converter 300b comprising a pair of magnetically coupled inductors L.sub.G1 and L.sub.G2 in accordance with a sixth embodiment of the invention. The skilled person will appreciate that the above discussed features, functions and components of the first embodiment of the class DE resonant power converter 300 may apply to the present embodiment as well. Likewise, corresponding components in the fifth and sixth embodiments of the present resonant power converters have been provided with corresponding reference numerals to ease comparison. The main difference between the fifth and sixth embodiments is that the previously discussed separate and substantially uncoupled gate inductors L.sub.G1 and L.sub.G2 have been replaced by the pair of magnetically coupled inductors L.sub.G1 and L.sub.G2 where their respective functions in the present class E resonant power converter 300b are similar to those of the first embodiment. The skilled person will appreciate that magnetic coupling between the gate inductors L.sub.G1 and L.sub.G2 may be achieved in numerous ways for example by a closely spaced arrangement of the inductors e.g. coaxially arranged. The magnetic coupling provides a number of advantages over the above-described first embodiment of the class DE resonant power converter 300 such as improved phase response between the respective gate signals at the gate terminals, or control inputs, of the inductors L.sub.G1 and L.sub.G2 and larger gain. The magnetic coupling ensures that the respective inductor currents in the inductors L.sub.G1 and L.sub.G2 are out of phase. Hence, forcing a phase shift that is substantially 180 degrees between the gate signals of the inductors L.sub.G1 and L.sub.G2.

(38) The magnetic coupling between the inductors may also be accomplished by a transformer structure as schematically indicated on FIG. 3B) wherein the inductors L.sub.G1 and L.sub.G2 are wound around a common magnetically permeable core. The latter embodiment has the advantage that a larger magnetic coupling between the inductors L.sub.G1 and L.sub.G2 can be achieved and the relative phase shift of substantially 180 degrees between the respective gate signals or voltages of the MOSFET switches S.sub.1 and S.sub.2 is enforced even stronger.

(39) FIG. 4 is a schematic electrical circuit diagram of a DC-DC or switched mode power converter/supply (SMPS) 400 which is based on the class E resonant power converter or inverter 100 disclosed above in a first embodiment of the invention. The DC-DC power converter 400 comprises, in addition to the circuitry of the class E resonant power converter 100, a voltage control loop controlling the level of a DC output voltage V.sub.OUT of the DC-DC converter and a rectifier 413 schematically illustrated by a storage capacitor and a diode. The rectifier 413 preferably includes a series inductor coupled between the illustrated diode and the output voltage terminal V.sub.OUT. The skilled person will appreciate that the illustrated diode(s) based rectifier 413 may be replaced by a synchronous rectifier based on one or more actively controlled semiconductor switches rather than diodes as described in additional detail below with reference to FIG. 8. The voltage control loop regulates respective resistances of a pair of pull-up and pull-down MOSFET resistors M.sub.1 and M.sub.2 forming part of bias voltage source or generator supplying the adjustable bias voltage V.sub.Bias. The adjustable bias voltage V.sub.Bias is applied to the gate terminal of transistor switch S.sub.1 through the gate inductor L.sub.G as explained in connection with FIG. 1A) above. The voltage control loop comprises a comparator or error amplifier 414 which has a first input coupled to a DC or AC reference voltage V.sub.REF and a second input coupled to the DC output voltage V.sub.OUT of the converter. A resulting error signal V.sub.ERR reflecting whether the output voltage is lower or higher than the reference voltage is fed to an optional level converter 414. The level converter 414 is configured to provide appropriate gate control signals V.sub.C1 and V.sub.C2 for the pair of pull-up and pull-down MOSFET resistors M.sub.1 and M.sub.2 to either increase or decrease the adjustable bias voltage V.sub.Bias. The bias voltage source or generator comprises the MOSFET resistors M.sub.1 and M.sub.2 coupled between the DC input voltage and ground. Hence, the adjustable bias voltage V.sub.Bias can either be pulled towards the DC input voltage or ground depending on the adjustable on-resistances of the MOSFET resistors M.sub.1 and M.sub.2. The skilled person will appreciate that the voltage control loop can be configured in numerous ways to provide appropriate control signals to the MOSFET resistors M.sub.1 and M.sub.2 for example by proportional voltage control or by purely binary voltage control, i.e. up/down.

(40) FIG. 6 is a circuit simulation model of a second DC-DC power converter based on the first embodiment of the class E resonant power converter. The DC-DC converter comprises a rectifier coupled between an output of the series resonant circuit, including C1 and L4, and a load resistance R6 coupled to an output voltage of the converter. The rectifier comprises components C3, D, L2 and C5. Inductor and capacitor component values of the second DC-DC power converter are listed on the figure in Henry and Farad, respectively. Accordingly, the inductance of the gate inductor Lg is set to a substantially fixed value of 68 nH. The semiconductor switch is modelled by an ideal switch ISW with the listed parameters, i.e. an on-state resistance of 1.0Ω off-state resistance of 1 MΩ and threshold voltage of 4.5 V.

(41) FIG. 7 shows a series of graphs 600, 610, 620, 630 and 640 illustrating various simulated voltage waveforms of the simulation model of the second DC-DC power converter for four different fixed DC bias voltage levels of the adjustable bias voltage V.sub.bias. V.sub.bias is stepped through fixed DC voltage levels of −7.0, −2.0, 3.0 and 8.0 volt as illustrated by waveforms 607, 605, 603, 601, respectively, of graph 600 showing the DC bias voltage level. The DC input voltage V2 (Vin) is kept constant at 50 volts for all simulations.

(42) The scale on the y-axis of all graphs indicates voltage in volts while the x-axis scale indicates time in steps of 0.01 μs such that the entire x-axis spans over about 0.05 μs.

(43) Graph 610 illustrates the corresponding oscillating control input voltage waveforms 617, 615, 613, 611 at the indicated gate node (refer to FIG. 6) for the four different levels of the DC bias voltage. The higher average level of the oscillating control input voltage waveforms for the highest DC bias voltage of 8.0 V is evident. Graph 620 illustrates the corresponding switch output voltage waveforms 627, 625, 623, 621 at the switch output node i.e. at the indicated drain node (refer to FIG. 6). The longer conducting states or on-states of the switch ISW for the highest DC bias voltage of 8.0 V is evident leading to a lower oscillation frequency or switching frequency of the converter.

(44) Graph 640 illustrates the corresponding load power waveforms 627, 625, 623, 621 for the power delivered the load resistor R6 through the converter output. The gradually increasing load power from about 1.5 W at the lowest DC bias voltage of −7.0 V to about 3.5 W at the highest DC bias voltage of 8.0 V is evident. Hence, converter output power and therefore converter output voltage can be controlled by adjusting the voltage supplied by the adjustable bias voltage V.sub.bias.

(45) FIG. 8 is a schematic electrical circuit diagram of a DC-DC or switched mode power converter/supply (SMPS) 800 based on the class E resonant power converter or inverter 100 according to the first embodiment of the invention discussed above.

(46) The DC-DC power converter 800 comprises, in addition to the circuitry of the class E resonant power converter 100, a synchronous rectifier building around transistor switch S.sub.R1 and comprising additional passive components L.sub.G2 and L.sub.OUT. The skilled person will understand that the DC-DC power converter 800 may comprise an output capacitor coupled from V.sub.OUT to the negative supply rail (e.g. ground) and a voltage control loop similar to the one discussed above in connection with FIG. 4 in the fourth embodiment of the invention. The voltage control loop being configured to control the output voltage at V.sub.OUT of the power converter 800 as defined by a DC or AC reference voltage. The transistor switch element S.sub.R1 and inductors L.sub.G2 and L.sub.OUT provide a synchronous rectifier in the DC-DC power converter 800 and replaces the diode based asynchronous rectifier circuit 413 discussed above. Since the control input, e.g. the gate drive signal, of the switching network of the present class E and DE resonant power converters does not need a traditional PWM or PDM type of control signal (but only the two adjustable bias voltage V.sub.Bias1 and V.sub.Bias2), the resonant power converters in accordance with the present embodiments are generally very well suited for synchronous rectification as illustrated on FIG. 8 for this particular embodiment. The traditional PWM or PDM type of control signals are not required because is not necessary to control a phase between the respective control input signals of the first transistor switch S.sub.1 and the rectification transistor switch S.sub.R. The rectification transistor switch S.sub.R1 may for example be coupled to a suitable fixed rectifier DC bias voltage V.sub.Bias2 applied to the inductor L.sub.G2 coupled to the gate (i.e. control input) of S.sub.R1. For rectification purposes, the gate terminal of S.sub.R1 is driven by an oscillation output voltage, i.e. the drain voltage V.sub.DS, of the first semiconductor switch S.sub.1 to automatically maintain synchronous operation between S.sub.1 and SR1. This absence of the traditional PWM or PDM type of control signals on the respective gate terminals of the first transistor switch S.sub.1 and rectification transistor switch S.sub.R1 is a significant advantage leading to simplified power converter design and smaller component count. In isolated power converter applications, the present diode based asynchronous rectifier circuit 413 possess an additional advantage because it eliminates the need for transmitting or communicating the traditional PWM or PDM type control signal or signals across a voltage isolation barrier of the resonant power converter. This type of voltage isolation barrier will typically require expensive and space consuming components like optocouplers or fast transformers in traditional power converter topologies. As illustrated by FIG. 8, the present DC-DC power converter with synchronous rectification may be completely symmetrical in terms of circuit topology across a series resonant network comprising resonant capacitor C.sub.R and resonant inductor L.sub.R allowing for bidirectional power flow between the DC input power source V.sub.IN 804 and the output voltage at V.sub.OUT. The skilled person will appreciate that the input transistor switch S.sub.1 and rectifier transistor switch S.sub.R1 may be substantially identical or different components and the same applies to the fixed inductance inductors L.sub.G2 and L.sub.G1 depending on factors such as the voltage conversion ratio of the resonant power converter.

(47) The skilled person will appreciate that the above-described synchronous rectifier may be added to each of the above discussed class E and DE resonant power converter embodiments depicted above on FIG. 1B), FIGS. 2A)-2B) and FIGS. 3A)-3B).