Clock circuit portions

Abstract

A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

Claims

1. A method of producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value; wherein the method comprises: providing a first control value to the oscillator circuit portion corresponding to the target frequency according to a predetermined nominal relationship, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, wherein the first control value comprises a previously-stored control value; comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency; and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, so as to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

2. The method as claimed in claim 1, wherein comparing the output clock signal with the reference clock signal comprises counting a number of cycles of the output clock signal elapsing within a predetermined number of cycles of the reference clock signal.

3. The method as claimed in claim 1, wherein the second control value is calculated with reference to the predetermined nominal relationship between control value and frequency of the output clock signal.

4. The method as claimed in claim 1, wherein the clock circuit portion is arranged to store a plurality of operational relationships for different operating conditions.

5. The method as claimed in claim 1, further comprising: measuring at least one operating condition; recalling a corresponding operational relationship between the control value and the frequency of the output clock signal; and calculating the magnitude with which the second control value differs from the first control value with reference to the recalled operational relationship.

6. The method as claimed in claim 1, further comprising: measuring the second frequency calculating a difference between the first frequency and the second frequency; determining an operational relationship between the control value and the frequency of the output clock signal; selecting a third control value with reference to the determined operational relationship; and providing said third control value to the oscillator circuit portion so as to cause the output clock signal to produce the output clock signal with a third frequency.

7. The method as claimed in claim 6, wherein measuring the second frequency comprises counting a number of cycles of the output clock signal elapsing within a predetermined number of cycles of the reference clock signal.

8. The method as claimed in claim 6, wherein determining the operational relationship comprises comparing the difference between the first and second frequencies and the difference between the first and second control values.

9. The method as claimed in claim 6, further comprising: measuring at least one operating condition; storing the determined operational relationship between the control value and the frequency of the output clock signal with the corresponding operating condition(s).

10. The method as claimed in claim 1, comprising: measuring at least one operating condition; determining whether an operational relationship between the control value and the frequency of the output clock signal has previously been stored that corresponds to the measured operating condition(s); if an operational relationship has previously been stored that corresponds to the measured operating condition(s), recalling the corresponding operational relationship and using said relationship to determine the second control value; and if an operational relationship has not previously been stored that corresponds to the measured operating condition(s), determining an operational relationship.

11. The method as claimed in claim 1, further comprising subsequently adjusting the second control value by a fixed amount for each cycle of the reference clock when an offset is detected between the frequency of the output clock signal and the target frequency.

12. The method as claimed in claim 1, wherein the control value comprises a coarse trim value and a fine trim value.

13. The method as claimed in claim 1, wherein the target frequency is between 1 MHz and 16 MHz and the reference frequency is between 1 kHz and 100 kHz.

14. The method as claimed in claim 1, comprising storing the second control value prior to entering a sleep period or a period of open-loop operation.

15. The method as claimed in claim 14, comprising storing the second control value only if the sleep period or a period of open-loop operation has an expected duration that is less than a predetermined threshold.

16. A method of operating an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value, the method comprising: operating the oscillator circuit portion in a sleep mode or an open-loop mode; subsequently providing a first control value to the oscillator circuit portion corresponding to a target frequency according to a predetermined nominal relationship, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, wherein the first control value comprises a previously-stored control value; comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency; and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, so as to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

17. The method as claimed in claim 16, comprising operating the oscillator circuit portion in a sleep mode or an open-loop mode for a duration longer than a predetermined threshold before providing the first control value or before comparing the output clock signal with the reference clock signal.

18. A clock circuit portion configured to produce an output clock signal with a target frequency comprising: a controller configured to output a control value; an oscillator configured to receive the control value and produce an output clock signal with a frequency dependent on the control value; and a reference clock input configured to receive a reference clock signal with a reference frequency; wherein the controller is configured: to output a first control value corresponding to the target frequency according to a predetermined nominal relationship, so as to cause the oscillator to produce the output clock signal with a first frequency, wherein the first control value comprises a previously-stored control value; to compare the output clock signal with the reference clock signal to determine an offset between the first frequency and the target frequency to output a second control value that differs from the first by a magnitude calculated with reference to the determined offset so as to cause the oscillator to produce the output clock signal with a second frequency.

19. A clock generation circuit portion for producing an output clock signal with a target frequency comprising: a controller configured to output a control value; an oscillator configured to receive the control value and produce an output clock signal with a frequency dependent on the control value according to a nominal relationship; and a reference clock input for receiving a reference clock signal; wherein the clock generation circuit portion is arranged: to operate in a closed-loop mode in which the controller is arranged to output a output value corresponding to the target frequency based on the nominal relationship, to compare the output clock signal and the reference clock signal and to adjust the control value during operation to keep the output clock signal at the target frequency; and to operate in an open-loop mode in which the controller is arranged to output a fixed second control value corresponding to a second frequency based on the nominal relationship, the second frequency being lower than the target frequency.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) One or more non-limiting examples of the present disclosure will now be described with reference to the accompanying Figures, in which:

(2) FIG. 1 is a block diagram of a clock generation circuit according to one embodiment;

(3) FIG. 2 is a timing diagram illustrating operation of the clock generation circuit of FIG. 1;

(4) FIG. 3 is a graph showing the relationship between a control value and the frequency of an output clock signal of the embodiment of FIG. 1;

(5) FIG. 4 is a block diagram of a clock generation circuit according to another embodiment;

(6) FIG. 5 is a graph showing the relationship between a control value and the frequency of an output clock signal of the embodiment of FIG. 4;

(7) FIG. 6 is a block diagram of a System-on-Chip on which embodiments invention may be implemented;

(8) FIG. 7 is a block diagram of another clock generation circuit;

(9) FIG. 8 is a graph showing uncertainties in the frequency of the output clock signal from the clock generation circuit of FIG. 7 for different modes of operation; and

(10) FIG. 9 is a flow diagram illustrating operation of the clock generation circuit of FIG. 1.

DETAILED DESCRIPTION

(11) A clock generation circuit 2 comprises a digitally-controlled oscillator (DCO) 4 and a controller 6. The clock generation circuit 2 is arranged to output an output clock signal 8 that is produced by the DCO 4. The output clock signal 8 has a frequency f.sub.output that is dependent on a digital control value 10 provided by the controller 6.

(12) The digital control value 10 output by the controller 6 is determined based on an input signal 12, a reference clock signal 14 and the clock signal 8, which is fed back from the DCO 4. The reference clock signal 14 is provided by an reference clock (not shown), such as a 32.768 kHz crystal oscillator circuit, that is highly accurate but has a frequency that is many times slower than the output clock signal 8.

(13) The operation of the clock generation circuit 2 will now be explained with reference to the timing diagram shown in FIG. 2, the plot shown in FIG. 3 and the flow diagram shown in FIG. 9.

(14) In step 902, prior to an initial time t.sub.1, the clock generation circuit 2 is operated in an open-loop mode. In other examples the clock generation circuit 2 may be operated in a sleep mode before the initial time t.sub.1. At time t.sub.1, the input signal 12 identifies a target frequency f.sub.target for the output clock signal 8. The target frequency f.sub.target may be selected by a user or by software running on a separate processor (not shown).

(15) The DCO 4 is calibrated during manufacture to determine a nominal relationship 11 (e.g. a linear relationship) between the control value 10 and the frequency f.sub.output of the output clock signal 8. This nominal relationship 11 is shown with the dashed line in FIG. 3. As shown in FIG. 3, in step 904 the nominal relationship 11 is used by the controller 6 to determine a first control value N.sub.1 that should cause the DCO 4 to generate an output clock signal with the target frequency f.sub.target.

(16) However, the conditions (e.g. the ambient temperature) in which the DCO 4 is operated differ from those used when determining the nominal relationship 11. The actual (“operational”) relationship 13 between the control value 10 and the output frequency f.sub.output is shown with a dot-dashed line in FIG. 3. The frequency f.sub.output of the output clock signal 8 when the first control value N.sub.1 is input is therefore f.sub.1, where f.sub.1≠f.sub.target.

(17) In step 906, in order to determine the frequency f.sub.1, the controller 6 counts the number of cycles of the output signal 8 elapsing for two cycles of the reference clock signal 14. Once these two cycles have elapsed, at time t.sub.2, the controller 6 determines f.sub.1 and calculates an offset between f.sub.1 and the target frequency f.sub.target.

(18) Using the gradient of the (predetermined) nominal relationship 11, the controller 6 determines a magnitude N by which the first control value N.sub.1 should be changed to achieve the target frequency f.sub.target. In step 908, a second control value N.sub.2 that differs from the first control value N.sub.2 by this magnitude N is calculated and input to the DCO 4 at time t.sub.2 (or momentarily thereafter), to produce an output clock signal 8 with a second frequency f.sub.2. The change from the first control value N.sub.1 to the second control value N.sub.2 and from the first frequency f.sub.1 to the second frequency f.sub.2 is shown in FIG. 3 as a first correction 17, which has the same gradient as the nominal relationship 11. It can be seen in FIGS. 2 and 3 that the second frequency f.sub.2 is much closer to t.sub.target than f.sub.1.

(19) However, there remains a small offset between f.sub.target and f.sub.2. After allowing one cycle of the reference clock 14 for the second frequency f.sub.2 to stabilise, at t.sub.3 the controller 6 again counts the number of cycles of the output signal 8 elapsing for two cycles of the reference clock 14 to determine f.sub.2.

(20) At t.sub.4, this count is used to determine f.sub.2, and a difference f between the first and second frequencies f.sub.1, f.sub.2. The difference f is then divided by the change N between N.sub.1 and N.sub.2, to determine the gradient of the operational relationship 13 (i.e. the actual relationship between the control value 10 and the output frequency f.sub.output).

(21) Now the gradient of the operational relationship 13 is known, it can then be used to calculate a third control value N.sub.3 to bring the output frequency f.sub.output to the target frequency f.sub.target. This is input to the DCO 4 just after t.sub.4, causing the DCO 4 to output an output clock signal 8 with a frequency f.sub.3 that is very close to the target frequency f.sub.target (e.g. within a predetermined tolerance of f.sub.target). The change from the second control value N.sub.2, to the third control value N.sub.3 and from the second frequency f.sub.2 to the third frequency f.sub.3 is shown in FIG. 3 as a second correction 19, which has the same gradient as (i.e. is parallel to) the actual operational relationship 13.

(22) Thus, despite the first frequency f.sub.1 being quite different to f.sub.target at t.sub.1, the clock generation circuit 2 produces an output clock signal 8 with a frequency f.sub.3 that is acceptably close to f.sub.target within only six cycles of the reference clock signal 14 (e.g. within 200 μs for a 32.768 kHz reference clock frequency).

(23) Once the target frequency f.sub.target is achieved, the clock generation circuit 2 reverts to a “crawling mode” in which the control value 10 is shifted up or down by only one for each cycle of the reference clock signal 14 in response to detected shifts in output frequency f.sub.output (see, e.g. a measurement interval starting at t.sub.5 and a crawling step in the control value 10 at t.sub.6). Because the factors affecting the output frequency f.sub.target (e.g. ambient temperature, humidity) generally change slowly, this crawling mode is sufficient to maintain accurate operation at f.sub.target once the initial offset seen at t.sub.1 has been corrected.

(24) The clock generation circuit 2 may subsequently return to a period of open-loop operation. If the expected duration of this period of open-loop operation is less than a predetermined threshold (i.e. if the duration is short enough to render significant frequency drift unlikely), the most recently applied control value 10 may be stored to allow the target frequency to be attained quickly afterwards. If the expected duration of this period of open-loop operation is greater than the predetermined threshold, the control value 10 may simply be reset (e.g. to a default value, or to first control value N.sub.1).

(25) FIG. 4 shows another clock generation circuit 102 that comprises a digitally-controlled oscillator (DCO) 104, a controller 106, a temperature sensor 116 and a storage portion 118 (e.g. a non-volatile memory). As with the clock generation circuit 2 described with reference to FIGS. 1-3, the clock generation circuit 102 of FIG. 4 is arranged to output an output clock signal 108 that is produced by the DCO 104. The output clock signal 108 has a frequency that is dependent on a digital control value 110 provided by the controller 106. An input signal 112 to the controller 106 identifies a target frequency f.sub.target for the output clock signal 108.

(26) The operation of the clock generation circuit 102 will now be described with reference to FIG. 5, which shows a nominal relationship 111 (e.g. determined during manufacture for a nominal set of operating conditions) and an operational relationship 113 (for the actual conditions in which the clock generation circuit 102 is being used) between the control value 110 and the frequency of the output clock signal 108. As with the clock generation circuit 2 described with reference to FIGS. 1-3, the nominal relationship 111 is used by the controller 106 to determine a first control value N.sub.1 that should cause the DCO 104 to generate an output clock signal with a target frequency f.sub.target.

(27) However, due to differences between the conditions under which the nominal relationship 111 was determined and the actual conditions in which the clock generation circuit 102 is being used, the output frequency f.sub.1 for N.sub.1 is not equal to the target frequency f.sub.target. For instance, in this example the nominal relationship 111 was determined for an ambient temperature of 20° C., but the current ambient temperature is 40° C.

(28) The controller 106 counts the number of cycles of the output signal 108 elapsing for two cycles of the reference clock signal 114, to determine f.sub.1 and subsequently the offset between f.sub.1 and the target frequency f.sub.target.

(29) The controller 106 also uses the temperature sensor 116 to measure the current ambient temperature, which is 40° C. The controller 106 then consults the storage portion 118 to see if an operational relationship 113 corresponding to an ambient temperature of 40° C. is stored. In this case there is and the operational relationship 113 is recalled. The gradient of the operational relationship 113 and the offset between f.sub.1 and the target frequency f.sub.target are used to determine a magnitude N by which the first control value N.sub.1 should be changed to achieve the target frequency f.sub.target. A second control value N.sub.2, that differs from the first control value N.sub.2 by this magnitude N, is calculated and input to the DCO 104 to produce an output clock signal 108 with a second frequency f.sub.2, which is equal to f.sub.target.

(30) Because the operational relationship 113 for the current operating conditions (i.e. 40° C.) is already stored in the storage portion 118, the target frequency f.sub.target is achieved within only a few cycles of the reference clock signal 114. If there was no such operational relationship 113 already stored, the clock generation portion 102 may perform a method such as that described above with reference to FIGS. 1-3 to determine the operational relationship 113. This may then be stored to the storage portion 118 for future use. Over time, therefore, a database of operational relationships 113 may be built up for a range of operating conditions.

(31) FIG. 6 shows a System-on-Chip (SoC) 600 in which the clock generation circuit 102 is implemented. SoC 600 comprises a 32 kHz crystal oscillator 601, connected to an external crystal 603 that generates the reference clock signal 114. The SoC 600 also comprises a CPU 605.

(32) The SoC 600 also comprises a bus 607 over which the controller 106, the CPU 605, the temperature sensor 116 and the storage portion 118 communicate. The CPU 605 may provide the input signal 112 that defines the target frequency f.sub.target.

(33) FIG. 7 shows a clock generation circuit 702 comprising a digitally-controlled oscillator (DCO) 704 and a controller 706. The clock generation circuit 702 is arranged to output an output clock signal 708 that is produced by the DCO 704. The output clock signal 708 has a frequency that is dependent on a digital control value 710 provided by the controller 706.

(34) The digital control value 710 output by the controller 706 is determined based on an input signal 712. The input signal 712 identifies a target frequency f.sub.target for the output clock signal 708. The target frequency f.sub.target may be selected by a user or by software running on a separate processor (not shown).

(35) The DCO 704 is calibrated during manufacture to determine a nominal relationship (e.g. a linear relationship) between the control value 710 and the frequency of the output clock signal 708. This nominal relationship is used by the controller 706 to determine the control value 710 that should be output to cause the oscillator 704 to output an output clock signal 708 with the target frequency f.sub.target.

(36) The clock generation circuit 702 is operable in closed-loop and open-loop modes. In the closed-loop mode, the digital control value 710 output by the controller 706 is determined based on an input signal 712, a reference clock signal 714 and the clock signal 708, which is fed back from the DCO 704. The reference clock signal 714 is provided by an reference clock (not shown), such as a 32.768 kHz crystal oscillator circuit, that is highly accurate but has a frequency that is many times slower than the output clock signal 708.

(37) In the closed-loop mode, the controller 706 continually compares the fed-back clock signal 708 to the reference clock signal 714 to identify any deviation of the clock signal 708 from the target frequency f.sub.target and adjusts the control value 710 accordingly to compensate. This is referred to as locking the output clock signal 708 to the reference clock signal 714. The reference clock 714 is very accurate, i.e., the frequency of the reference lock signal 714 is always within ±2% of its nominal value. Because the output clock signal 708 is locked to the reference clock signal 714, it is also accurate to within ±2% of the target frequency f.sub.target. This accuracy is illustrated in FIG. 8, which shows the uncertainty 802 around the target frequency f.sub.target in the output clock signal 714 when in closed-loop mode. When the clock generation circuit 702 is operable in the closed-loop mode, a user can be confident that the frequency of the output signal 708 will be as accurate as the reference clock signal (in this case to ±2%).

(38) In the open-loop mode, no reference clock signal 714 is provided, and there is no feedback from the oscillator 704 to the controller 706 or continual adjustment of the control value 710. Instead, the control value 710 is simply set at the value that will produce f.sub.target according to the nominal relationship between the control value 710 and the frequency of the output clock signal 708 and remains unchanged throughout operation. This is also referred to as “free-running” mode.

(39) The inherent accuracy of the oscillator 704 is, however, much lower than that of the reference clock signal 714. When in open-loop mode, the frequency of the output clock signal 708 may vary by as much as ±5%. This is illustrated in FIG. 8, which shows the uncertainty 804 around the target frequency f.sub.target in the output clock signal 708 when in a conventional open-loop mode.

(40) FIG. 8 also shows a maximum allowable frequency f.sub.max, which, in this case, is 2% above f.sub.target. The maximum allowable frequency f.sub.max may simply be the maximum frequency the clock generation circuit 702 is specified as providing (e.g. to enable users to properly design circuitry to which the clock generation circuit 702 is connected that does not need to be over-specified which would consume additional power in normal use). For example, unillustrated circuitry connected to the clock generation circuit 702 may be unable to cope with a clock frequency exceeding f.sub.max.

(41) In closed-loop operation, the uncertainty 802 in the frequency of the output signal 708 in the closed loop mode is only ±2%, so a user can be confident that the maximum frequency f.sub.max (which is 2% above f.sub.target) will not be exceeded. However in conventional open-loop operation, the uncertainty 804 is ±5% and extends above the f.sub.max (which is at +2%). Thus a user cannot be confident that the frequency of the output clock signal 708 will remain under the maximum frequency f.sub.mas when the circuit 702 is operated in a conventional open-loop mode.

(42) The clock generation circuit 702 is therefore operable in a skewed open-loop mode. As with the conventional open-loop mode, in this mode no reference clock signal 714 is provided, and there is no feedback from the oscillator 704 to the controller 706 or continual adjustment of the control value 710. However, instead of the control value 710 being set at the value that will produce f.sub.target according to the nominal relationship, the control value 710 is set at a value that will produce an artificially down-skewed frequency f.sub.skewed, that is 3% lower than f.sub.target. This means that even with a ±5% uncertainty (shown as 806 in FIG. 7), the frequency of the output signal 708 will not exceed f.sub.max. Instead, the uncertainty 806 ranges from −8% to +2%. Even though this may lead to a frequency up to 8% lower than the target frequency, a user can be confident that even in open-loop mode the maximum frequency f.sub.max will not be exceeded.

(43) Although some particular embodiments have been described in detail, many variations and modifications are possible whilst remaining within the scope of the invention.