PIECEWISE LINEAR FUNCTION GENERATING ELECTRONIC CIRCUIT, CORRESPONDING GENERATOR, AMPLIFIER, METHOD AND COMPUTER PROGRAM PRODUCT

Abstract

A cell includes a first pair and a second pair of MOS transistors. Each of the first pair and second pair of MOS transistors have drain electrodes coupled to a respective common input node. Each of the first pair and second pair of MOS transistors includes a diode-connected MOS transistor and a latched MOS transistor. The latched MOS transistors of the first pair and second pair of MOS transistors have cross-coupled gate and drain electrodes. Source electrodes of the diode connected MOS transistors from the first pair and second pair of MOS transistors are coupled to a first current output common node to output a current to a first current collecting circuit. Source source electrodes of the latched MOS transistors of the first pair and second pair of MOS transistors are coupled to a second current output common node to output a current to a second current collecting circuit.

Claims

1. A circuit for generating a piecewise linear current transfer function, comprising: a latched circuit module cell comprising a first pair of transistors and a second pair of transistors, each of the first pair of transistors and the second pair of transistors having drain electrodes coupled to a respective common input node; wherein each of the first pair of transistors and the second pair of transistors comprises a diode-connected transistor and a latched transistor, wherein the latched transistors of the first pair of transistors and the second pair of transistors have gate and drain electrodes cross coupled; wherein source electrodes of the diode-connected transistors are coupled to a first current output common node and wherein source electrodes of the latched transistors are coupled to a second current output common node.

2. The circuit according to claim 1, wherein the latched circuit module cell is coupled to a first current collecting circuit coupled to collect a current at the first current output common node in order to implement an input current maximizing function between currents applied at the common input nodes of said latched circuit module cell.

3. The circuit according to claim 1, wherein the latched circuit module cell is coupled to a second collecting circuit coupled to collect a current as the second current output node in order to implement a current minimizing function between currents applied at the common input nodes of said latched circuit module cell.

4. The circuit according to claim 1, further comprising a first current supplying circuit configured to supply a first current to the common input node of the first pair of transistors, and a second current supplying circuit configured to supply a second current to the common input node of the second pair of transistors.

5. The circuit according to claim 4, wherein the first current is a variable current comprising a current ramp, and wherein the second current is a constant reference current.

6. The circuit according to claim 1, wherein transistors of the first pair of transistors and the second pair of transistors are NMOS transistors.

7. The circuit according to claim 1, wherein transistors of the first pair of transistors and the second pair of transistors are PMOS transistors.

8. The circuit according to claim 1, wherein the latched circuit module cell is configured to have input currents and output currents flowing in opposite direction with respect to input and output nodes.

9. The circuit according to claim 1, wherein the latched circuit module cell is configured to have input currents and output currents both entering or exiting input and output nodes.

10. The circuit according to claim 1, wherein dimensions of transistors in the first pair of transistors and the second pair of transistors are the same.

11. The circuit according to claim 1, wherein said latched circuit module cell receives an input current ramp and an input constant current corresponding to a negative offset value and further comprising: a first current collecting circuit coupled to collect a current at the first current output common node to implement an input current maximizing function between currents applied at the input nodes; a subtraction circuit configured to subtract the current constant value from the first current output; and a multiplier circuit configured to multiply by an integer in order to implement a current ramp with the negative offset generator.

12. A piecewise linear generator comprising said circuit of claim 1.

13. A class AB amplifier having a differential architecture, comprising: respective positive and negative input stages coupled to a level shifter; wherein said positive and negative input stages are coupled to a circuit according to claim 1.

14. A method for generating a piecewise linear transfer function, comprising: generating a piecewise linear current for transfer function using one or more of the circuits of claim 1.

15. The method of claim 14, comprising defining a linear piecewise current characteristic as a sequence of functions nested one into the other; configuring one circuit of claim 1 for generating a piecewise linear current transfer function implementing the innermost nested function; and configuring cascaded subsequent circuits of claim 1 for generating a piecewise linear current transfer function to perform the subsequent nested functions.

16. A computer-program product that can be loaded into the memory of at least one processor and comprises portions of software code for implementing the method according to claim 14.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Embodiments of the present disclosure will now be described with reference to the annexed drawings, which are provided purely by way of non-limiting example and in which:

[0026] FIG. 1 has already been described in the foregoing;

[0027] FIGS. 2A-2B show an embodiment of the circuit here described;

[0028] FIGS. 3A-3C show characteristic diagrams of the currents of the circuit of FIG. 2A, 2B;

[0029] FIG. 4 show an embodiment of the circuit here described;

[0030] FIGS. 5A-5C show characteristic diagrams of the currents of circuits of previous embodiments;

[0031] FIGS. 6A-6B show an embodiment of the circuit here described;

[0032] FIGS. 7A-7B show an embodiment of the circuit here described;

[0033] FIGS. 8A-8B show an embodiment of the circuit here described;

[0034] FIGS. 9A-9B show an embodiment of the circuit here described;

[0035] FIGS. 10A-10C show characteristic diagrams of the currents of the circuit of FIG. 9A, 9B;

[0036] FIGS. 11A-11B show an embodiment of the circuit here described;

[0037] FIGS. 12A-12C show characteristic diagrams of the currents of the circuit of FIG. 11A, 11B;

[0038] FIGS. 13A-13B show an embodiment of the circuit here described;

[0039] FIGS. 14A-14C show characteristic diagrams of the currents of the circuit of FIG. 13A, 13B;

[0040] FIGS. 15A-15B show an embodiment of the circuit here described;

[0041] FIGS. 16A-16B show characteristic diagrams of the currents of the circuit of FIG. 15A, 15B;

[0042] FIG. 17 shows a schematic circuit of a class AB amplifier;

[0043] FIG. 18 shows a schematic circuit of a class AB amplifier implemented by the circuits here described;

[0044] FIGS. 19A-19B show a schematic diagram of a piecewise linear function implemented by the circuits here described;

[0045] FIGS. 20A and 20B show a diagram representing details of the piecewise linear function of FIGS. 19A-19B.

DETAILED DESCRIPTION

[0046] In the following description, numerous specific details are given to provide a thorough understanding of embodiments. The embodiments can be practiced without one or several specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0047] Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0048] The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0049] Figures parts, elements or components which have already been described with reference to FIGS. 1 to 4 are denoted by the same references previously used in such figures; the description of such previously described elements will not be repeated in the following in order not to overburden the present detailed description.

[0050] FIG. 2A shows a circuit schematic of an embodiment of an electronic circuit 20 for generating a piecewise linear current transfer function, which includes a latched cell 21. Such latched cell 21 comprises a first pair of NMOS transistors M.sub.1, M.sub.2, having their drain electrodes coupled together at a respective input common node, which is indicated with V.sub.1, this reference designating for simplicity of representation also the voltage forming on such node. The embodiment of FIG. 2A represents the circuit 20 without a current collecting circuit coupled to its output. Then the latched cell 21 includes a second pair of NMOS transistors M.sub.3, M.sub.4, which is similarly coupled, the drain electrodes coupled together in a second input common node, which is indicated with V.sub.2. NMOS transistors M.sub.1 and M.sub.4 are diode-connected (i.e., their drain is coupled to their gate). NMOS transistors M.sub.2 and M.sub.3 have their respective gates coupled to the drain of the other NMOS, which are also the input nodes V.sub.1 and V.sub.2. The source electrodes of transistors M.sub.1, M.sub.2, M.sub.3, M.sub.4 in FIG. 2A are coupled together, and then to ground GND. However, this is only because for simplicity in FIG. 2A the cell 21 is not shown coupled to current collecting circuits, while the actual configuration of the source nodes is shown with reference to FIG. 2B, where a collecting circuit 50 is coupled to the latched cell 21 outputs.

[0051] Two respective current generators 22.sub.1 and 22.sub.2 are coupled between the voltage supply VDD and the input common nodes V.sub.1 and V.sub.2, respectively, for injecting a respective first input current I.sub.1 and second input current I.sub.2 entering the drain electrodes of the two pairs M.sub.1, M.sub.2 and M.sub.3, M.sub.4. Current generators 22.sub.1 and 22.sub.2 are representative of current supplying circuits, which can supply for instance constant currents or current ramps. Such current supplying circuits may be embodied also by other electronic circuits for generating a piecewise linear current transfer function supplying current at their outputs, which are coupled to the circuit 20 of FIG. 2A to supply the input current I.sub.1 and second input current I.sub.2.

[0052] Thus, NMOS transistors M.sub.1 and M.sub.4 can be defined as the diode-connected transistors of the pairs, while NMOS M.sub.2 and M.sub.3 are indicated as the latch transistors of the two pairs.

[0053] Considering thus the electronic circuit 20 of FIG. 2A when currents I.sub.1=I.sub.2, if the dimensions of the NMOS transistors M.sub.1, M.sub.2, M.sub.3, M.sub.4, are the same (i.e., such NMOS are identical, e.g., have matching MOS parameters), the first input current I.sub.1 is equally divided between the NMOS transistors M.sub.1 and M.sub.2 of the first pair and for the drain currents I.sub.D, I.sub.D1=I.sub.D2=I.sub.1/2 and I.sub.D3=I.sub.D4=I.sub.2/2.

[0054] Indicating as mentioned with V.sub.1 the voltage on the drain electrodes of the first pair, i.e., the voltage on the input node of such pair, and with V.sub.2 the voltage on the drain electrodes of the second pair, i.e., the voltage on the input node of the second pairs, in this equilibrium point, i.e., when currents I.sub.1=I.sub.2, V.sub.1=V.sub.2 so that the NMOS transistor M.sub.1, M.sub.2, M.sub.3, M.sub.4 are each in saturation zone.

[0055] It is underlined that the circuit in FIG. 2A is a schematic representation of the circuit here described, to help understand the working principle, while an embodiment of the circuit is shown in FIG. 2B. The circuit of FIG. 2A operates as a current comparator comparing the first input current I.sub.1 and the second input current I.sub.2, however to read the result of the comparison is necessary that the output currents I.sub.D1, I.sub.D2, I.sub.D3, I.sub.D4 are not merged together in a ground node, as shown in FIG. 2A. In the embodiment of FIG. 2B described here below these currents are grouped accordingly (i.e. I.sub.D6=I.sub.D1+I.sub.D4 and I.sub.D5=I.sub.D2+I.sub.D3).

[0056] In FIG. 2B it is therefore shown a circuit equivalent to that to FIG. 2A, in which to the electronic circuit 20 is coupled a circuit 50 which is just an example of a utilizer circuit, or current collecting circuit, collecting the currents coming from the first transistor pair and the second transistor pair, i.e., from the sources of the NMOS M.sub.1, M.sub.2 of the first pair and from the sources of the NMOS M.sub.3, M.sub.4 respectively, which in FIG. 2A are shown as coupled to ground. The current collecting circuit 50 simply includes a first diode connected collect NMOS transistor M.sub.5 coupled by its drain to the sources of the NMOS transistors M.sub.2, M.sub.3, through which flows a first collected current I.sub.5 from its drain to the ground where the source of the first diode connected collect NMOS transistor M.sub.5 is coupled. A second diode connected collect NMOS transistor M.sub.6 is analogously coupled to the sources of the NMOS transistors M.sub.1, M.sub.4. Indicating with V.sub.3 and V.sub.4 the voltage on the drains of transistors M.sub.5 and M.sub.6, as mentioned the circuit of FIG. 2B is equivalent to the circuit of FIG. 2A at the equilibrium, since V.sub.3=V.sub.4 and transistors M.sub.5 and M.sub.6 are just collecting the currents coming from M.sub.1-4 and M.sub.2-3.

[0057] Although the circuit of FIG. 2B shows the circuit 20 including the latched cell 21 when in use, and in particular shows the outputs of the latched cell 21, i.e. the source electrodes of the diode connected MOS transistors M.sub.1, M.sub.4 of the first pair and second pair are coupled to a respective current maximizing output common node V.sub.4 and the source electrodes of the latched MOS transistors M.sub.2, M.sub.3 of the first pair and second pair being coupled to a respective current minimizing output common node V.sub.3, given the equivalence the circuit of FIG. 2A is considered for simplicity.

[0058] Considering thus a small signal current I.sub.I.sub.d applied on input nodes V.sub.1 and V.sub.2, the input impedance Z.sub.IN of the circuit 20, i.e., cross-coupled latch, is:

Z.sub.IN.fwdarw.∞

[0059] Thus, applying a current small signal i.sub.I.sub.d the circuit reacts with an ideal output v.sub.O.sub.d:

v.sub.O.sub.d=v.sub.2−v.sub.1=Z.sub.IN.Math.i.sub.I.sub.d∞

[0060] This means that if it is applied a small current difference between the latch input nodes V.sub.1 and V.sub.2, the latch saturates the outputs conveying the first current I.sub.1 only on NMOS M.sub.1 or M.sub.2 of the first pair, and similarly happens for the second current I.sub.2.

[0061] The previously discussed equilibrium point is thus an unstable equilibrium point.

[0062] It is possible to generalize the case saying that if I.sub.1>I.sub.2 then:

I.sub.1.fwdarw.M.sub.1 and I.sub.2.fwdarw.M.sub.3

While if I.sub.1<I.sub.2 then:

I.sub.1.fwdarw.M.sub.2 and I.sub.2.fwdarw.M.sub.4

[0063] In other words, the larger current will flow always through the diode connected devices M.sub.1, M.sub.4.

[0064] Therefore, if it is collected the current flowing through the diode connected devices M.sub.1, M.sub.4 and the current flowing in the latch stage M.sub.2, M.sub.3, this corresponds to performing a mathematical operation

I.sub.6=max(I.sub.1,I.sub.2)

I.sub.5=min(I.sub.1,I.sub.2)

[0065] where I.sub.5 and I.sub.6 are the first and second output current from output nodes V.sub.3 and V.sub.4 which can flow for instance through circuit 50 of FIG. 2B. For this reason, node V.sub.4 in which flows current I.sub.6 is a current maximizing output common node, while node V.sub.3 in which flows current I.sub.5 is a current minimizing output common node V.sub.3, also used as current limiter.

[0066] Under this view, the collecting circuit 50 includes a first collecting circuit, transistor M.sub.6, coupled to collect a current I.sub.6 at the first output common node V.sub.4, in particular to implement an input current maximizing function between currents applied at the input nodes, and/or a second collecting circuit, transistor M.sub.5 coupled to collect a current I.sub.5 as the second output node V.sub.3, in particular to implement a current minimizing function between currents applied at the input nodes. Current collecting circuit 50 includes both the first and the second collecting circuit, however it is clear that only the first collecting circuit, transistor M.sub.6, or the second collecting circuit, transistor M.sub.5, may be present, if the circuit 20 is configured to implement a current maximizing function or current minimizing function only, i.e.

I.sub.6=max(I.sub.1,I.sub.2)

I.sub.5=min(I.sub.1,I.sub.2)

[0067] Also, such first and second collecting circuits can correspond to the inputs of other circuits like the electronic circuit 20 for generating a piecewise linear current transfer function.

[0068] In the same way, the electronic circuit 20 for generating a piecewise linear current transfer function may be coupled to one or more current supplying circuits configured to supply a first current, I.sub.1 to the common input node of one between the first pair M.sub.1, M.sub.2 and the second pair M.sub.3, M.sub.4 and/or a second current I.sub.2 to the common input node of the other pair. Such current supplying circuits as mentioned may be embodied by current generators, or other circuits like the electronic circuit for generating a piecewise linear current transfer function 20.

[0069] As shown in the diagrams of FIG. 3A-3C, showing the input currents I.sub.1, I.sub.2 as a function of first input current I.sub.1. Here and in the following figures, all the diagrams showing the currents are plotted as having the first input current on the abscissa. The first input current I.sub.1 is a current ramp, and the second current I.sub.2 is constant (FIG. 3A).

[0070] Diagrams 3A-3C refer to a static condition. The slope of the first input current I.sub.1 here is unity since the first input current I.sub.1 (FIG. 3A) is the quantity both in x-axis and y-axis.

[0071] Instead, in FIGS. 10A-10C and 12A-12C, described in the following, the slope can be different from the value one, since they contain input different from the first input current I.sub.1, e.g., I.sub.4. In embodiments, the circuit 20 may use a first input current I.sub.1 which is variable, for instance a current ramp, while the second input current I.sub.2 may be a constant reference current. The first output current I.sub.5 (FIG. 3B) is limited to the minimum value of input currents I.sub.1 and I.sub.2, i.e., follows first input current I.sub.1 and then when I.sub.1 exceeds I.sub.2 stays at the constant reference value of I.sub.2. Thus, on the first output current I.sub.5, the circuit 20 operates as a current limiter, i.e. performs a function which is min(I.sub.1,I.sub.2). Of course, the latched cell 21 may receive at is inputs any type of current, i.e., with any type of variation in time, performing its current maximizing or minimizing operation depending on the output which is selected.

[0072] On the other hand, the second output current I.sub.6 (FIG. 3C) follows the maximum value of the input currents I.sub.1 and I.sub.2, i.e., follows I.sub.2 and then when I.sub.1 exceeds I.sub.2 follows the increase of the first current I.sub.1. Thus, on the second output current I.sub.6, the circuit 20 operates as a current maximizer, i.e. performs a function which is max(I.sub.1,I.sub.2).

[0073] In FIG. 4 the latch cell 21 is schematized with the first input current and second input current indicated here as I.sub.IN1, I.sub.IN2, corresponding to I.sub.1 and I.sub.2 applied by the current generators in FIG. 2A, 2B, and the output currents I.sub.O1, I.sub.O2 corresponding to the current I.sub.5, I.sub.6 respectively, outputted from the two NMOS transistor pairs of the latch 21. The behavior of currents I.sub.IN1, I.sub.IN2, I.sub.O1, I.sub.O2 is shown in FIGS. 5A-5C and corresponds to that of FIGS. 3A-3C.

[0074] The latch cell 21 described before can be seen as an elementary logical block, having as input currents first input current I.sub.IN1 and second input current I.sub.IN2 and as output currents I.sub.O1, I.sub.O2 which supply the minimum or maximum of the input currents. If one of the input currents is a constant current, e.g. I.sub.IN2, the output current I.sub.O1 taken on the sources of the latched transistors implements a current limiter.

[0075] In a variant embodiment 31, shown in FIG. 6A, the latched cell or elementary logical block can have the outputs on the same side of the inputs, i.e. an elementary logic block in which both the input currents and the output currents are entering (or dually exiting) their respective input or output nodes, i.e. they have the same direction with respect to their respective input or output nodes, as opposed to the latched cell 21, where the input currents and the output current have opposite direction, i.e. input currents enter the block, output currents exit the block.

[0076] This is convenient to cascade a chain of elementary cells.

[0077] As detailed in FIG. 6B, showing the corresponding circuit, the sources of the diode connected NMOS, M.sub.1, M.sub.4 are coupled in a same node, coupled to M.sub.6, while the sources of the latch NMOS, M.sub.1, M.sub.4 are coupled in a same node, coupled to M.sub.5, on these two nodes being collected the output currents I.sub.O1 and I.sub.O2 respectively. In the case of FIG. 6B, M.sub.5 is coupled to a NMOS M.sub.8 to form a current mirror outputting the first output current I.sub.O1, while M.sub.5 is coupled to a respective NMOS M.sub.7 to form a current mirror outputting the second output current I.sub.O2. The cell 31 of FIGS. 6A-6B still behaves as described in the diagrams of FIGS. 3A-3C.

[0078] FIGS. 7A-7B and 8A-8B show the same blocks 21 and 31 implemented with PMOS transistors, instead of NMOS transistors. The structure of the latch is the same, i.e., the latch PMOS are coupled one to the other drain to gate, and the input currents I.sub.IN1, I.sub.IN2 are exiting their drains to ground or to a current generator coupled to ground, while at sources of the pairs are the output currents I.sub.O1, I.sub.O2, which flows from the PMOS digital voltage supply VSS.

[0079] FIG. 9A shows an embodiment in which two latched cells, or elementary blocks, 21a, 21b are cascaded to implement a nested function.

[0080] In this case the output of a first latch 21a, with NMOS transistors, receives input currents I.sub.IN1, I.sub.IN2. The first output current I.sub.O1 is supplied as first input current I.sub.IN3 of a second latch 21b, while the second input current of the second latch 21b is a current I.sub.IN4, collecting the output current I.sub.O4, which results:

I.sub.O4=max(I.sub.IN3,I.sub.IN4)=max(min(I.sub.IN1,I.sub.IN2),I.sub.IN4).

[0081] The behavior of the corresponding currents is shown in FIGS. 10A-10C also showing the currents as functions of the first current I.sub.IN1. In particular, FIG. 10A shows a behavior of input currents I.sub.IN1 and I.sub.IN2 corresponding to that of FIG. 5A, while also the output current I.sub.IN4 is increasing with a ramp, similarly to I.sub.IN1. The result, shown in FIG. 10C, is that current I.sub.O4 follows current I.sub.O1 till I.sub.O4 exceeds the constant value of the reference input current I.sub.IN2, then follows the value of I.sub.IN4 as dictated by the equation above, resulting in the piecewise linear characteristic of FIG. 10C.

[0082] FIG. 11A shows an embodiment in which two swapped cells, i.e. a NMOS latch 31 and a PMOS latch 31p, are used. This limits the need of large rails (V.sub.dd−V.sub.ss), V.sub.dd and V.sub.ss indicating the positive and negative supply voltage.

[0083] The output current I.sub.O1 of the PMOS latch 31p is coupled to the input I.sub.IN3 of the NMOS latch 31, to which other input I.sub.IN4 is fed a respective current.

[0084] The output 104 is:

I.sub.O4=max(I.sub.IN3,I.sub.IN4)=max(min(I.sub.IN1,I.sub.IN2),I.sub.IN4)

[0085] which is the same of the circuit of FIG. 9A, shown in the diagrams of FIGS. 10A-10C.

[0086] The output current I.sub.O4 may be the result of a comparison between a function ƒ (I.sub.IN1) and a Current Reference Ramp (CRR) I.sub.IN4=m.Math.I.sub.IN1−I.sub.Q, where m is the slope and and I.sub.Q the value of the y axis intercept, i.e. for I.sub.IN1=0. In this case I.sub.O1=I.sub.IN3=ƒ(I.sub.IN1).

[0087] These currents are shown in the diagrams of FIGS. 12A-12C. FIG. 12B shows function ƒ (I.sub.IN1) as being the current ramp (I.sub.IN1) limited to the constant value of I.sub.IN3.

[0088] To generate a Current Reference Ramp (CRR) with a negative offset, i.e., when I.sub.IN=0 I.sub.O<0, may represent a difficulty since the current flow in a latch is unidirectional.

[0089] Since this ramp must be used only for positive current comparisons, it can be generated as:

I.sub.O=m.Math.I.sub.IN−I.sub.Q for I.sub.IN>I.sub.q=I.sub.Q/m

[0090] FIG. 13A shows schematically a circuit 71 to generate a ramp with negative offset, i.e., I.sub.Q>0. Circuit 71 includes a latch cell 21 performing a max function, i.e., the output is collected on the maximizing node, to which are supplied as inputs I.sub.I1, a ramp current like the one of FIG. 5A, and I.sub.IN2=I.sub.Q, constant value current corresponding to the negative offset value, then the maximizing output, e.g. 102, is taken. In a subtraction block 41 then the current constant value I.sub.Q is subtracted from the output of the latch 21. The result is fed to a multiply by integer m block 42 producing a final output current I.sub.O=m.Math.I.sub.IN−mI.sub.q=m.Math.I.sub.IN−I.sub.Q, i.e. a ramp with negative offset.

[0091] FIG. 13B shows the corresponding circuital implementation, where the latch 31 is coupled to the circuit 60. The subtraction block 41 is embodied through current generators generating a constant current I.sub.Q which are coupled between the outputs of the latch 31 and the ground, drawing current from the output nodes of latch 31. The current I.sub.O2, i.e., the maximizing output of latch 31, is taken by the second mirror, which has a 1:m mirroring ratio, thus forming the multiplier 42.

[0092] FIG. 14A shows the diagram of the input currents I.sub.I1, I.sub.I2, the ramp I.sub.IN and the constant value I.sub.Q, and of max (I.sub.IN, I.sub.0) performed by block 21. FIG. 14B shows the diagram of the currents in input, max (I.sub.IN, I.sub.Q) and I.sub.Q, and output, max (I.sub.IN, I.sub.Q)−I.sub.Q, of the subtraction block 41, in FIG. 14C such current, max (I.sub.IN, I.sub.Q)−I.sub.Q as input of the multiplier 42 and the final output I.sub.O=m.Math.I.sub.IN−I.sub.Q, after the multiplication by m in the multiplier 42.

[0093] If it is needed to generate a Current Reference Ramp with a positive offset I.sub.O=m.Math.I.sub.IN+I.sub.Q, then it could be obtained as a circuit 81 comprising a chain of a multiplier by m 82 which output is summed in a summation block 83 to the constant offset current I.sub.Q, as shown schematically in FIG. 15A. FIG. 15B shows the circuital implementation, where the multiplier 82 is obtained by a 1:m ratio mirror circuit to which output is summed the constant offset current I.sub.Q by a current generator 83.

[0094] FIGS. 16A-16B show characteristic diagrams of the currents of the circuit of FIG. 15A, 15B, i.e., FIG. 16A shows the diagram of the input currents, the ramp I.sub.IN and the constant value I.sub.Q, while FIG. 14B shows the diagram of the final output I.sub.O=m.Math.I.sub.IN+I.sub.Q.

[0095] Thus, as shown above, the solution is in the first place directed to an electronic circuit for generating a piecewise linear current transfer function, comprising at least a circuit module, such as latch cell 21 (or 31, 21P, 31P) comprising a first pair of MOS transistor M.sub.1, M.sub.2, e.g. NMOS or PMOS, and a second pair of MOS transistor M.sub.3, M.sub.4, each of the first pair of MOS transistors M.sub.1, M.sub.2 and second pair of MOS transistor M.sub.3, M.sub.4 having their drain electrodes coupled to a respective common input node, e.g. V.sub.1, V.sub.2,

[0096] each of the first pair of MOS transistors M.sub.1, M.sub.2 and second pair of MOS transistor M.sub.3, M.sub.4 comprising a diode-connected MOS transistor, e.g., M.sub.1, M.sub.4, and a latched MOS transistor M.sub.2, M.sub.3, the latched MOS transistors M.sub.2 and M.sub.3 of the two pairs having their respective gate electrodes coupled to the drain of the other latched MOS transistor, M.sub.3 and M.sub.2 respectively,

[0097] the source electrodes of the diode connected MOS transistors M.sub.1, M.sub.4 of the first pair and second pair being coupled to a respective current first output common node I.sub.O2 and the source electrodes of the latched MOS transistors M.sub.2, M.sub.3 of the first pair and second pair being coupled to a respective second output common node I.sub.O1.

[0098] The electronic circuit may be coupled to or comprise a first collecting circuit, such as transistor M.sub.6, coupled to collect a current, e.g. I.sub.6, at the first output common node, e.g. V.sub.4, in particular to implement an input current maximizing function between currents applied at the input nodes, and/or a second collecting circuit, such as transistor M.sub.6, coupled to collect a current, e.g. I.sub.6, at the second output node, e.g. V.sub.3, in particular to implement a current minimizing function between currents applied at the input nodes.

[0099] The electronic circuit may be coupled to or comprise one or more current supplying circuits, e.g., generators 22, configured to supply a first current, e.g. I.sub.IN1, to the common input node of one between the first pair of transistors M.sub.1, M.sub.2 and the second pair of transistors, M.sub.3, M.sub.4, and/or a second current I.sub.IN2 to the common input node of the other pair.

[0100] In general, two input currents are supplied, but as shown above, also only one input current can be supplied. Then, the electronic circuit 20 may have that the first input current I.sub.IN1 is a variable current, in particular a ramp, and the second current I.sub.IN2 is a constant reference current I.sub.IN1.

[0101] Also, by combining two or more of such cells having as output max(I.sub.IN1, I.sub.IN2) and/or min(I.sub.IN1, I.sub.IN2), with the possibility of not using some inputs or some outputs (which is in this case preferably coupled to ground), it is possible to combine the output of each piecewise linear generating circuit or cell to obtain other PWL functions, as shown for instance with reference to FIGS. 9A, 9B, 11A, 11B.

[0102] To this regard, by way of example, a “triangle to quadratic” PWL generator may be obtained by using the latch blocks 21, 31, 21p, 31p described, nesting the previously discussed functions (max ( ) and min ( )) in which the arguments are a set of current reference ramps coded as two vectors containing the angular coefficient “m” and the offset coefficients “I.sub.q”, by cascading the corresponding latch cells.

[0103] As shown in FIGS. 19A-19B, a piecewise linear transfer function f(I.sub.IN) between an input current I.sub.IN and an output current I.sub.O which determines a quadratic output may be implemented. A triangular waveform current I.sub.IN is applied as input to a circuit, obtained by cascading latch cells selected among latch cells 21, 31, 21p, 31p, and selecting the required maximizing or minimizing output to couple with the next cascaded cell, implementing a symmetric transfer function f(I.sub.IN) comprising a −x.sup.2 and a +x.sup.2 parabolic branches.

[0104] As shown in FIGS. 20A and 20B due to the different concavities of the two branches of the transfer function f(I.sub.IN) the implementation of the PWL generator is divided in input in two sections I.sub.IN=[0-0.5] and I.sub.IN=[0.5-1.0] being [0-1] the amplitude of the triangular input current I.sub.I. In FIG. 20A are indicated the values of the angular coefficients m and offset coefficient I.sub.IQ of the eight ramps, four for section, forming the piecewise linear transfer function f(I.sub.IN).

[0105] As shown, a sequence of four linear segment S1, S2, S3, S4 are used, defined by pairs of coefficient m and offset current I.sub.q, which are respectively in the example shown (0.25, −0.01562), (0.5, −0.06250), (0.75, −0.14062), (1, −0.25). The value of coefficients m and offset current I.sub.q can be easily calculated with an approximation of the curve to generate in a given number of linear segments, for instance using programs like Matlab or Octave.

[0106] Then, each segment S1 . . . S4 can be generated with a respective circuit like the one in FIG. 13A (since offset currents are all negative) setting the required values of offset current I.sub.q and angular coefficient m. Then the first two segments S1 and S2 can be brought as input to a first maximizing block, obtaining max (S1,S2) which is then brought as input together with segment S3 to a second maximizing block, obtaining max (max (S1, S2), S3), which is then brought to a third maximizing block together with segment S4, obtaining max (max (max (S1, S2), S3), S4).

[0107] For the portion of curve of FIG. 20B, four linear segment S5, S6, S7, S8 are used, with pairs of coefficient m and offset current I.sub.q, which are respectively (1, −0.252), (0.75, −0.109375), (0.5, −0.00625), (0.25, −0.2625).

[0108] The current ramps corresponding to segments S5, S6, S7, S8 can be obtained on the basis of their respective m,I.sub.q coefficients by the circuit of FIG. 13A (when the offset I.sub.q is positive) or FIG. 15A (when the offset I.sub.q is negative, like for S7, S8). Then segments S5, S6, S7, S8 are brought as input to a cascade of three maximizing block, in the same way as described for segments S1, S2, S3, S4, starting with the first two segments in the sequence.

[0109] Thus, in general the method for generating a piecewise linear characteristic may include performing cascading, i.e., coupling at least an output of a latch cell to the input of a cascaded latch cell, latch cells selected between cells 21, 31, 21P, 31P configured in a configuration selected between at least current maximizer configuration, i.e. the output of the latch cell is taken on the current maximizing node, current minimizer configuration, i.e. the output of the latch cell is taken on the current minimizing node, and current reference ramp generator configuration with negative offset 71 or positive offset 81, to obtain a given a determined linear piecewise characteristic. Of course, other type of circuits different from latch cells may be inserted in the cascade.

[0110] The method of generating a linear piecewise characteristic may include therefore defining a linear piecewise current characteristic to be obtained as a sequence of functions nested one into the other. For instance, with reference to FIG. 20, the sequence of segments S1, S2, S3, S4 which reproduces the quadratic function is defined as a sequence of nested max functions where the innermost is between the first two adjacent segments, S1, S2, and the subsequent have as arguments the result of the nested function and the next segment, i.e. max (max (max (S1, S2), S3), S4).

[0111] The method includes then to configure a first circuit for generating a piecewise linear current transfer function implementing the innermost nested function, in the example a cell 21, having as inputs segments S1, S2 for instance, which maximizing output is taken. Of course, segments S1 and S2 may be current ramps generated by circuits 71 or 81.

[0112] Then, the method includes configure and cascade subsequent circuits for generating a piecewise linear current transfer function to perform the subsequent nested functions, i.e., couple at each maximizing output of a cell 21 a further cell 21 having as other input the next segment in the sequence, and taking the maximizing output of such further cell 21.

[0113] For nested function is here intended a function which is enclosed in another, called the enclosing function. In a sequence of nested functions, only the innermost functions are nested functions, while the other are also enclosing function, and the outermost is only an enclosing function.

[0114] A further application of the circuit 20 and of the latched cell 21, 31 can be in the field of class AB amplifiers.

[0115] The amplifier represents the most important block in a multitude of electronic applications.

[0116] Under this view, the parameters correlated to the power consumption of the amplifier are very relevant.

[0117] Since nowadays battery powered devices are increasingly diffused, it is important that the power must be delivered to the load with negligible losses, i.e. efficiently.

[0118] So it is important to choose an amplifier stage capable to deliver large currents to the load with negligible DC bias power consumption. These are the most important characteristic of a Class-AB amplifier where the maximum deliverable current is much higher than the DC bias current.

[0119] On the other hand, even more applications need deliver large currents at high frequency to low resistance/high capacitance loads. One example, but not limited to, could be the TV/display driver stages. Large currents and high frequency operations may lead to electromagnetic disturbances of the neighboring environment.

[0120] Due to this reason, it is even important to design very efficient architectures capable to increase the lifetime of the battery powered devices without losing sight of the amplitude these current flows (i.e. current steps).

[0121] It is possible to highlight the most important key factors that a device should meet. A possible definition of the power efficiency is that it is directly proportional to the ratio of the current delivered to the load to the bias current consumption. On the other hand the noise, which is proportional to the high frequency current Ai should be minimized.

[0122] In a Class A stage, the efficiency is very low since the maximum delivered current is a portion of the biasing available current. This kind of amplifier stages are very common when the linearity is a priority.

[0123] The natural solution that maximize the power efficiency is the Class AB amplifier stage, which is capable of deliver to the load a current that is not-related-and-larger-than the biasing current.

[0124] The main drawback of the Class AB amplifier stage is that, despite it can deliver a current to the load that is uncorrelated with the DC biasing current, the maximum amplitude of this current is not well controlled when an input voltage step is applied.

[0125] A Class AB single stage operational transconductance amplifier is represented schematically to describe such drawback.

[0126] The class AB amplifier circuit shown in FIG. 17 presents an input stage I.sub.1, consisting of an NMOS transistor M.sub.2 that acts as input terminal for a positive differential signal Vin(+) and as PMOS transdiode load M.sub.4, of an input stage I2, consisting of an NMOS transistor M.sub.1 that acts as input terminal for a negative differential signal Vin(−) and as PMOS transdiode load M.sub.4, of an input stage with a shifted level, also called “level-shifted stage input”, I3, consisting of NMOS transistors M9 and M10 and of PMOS transistors M7 and M8 in which M9 has the source electrode connected with the source electrode of M8, and M10 has the source electrode connected with the source electrode of M7. M7 and M8 have the gate connected to the drain which is coupled to ground through a respective bias current generator Ib. M.sub.1 is coupled to VDD through its drain while M.sub.2 is coupled to a first current mirror formed by PMOS M6A (diode connected, input of the mirror) and PMOS M6B, with their source coupled to VDD. The drains of M.sub.3 and of M6B are coupled respectively to the drain of a NMOS M.sub.5A (diode connected) and of a NMOS M5B forming a second mirror coupled to the ground. The common node defined by the coupled drains of M6B, M5B defines an output node to which an output capacitance C.sub.out is coupled. A current IUP flowing in the first current mirror is injected both in the drain of M.sub.2 and in the output node in condition of a large voltage step applied, as described in the following.

[0127] From FIG. 17, is possible to see that under biasing conditions, the MOS devices M.sub.7,10 and M.sub.8,9 forms a level shifter even for a small signal applied between V.sub.IN+ and V.sub.IN−. In fact, due to these MOS devices, if a small signal input V.sub.IN− is applied at the node a, it is directly seen on the node b. Since that the V.sub.IN− is applied on the gate of NMOS M.sub.4 and V.sub.IN+ is applied on the gate of M.sub.2, then the couple M.sub.2-M.sub.4 forms an equivalent transconductance:

g.sub.m_EQ=g.sub.m2//g.sub.m4

[0128] where g.sub.m2 and g.sub.m4 are respectively, the transconductance of M.sub.2 and M.sub.4.

[0129] In DC biasing condition, if Vin.sub.−=Vin.sub.+ then the devices M.sub.7-M.sub.3 form a current mirror so the bias current I.sub.B appear on drain of M.sub.3 and M.sub.1.

[0130] Considering now a large voltage step applied between V.sub.IN+ and V.sub.IN−, under this condition, the MOS devices M.sub.1 and M.sub.3 are instantaneously off while the current i.sub.UP is generated from the previously discussed g.sub.m_EQ of M.sub.2-M.sub.4. Considering for simplicity that the dimensions of first mirror PMOS M.sub.6A-6B are the same, the current i.sub.UP is directly applied on the load C.sub.OUT.

[0131] Under these assumptions, when a large voltage step is applied on the input of the amplifier 20, then a large current i.sub.UP is applied to the load and this current is uncorrelated from the biasing current I.sub.B.

[0132] Thus, a Class AB amplifier it is used an efficient way to deliver a large current to the load C.sub.OUT but doing so it is lost the possibility to control and/or limit the maximum current to the load disregarding the amplitude of input, i.e. to control the input slew rate.

[0133] The solution here described is directed to a Class AB amplifier with a controlled output slew rate.

[0134] The output current i.sub.OUT is:

i.sub.OUT=g.sub.m_EQ.Math.v.sub.IN  (1)

[0135] From equation (1), is possible to see that the maximum deliverable current is proportional to the equivalent transconductance g.sub.m_EQ and to the differential input voltage v.sub.IN.

[0136] If the target is to limit the power line drops to limit the noise injected to the other devices, the current limitation must be independent from the input voltage like happen in Class A in slewing condition.

[0137] In addition, if the accuracy of the limiting current must be high, this architecture is not well suited since it depends on the absolute accuracy of the equivalent transconductance g.sub.m_EQ and from the absolute of the maximum input voltage v.sub.IN_MAX. Either quantities are not well controlled since they depend on many factors (process, temperature, and voltages).

[0138] The solution here described introduces a slew rate limitation to an architecture where the deliverable current is intrinsically unlimited (Class AB).

[0139] FIG. 18 shows a schematic circuit of the proposed class AB amplifier, which includes inserting a current limiter on the current supplied to the load.

[0140] Such current limiter is for instance embodied by the latch 31. As shown in FIG. 18 a first latch cell 31p, of the PMOS type, has one of its current inputs I.sub.IN1 receiving the current flowing in the second current mirror M.sub.5A, M.sub.5B, in particular by a NMOS M.sub.XA coupled in parallel with respect to the NMOS M.sub.5B on the second mirror, i.e. with its gate coupled to the gates of M.sub.5A and M.sub.5B. The drain of the NMOS M.sub.XA is coupled to current inputs I.sub.IN1. The second input current I.sub.IN2 of the limiter 31 is coupled to a current generator drawing from it a maximum current I.sub.MAX. The output of the latch 31p operating a limiter, indicated by 102, is coupled to the NMOS transistor M.sub.1 that acts as input terminal for a negative differential signal Vin(−).

[0141] Symmetrically a second latch cell 31, of the NMOS type, has one of its current inputs I.sub.IN1 receiving the current flowing in the first current mirror M.sub.6A, M.sub.6B, in particular by a PMOS M.sub.XB coupled in parallel with respect to the PMOS M.sub.6B on the second mirror, i.e. with its gate coupled to the gates of M.sub.6A and M.sub.6B. The drain of the PMOS M.sub.XB is coupled to current input I.sub.IN1. The second input current I.sub.IN2 of the latch 31 is coupled to a current generator injecting in it a maximum current I.sub.MAX.

[0142] With reference to the first latch 31p, supposing to have I.sub.B<I.sub.MAX, during the DC operation, since I.sub.IN1=I.sub.B and I.sub.IN2=I.sub.MAX then I.sub.O2=I.sub.B.

[0143] If a voltage drop Δv, e.g. a decrease of the voltage of a short time length is applied on the negative input Vin.sub.− and the relative generated current on the drain of NMOS M.sub.3 is less than the maximum current I.sub.MAX, then, the current limiter, i.e. latch 31, is transparent and I.sub.O2=I.sub.IN1. While, if the voltage drop Δv has an amplitude enough to generate a current at the drain of NMOS M.sub.3 so that I.sub.D3>I.sub.MAX (FIG. 4C) then, the current limiter will limit the current so that:

I.sub.O2=I.sub.MAX  (2)

[0144] There are two different current limiters since a symmetrical output current limitation is needed.

[0145] The solution just described regarding the class AB amplifier overcomes the problem discussed. In particular:

[0146] current levels delivered to the load are larger than the biasing currents;

[0147] current limiting (slew rate) is implemented in a Class AB architecture; and

[0148] high accuracy of the limited/controlled maximum output current is obtained.

[0149] The claims are an integral part of the technical teaching of the disclosure provided herein.

[0150] Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present invention, as defined by the ensuing claims.