High-linearity variable gain amplifier and electronic apparatus

Abstract

A variable gain amplifier and an electronic apparatus. The variable gain amplifier includes a first transconductance stage circuit and a second transconductance stage circuit, where the first transconductance stage circuit includes a first amplifying circuit and a second amplifying circuit, the second transconductance stage circuit includes a third amplifying circuit and a fourth amplifying circuit, the first amplifying circuit and the fourth amplifying circuit form a differential input pair, and the second amplifying circuit and the third amplifying circuit form a differential input pair, and where each amplifying circuit of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit includes a plurality of parallel transistors, and bias control of the plurality of transistors is independent of each other.

Claims

1. A variable gain amplifier, comprising: a first transconductance stage circuit, comprising a first amplifying circuit and a second amplifying circuit; and a second transconductance stage circuit, comprising a third amplifying circuit and a fourth amplifying circuit; wherein the first amplifying circuit and the fourth amplifying circuit form a first differential input pair, and wherein the second amplifying circuit and the third amplifying circuit form a second differential input pair; and wherein each amplifying circuit of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit comprises a plurality of parallel transistors, and wherein bias control of each transistor of the plurality of parallel transistors of the respective amplifying circuit is independent of bias control of each other transistor of the respective plurality of parallel transistors.

2. The variable gain amplifier according to claim 1, wherein the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit have a same structure.

3. The variable gain amplifier according to claim 1, wherein bias currents separately output by the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit meet the following condition:
|i.sub.p2+i.sub.n1|=|i.sub.n2+i.sub.p1|=C; wherein i.sub.p1 is the bias current output by the first amplifying circuit, wherein i.sub.p2 is the bias current output by the second amplifying circuit, wherein i.sub.n1 is the bias current output by the third amplifying circuit, wherein i.sub.n2 is the bias current output by the fourth amplifying circuit, and wherein C is a constant.

4. The variable gain amplifier according to claim 3, wherein, when the variable gain amplifier performs gain switching, a bias current output by an amplifying circuit of at least one of the first differential input pair or the second differential input pair decrements, and a bias current output by the other amplifying circuit of the at least one of the first differential input pair or the second differential input pair increments.

5. The variable gain amplifier according to claim 1, further comprising: a first degeneration circuit; and a second degeneration circuit, wherein the first degeneration circuit is configured to change linearity of a bias current output by each transistor in the first transconductance stage circuit, and wherein the second degeneration circuit is configured to change linearity of a bias current output by each transistor in the second transconductance stage circuit.

6. The variable gain amplifier according to claim 5, wherein at least one of the first degeneration circuit or the second degeneration circuit comprises at least one of a resistor or an inductor.

7. The variable gain amplifier according to claim 5, wherein the plurality of transistors is a plurality of triodes.

8. The variable gain amplifier according to claim 7, wherein in each of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit, bases of the plurality of transistors are configured to separately receive an input voltage, emitters of the plurality of transistors are separately coupled to ground through at least one of the first degeneration circuit or the second degeneration circuit, and collectors of the plurality of transistors are short-circuited together and are configured to output a bias current.

9. The variable gain amplifier according to claim 5, wherein the plurality of transistors are metal-oxide semiconductor (MOS) transistors.

10. The variable gain amplifier according to claim 9, wherein in each of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit, gates of the plurality of transistors are configured to separately receive an input voltage, sources of the plurality of transistors are separately coupled to ground through at least one of the first degeneration circuit or the second degeneration circuit, and drains of the plurality of transistors are short-circuited together and are configured to output a bias current.

11. A detection apparatus, comprising: a radio frequency front-end, comprising a plurality of radio frequency channels that correspond, in a one-to-one arrangement, to a plurality of antennas, wherein radio frequency channels of the plurality of radio frequency channels are separately coupled to the plurality of antennas, wherein each radio frequency channel of the plurality of radio frequency channels comprises at least one of a radio frequency receive channel or a radio frequency transmit channel, and wherein the at least one of the radio frequency receive channel or the radio frequency transmit channel separately comprises a variable gain amplifier; and a combiner, separately coupled to the plurality of radio frequency channels; wherein the variable gain amplifier of each radio frequency channel of the plurality of radio frequency channels comprises: a first transconductance stage circuit, comprising a first amplifying circuit and a second amplifying circuit; and a second transconductance stage circuit, comprising a third amplifying circuit and a fourth amplifying circuit, wherein the first amplifying circuit and the fourth amplifying circuit form a first differential input pair, and wherein the second amplifying circuit and the third amplifying circuit form a second differential input pair; and wherein each amplifying circuit of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit comprises a plurality of parallel transistors, and wherein bias control of each transistor of the plurality of parallel transistors of the respective amplifying circuit is independent of bias control each other transistor of the plurality of parallel transistors.

12. The detection apparatus according to claim 11, wherein each radio frequency receive channel further comprises: a low-noise amplifier, wherein an input end of the low-noise amplifier is coupled to an antenna corresponding to the radio frequency receive channel, and wherein an output end of the low-noise amplifier is coupled to an input end of the variable gain amplifier; an amplifier, wherein an output end of the variable gain amplifier is coupled to an input end of the amplifier; and a phase shifter, wherein an output end of the amplifier is coupled to an input end of the phase shifter, and wherein an output end of the phase shifter is coupled to the combiner.

13. The detection apparatus according to claim 11, wherein the radio frequency transmit channel further comprises: a power amplifier, wherein an output end of the variable gain amplifier is coupled to an input end of the power amplifier, and wherein an output end of the power amplifier is coupled to an antenna corresponding to the radio frequency transmit channel; an amplifier, wherein an output end of the amplifier is coupled to an input end of the variable gain amplifier; and a phase shifter, wherein an input end of the phase shifter is coupled to the combiner, and wherein an output end of the phase shifter is coupled to an input end of the amplifier.

14. The detection apparatus according to claim 11, wherein the detection apparatus is at least one of a phased array receiver, a phased array transmitter, or a phased array transceiver.

15. A variable gain amplifier, comprising: a first amplifying circuit; a second amplifying circuit; a third amplifying circuit; and a fourth amplifying circuit; wherein the first amplifying circuit and the fourth amplifying circuit form a first differential input pair, and wherein the second amplifying circuit and the third amplifying circuit form a second differential input pair; and wherein each amplifying circuit of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit comprises a plurality of parallel transistors, and wherein bias control of each transistor of the plurality of parallel transistors of the respective amplifying circuit is independent of bias control of each other transistor of the respective plurality of parallel transistors.

16. The variable gain amplifier according to claim 15, wherein the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit have a same circuit structure.

17. The variable gain amplifier according to claim 15, wherein, when the variable gain amplifier performs gain switching, a bias current output by an amplifying circuit of at least one of the first differential input pair or the second differential input pair decrements, and a bias current output by the other amplifying circuit of the at least one of the first differential input pair or the second differential input pair increments.

18. The variable gain amplifier according to claim 15, further comprising: a first degeneration circuit; and a second degeneration circuit, wherein the first degeneration circuit is configured to change linearity of a bias current output by each transistor in the first amplifying circuit and second amplifying circuit, and wherein the second degeneration circuit is configured to change linearity of a bias current output by each transistor in the third amplifying circuit and fourth amplifying circuit.

19. The variable gain amplifier according to claim 18, wherein in each of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit, bases of the plurality of transistors are configured to separately receive an input voltage, wherein emitters of the plurality of transistors are separately coupled to ground through at least one of the first degeneration circuit or the second degeneration circuit, and wherein collectors of the plurality of transistors are short-circuited together and are configured to output a bias current.

20. The variable gain amplifier according to claim 18, wherein in each of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit, gates of the plurality of transistors are configured to separately receive an input voltage, sources of the plurality of transistors are separately coupled to ground through at least one of the first degeneration circuit or the second degeneration circuit, and drains of the plurality of transistors are short-circuited together and are configured to output a bias current.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) To describe the technical solutions in the embodiments of this application more clearly, the following briefly describes the accompanying drawings required for describing the embodiments.

(2) FIG. 1 is a schematic diagram of a structure of a current steering variable gain amplifier in the prior art;

(3) FIG. 2 is a schematic diagram of a structure of a bias-controlled variable gain amplifier in the prior art;

(4) FIG. 3a to FIG. 3c each are schematic diagrams of a structure of a variable gain amplifier according to an embodiment of this application;

(5) FIG. 4 is a schematic diagram of a structure of a differential input pair of the variable gain amplifier in FIG. 3a to FIG. 3c;

(6) FIG. 5 is a schematic diagram of a structure of another variable gain amplifier according to an embodiment of this application;

(7) FIG. 6 is a schematic diagram of a relationship between a bias current of a transistor and third-order inter-modulation power;

(8) FIG. 7 is a schematic diagram of an equivalent circuit of the variable gain amplifier shown in FIG. 3a to FIG. 3c;

(9) FIG. 8 is a schematic diagram of a linearity curve of a variable gain amplifier based on a transconductance stage circuit in the prior art;

(10) FIG. 9 is a schematic diagram of a half-side equivalent circuit of the variable gain amplifier shown in FIG. 3a to FIG. 3c;

(11) FIG. 10 is a schematic diagram of a linearity curve of a variable gain amplifier in a halved splitting manner, a quartered splitting manner, and a conventional non-splitting manner according to an embodiment of this application;

(12) FIG. 11 is a schematic diagram of a linearity curve of a variable gain amplifier in a quartered splitting manner, an unequal splitting manner, and a conventional non-splitting manner according to an embodiment of this application; and

(13) FIG. 12 is a schematic diagram of a structure of an electronic apparatus according to an embodiment of this application.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(14) To make objectives, technical solutions, and advantages of this application clearer, the following further describes this application in detail with reference to the accompanying drawings.

(15) Refer to FIG. 3a. An embodiment of this application provides a variable gain amplifier 30. Specifically, as shown in FIG. 3a, the variable gain amplifier 30 may include a first transconductance stage (Gm stage) circuit 31 and a second transconductance stage circuit 32. The first transconductance stage circuit 31 includes a first amplifying circuit Q.sub.p1 and a second amplifying circuit Q.sub.p2. The second transconductance stage circuit 32 includes a third amplifying circuit Q.sub.n1 and a fourth amplifying circuit Q.sub.n2. The first amplifying circuit Q.sub.p1 and the fourth amplifying circuit Q.sub.n2 form a differential input pair, and the second amplifying circuit Q.sub.p2 and the third amplifying circuit Q.sub.n1 form a differential input pair. Input ends of the first amplifying circuit Q.sub.p1 and the second amplifying circuit Q.sub.p2 separately receive a first voltage V.sub.rf+ through a direct-current blocking capacitor C1 and a direct-current blocking capacitor C2. The first amplifying circuit Q.sub.p1 generates a first current i.sub.p1 based on the first voltage V.sub.rf+ under control of a first bias voltage V.sub.b1. The second amplifying circuit Q.sub.p2 generates a second current i.sub.p2 based on the first voltage V.sub.rf+ under control of a second bias voltage V.sub.b2. Input ends of the third amplifying circuit Q.sub.n1 and the fourth amplifying circuit Q.sub.n2 separately receive a second voltage V.sub.rf¬ through direct-current blocking capacitors C3 and C4. The third amplifying circuit Q.sub.n1 generates a third current i.sub.n1 based on the second voltage V.sub.rf¬ under control of the first bias voltage V.sub.b1. The fourth amplifying circuit Q.sub.p2 generates a fourth current i.sub.n2 based on the second voltage V.sub.rf¬ under control of the second bias voltage V.sub.b2. The first voltage V.sub.rf+ and the second voltage V.sub.rf¬ are differential input voltages (namely, a pair of symmetric signals that are equal in magnitude but opposite in polarity). Finally, on an output stage of the variable gain amplifier 30, the first current i.sub.p1 and the fourth current i.sub.n2 are combined to form a first output current i.sub.out+, and the second current i.sub.p2 and the third current i.sub.n1 are combined to form a second output current i.sub.out−. The first output current i.sub.out+ and the second output current i.sub.out− are differential output signals. In other words, a current signal finally output by the variable gain amplifier 30 is a difference between the first output current i.sub.out+ and the second output current i.sub.out−.

(16) A person skilled in the art should know that a transconductance stage circuit may also be referred to as an operational trans-conductance amplifier (OTA), and is an amplifier that converts an input differential voltage into an output current. A gain of the transconductance stage circuits 31, 32 may be adjusted by changing magnitudes of the first bias voltage V.sub.b1 and the second bias voltage V.sub.b2, to adjust magnitude of the output current signal.

(17) In this embodiment, the first amplifying circuit Q.sub.p1, the second amplifying circuit Q.sub.p2, the third amplifying circuit Q.sub.n1, and the fourth circuit Q.sub.n2 are all symmetrically designed. In other words, structures of the first amplifying circuit Q.sub.p1, the second amplifying circuit Q.sub.p2, the third amplifying circuit Q.sub.n1, and the fourth amplifying circuit Q.sub.n2 are the same in layout and size, to maintain consistency of a dynamic gain curve (namely, a gain-control voltage/control codeword).

(18) Specifically, any one of the first amplifying circuit Q.sub.p1, the second amplifying circuit Q.sub.p2, the third amplifying circuit Q.sub.n1, and the fourth amplifying circuit Q.sub.n2 includes a plurality of parallel transistors (which may also be referred to as Gm transistors), and bias control of the plurality of transistors is independent of each other. In a conventional solution, a first amplifying circuit Q.sub.p1, a second amplifying circuit Q.sub.p2, a third amplifying circuit Q.sub.n1, or a fourth amplifying circuit Q.sub.n2 in a similar transconductance stage circuit is a transistor. However, in this embodiment, the first amplifying circuit Q.sub.p1, the second amplifying circuit Q.sub.p2, the third amplifying circuit Q.sub.n1, or the fourth amplifying circuit Q.sub.n2 is separately split into a plurality of small-sized parallel transistors. The bias voltage of each transistor is independently controlled. When a variable gain amplifier gain decreases from a maximum gain state, linearity of the variable gain amplifier is mainly determined by an amplifying circuit with a relatively small bias current in the differential input pair. When a current is small, linearity of a small-sized transistor is better than that of a large-sized transistor. Therefore, a conventional amplifying circuit in which a large-sized transistor is used is split into a plurality of small-size transistors, so that a problem of linearity deterioration that occurs when a conventional VGA gain is switched can be resolved. This improves the linearity, and further ensures that a phase of the output signal of the variable gain amplifier is kept constant.

(19) In this embodiment, a quantity of the plurality of parallel transistors in any amplifying circuit and a relative size proportion of the plurality of parallel transistors may be flexibly adjusted based on a design requirement, to improve the linearity to different degrees. This is not specifically limited in this embodiment.

(20) As shown in FIG. 3a, the variable gain amplifier 30 further includes a first degeneration circuit L1 and a second degeneration circuit L2. The first degeneration circuit L1 is configured to change linearity of the output current of each transistor in the first transconductance stage circuit 31. The second degeneration circuit L2 is configured to change linearity of the output current of each transistor in the second transconductance stage circuit 32. By improving linearity of the output signal of the entire variable gain amplifier through the two degeneration circuits, a transconductance gain of the variable gain amplifier may change linearly with the bias voltage as much as possible.

(21) In this embodiment of this application, a degeneration circuit used to improve linearity of an output current of each transistor is introduced, to improve the linearity of the output signal of the variable gain amplifier 30. This enables the transconductance gain of the variable gain amplifier 30 to change linearly with the bias voltage as much as possible.

(22) The first degeneration circuit L1 and the second degeneration circuit L2 each may include at least one of a resistor or an inductor. In other words, in this embodiment of this application, the degeneration circuit L1 or the second degeneration circuit L2 may be a separate resistor, a separate inductor, or a combination of the resistor and the inductor.

(23) For example, FIG. 3a further shows a structure of the fourth amplifying circuit Q.sub.n2. It should be noted that, for ease of description, FIG. 3a shows only a detailed structure of the fourth amplifying circuit Q.sub.n2. Because of the structures of the first amplifying circuit Q.sub.p1, the second amplifying circuit Q.sub.p2 and the third amplifying circuit Q.sub.n1 are the same as the structure of the fourth amplifying circuit Q.sub.n2. Therefore, for the structures of the first amplifying circuit Q.sub.p1, the second amplifying circuit Q.sub.p2 and the third amplifying circuit Q.sub.n1, also refer to the structure of the fourth amplifying circuit Q.sub.n2 shown in FIG. 3a. In FIG. 3a, the fourth amplifying circuit Q.sub.n2 includes a first transistor Q.sub.0 and a second transistor Q.sub.1 that are connected in parallel. Correspondingly, the second bias voltage V.sub.b2 may include a first bias voltage V.sub.b20 and a second bias voltage V.sub.b21. The first bias voltage V.sub.b20 is used to control a gain of the first transistor Q.sub.0, the second bias voltage V.sub.b21 is used to control a gain of the second transistor Q.sub.1, and bias voltages of the first transistor Q.sub.0 and the second transistor Q.sub.1 are independently controlled.

(24) It should be noted that FIG. 3a further shows bias resistors R1, R2, R3, and R4 that are separately coupled to the differential signal input ends of the amplifying circuits. By changing the first bias voltage V.sub.b1 or the second bias voltage V.sub.b2 that is applied on the bias resistors R1, R2, R3 and R4, in other words, bias control may be performed on each amplifying circuit. A person skilled in the art should know that, for example, when the fourth amplifying circuit Q.sub.n2 includes the first transistor Q.sub.0 and the second transistor Q.sub.1 that are connected in parallel, the symbol Q.sub.n2 in FIG. 3a represents an equivalent circuit corresponding to the first transistor Q.sub.0 and the second transistor Q.sub.1 that are connected in parallel. Correspondingly, symbols such as C4, V.sub.b2, and R4 separately represent the equivalent direct-current blocking capacitor, the bias voltage, and the bias resistor in the fourth amplifying circuit Q.sub.n2. In actual application, the direct-current blocking capacitor and the bias resistor are separately disposed at the differential signal input ends of the first transistor Q.sub.0 and the second transistor Q.sub.1. The bias voltage V.sub.b20 is applied on a bias resistor corresponding to the first transistor Q.sub.0, a bias current output by the first transistor Q.sub.0 may be changed. The bias voltage V.sub.b21 is applied on the bias resistor corresponding to the second transistor Q.sub.1, a bias current output by the second transistor Q.sub.1 may be changed. This implements gain control of the fourth amplifying circuit Q.sub.2. In this application, for ease of description, no symbol is used to mark them in FIG. 3a to FIG. 3c.

(25) In this embodiment, the first transistor Q.sub.0 and the second transistor Q.sub.1 may be triodes, for example, bipolar junction transistors (BJT). In this case, respective bases of the first transistor Q.sub.0 and the second transistor Q.sub.1 are separately configured to receive the second voltage V.sub.rf. After respective collectors of the first transistor Q.sub.0 and the second transistor Q.sub.1 are short-circuited, the first transistor Q.sub.0 and the second transistor Q.sub.1 are configured to output the fourth current i.sub.n2. Respective emitters of the first transistor Q.sub.0 and the second transistor Q.sub.1 are separately coupled to ground through the second degeneration circuit L2. By changing the bias voltages of the respective bases of the first transistor Q.sub.0 and the second transistor Q.sub.1, namely, the first bias voltage V.sub.b20 and the second bias voltage V.sub.b21, transconductance of the triode can be controlled. This implements the gain control.

(26) In another implementation, as shown in FIG. 3b, the fourth amplifying circuit Q.sub.n2 may include the first transistor Q.sub.0, the second transistor Q.sub.1, a third transistor Q.sub.2, and a fourth transistor Q.sub.3 that are connected in parallel. It should be understood that the structures of the first amplifying circuit Q.sub.p1, the second amplifying circuit Q.sub.p2, and the third amplifying circuit Q.sub.n1 are also separately the same as the structure of the fourth amplifying circuit Q.sub.n2. When the first transistor Q.sub.0, the second transistor Q.sub.1, the third transistor Q.sub.2, and the fourth transistor Q.sub.3 are all triodes, for a connection relationship among a base, a collector, and an emitter of each triode, refer to FIG. 3a and descriptions of a corresponding embodiment. Details are not described herein again. By independently controlling a base bias voltage (namely, V.sub.b20, V.sub.b21, V.sub.b22, V.sub.b23) of each triode, transconductance of each triode may be changed. This implements overall gain control of the fourth amplifying circuit Q.sub.n2. It should be understood that gain control is separately performed on the first amplifying circuit Q.sub.p1, the second amplifying circuit Q.sub.p2, the third amplifying circuit Q.sub.n1, and the fourth amplifying circuit Q.sub.n2. Finally, an overall gain of the variable gain amplifier 30 may be affected.

(27) In another implementation, the plurality of parallel transistors in the fourth amplifying circuit Q.sub.n2 may alternatively be metal-oxide semiconductor (MOS) transistors. As shown in FIG. 3c, for example, a P-channel MOS transistor is used as a transistor. The fourth amplifying circuit Q.sub.n2 may include four MOS transistors that are connected in parallel. To be distinguished from the triodes in FIG. 3a and FIG. 3b, M0, M1, M2 and M3 are separately used herein to represent the four MOS transistors. In this case, gates of the MOS transistors (M0, M1, M2, and M3) are configured to receive the second voltage V.sub.rf¬. Respective drains of the MOS transistors (M0, M1, M2, and M3) are short-circuited together, and then are configured to combine respective drain currents of the MOS transistors (M0, M1, M2, and M3), to output the fourth current i.sub.n2. Respective sources of the MOS transistors (M0, M1, M2, and M3) are separately coupled to ground through the second degeneration circuit L2. By changing bias voltages of the gates of the MOS transistors (M0, M1, M2, and M3), namely, V.sub.b20, V.sub.b21, V.sub.b22 and V.sub.b23, transconductance of each MOS transistor may be controlled. This implements the gain control of the fourth amplifying circuit Q.sub.n2. For the structures of the first amplifying circuit Q.sub.p1, the second amplifying circuit Q.sub.p2, and the third amplifying circuit Q.sub.n1, refer to the structure of the fourth amplifying circuit Q.sub.n2. Details are not described again.

(28) To better describe how the variable gain amplifier provided in this embodiment improves the linearity, the following uses a triode as an example to describe a gain control principle of the technical solution of this application. When the MOS transistors are used, a gain control principle of the MOS transistors is similar.

(29) A person skilled in the art should know that, in the triode, a collector current I.sub.c of the triode is closely related to a base voltage of the triode, as shown in formula (1):
I.sub.c=I.sub.s*e.sup.V.sup.be.sup./V.sup.t  (1)

(30) I.sub.s is a saturation current, V.sub.be is a junction voltage between a base and an emitter, and V.sub.t is a thermal voltage, where

(31) $V_T=\frac{\mathrm{kT}}{q}.$
k represents a Boltzmann constant (namely, k=1.386488×10.sup.−23J/K), T represents a Fahrenheit temperature, and q represents a quantity of charges of an elementary charge (namely, q=1.602 176 565×10.sup.−19 C).

(32) Correspondingly, a transconductance gain g.sub.m of the triode may be expressed as:
g.sub.m=∂I.sub.c/∂V.sub.be=I.sub.c/V.sub.t  (2)

(33) Therefore, the transconductance gain g.sub.m of the triode is proportional to I.sub.c.

(34) Further, FIG. 4 shows the differential input pair Q.sub.p2 and Q.sub.n1 of the variable gain amplifier in FIG. 3a to FIG. 3c. It can be seen that the differential first voltage V.sub.rf+ and the differential second voltage V.sub.rf¬ are separately input to bases of the differential input pair Q.sub.p2 and Q.sub.n1, and at the same time, collectors of the differential input pair Q.sub.p2 and Q.sub.n1 are short-circuited. An output current I.sub.out of the differential input pair Q.sub.p2 and Q.sub.n1 may be expressed as:
I.sub.out=i.sub.p2+i.sub.n1=g.sub.m2*V.sub.rf++g.sub.m1*V.sub.rf−=(g.sub.m2−g.sub.m1)*V.sub.rf=(|i.sub.p2|−|i.sub.p1|)*V.sub.rf/V.sub.t  (3)

(35) g.sub.m1 is a transconductance gain of Q.sub.p2, g.sub.m2 is a transconductance gain of Q.sub.n1, and V.sub.rf=|V.sub.rf+|−|V.sub.rf−|.

(36) It can be seen from formula (3) that, by changing the bias voltages V.sub.b1 and V.sub.b2 of respective bases or gates of the differential input pairs Q.sub.p2 and Q.sub.n1, magnitudes of the second current I.sub.p2 and the third current I.sub.n1 that flow through the differential input pair Q.sub.p2 and Q.sub.n1 can be controlled independently. In this way, transconductance of the differential input pair Q.sub.p2 and Q.sub.n1 is controlled to implement gain control.

(37) Further, refer to FIG. 5. The gain control principle shown in FIG. 4 is further extended to the variable gain amplifiers 30 shown in FIG. 3a to FIG. 3b. It should be noted that a structure of the variable gain amplifier 30 in FIG. 5 is the same as that in FIG. 3a to FIG. 3b, and reference may be made to FIG. 3a to FIG. 3b. A difference lies in that FIG. 5 further shows a bias network 33 configured to provide the bias voltages V.sub.b1 and V.sub.b2. For example, by changing magnitudes of currents transmitted by a current source I.sub.t and a current source I.sub.2 in the bias network 33 to the bias resistors R1/R3 and R2/R4, the bias voltages V.sub.b1 and V.sub.b2 may be controlled.

(38) In this embodiment, a key to implementing the gain control on the variable gain amplifier 30 lies in a current distribution policy. A bias current of the variable gain amplifier 30 meets the following condition:
|i.sub.p2+i.sub.n1|=|i.sub.n2+i.sub.p1|=C  (4)

(39) C is a constant, in other words, total currents of i.sub.out+ and i.sub.out− are the same, but polarities of i.sub.out+ and i.sub.out− are opposite.

(40) Correspondingly, a final gain of the variable gain amplifier 40 may be calculated by using formula 5:

(41) $\begin{array}{cc}\mathrm{Gain}\propto \frac{\left(i_{out+}-i_{out-}\right)}{\left(V_{\mathrm{rf}+}-V_{\mathrm{rf}-}\right)}& \left(5\right)\end{array}$

(42) Gain represents a gain of the variable gain amplifier 30.

(43) Theoretically, the gain control may be implemented by controlling a percentage of a current flowing through the second amplifying circuit Q.sub.p2 (or the fourth amplifying circuit Q.sub.n2) and the first amplifying circuit Q.sub.p1 (or the third amplifying circuit Q.sub.n1). For example, when the current i.sub.p2 flowing through the second amplifying circuit Q.sub.p2 is the same as the current i.sub.n1 flowing through the third amplifying circuit Q.sub.n1, because of positive and negative cancellation, the current signal i.sub.out output by the variable gain amplifier 30 is 0, and the gain is the smallest. When all currents flow through the second amplifying circuit Q.sub.p2, and when the third amplifying circuit Q.sub.n1 is turned off, the variable gain amplifier 30 may obtain a maximum gain. It can be seen that the current distribution policy impacts gain adjustment precision and a dynamic range of the variable gain amplifier 30.

(44) In this embodiment, to better control the gain of the variable gain amplifier 30, the following current distribution policy is proposed.

(45) It is assumed that N-bit (bit) gain control needs to be implemented, where N is a positive integer, and each time a gain level is adjusted, a current change amount of a transistor is I.sub.0. A bias current relationship of the variable gain amplifier 30 may be expressed as follows:
i.sub.p2+i.sub.n1=i.sub.n2+i.sub.p1=I.sub.sum=2.sup.N*I.sub.0  (6)

(46) For example, when the variable gain amplifier 30 is in the highest gain, the current i.sub.p2 flowing through the second amplifying circuit Q.sub.p2 may be 2.sup.N*I.sub.0. In addition, because the third amplifying circuit Q.sub.n1 is turned off, the current i.sub.n1 flowing through the third amplifying circuit Q.sub.n1 is 0. When i.sub.p2=i.sub.n1=2.sup.N-1*I.sub.0, because i.sub.p2 and i.sub.n1 cancel each other out, the variable gain amplifier 30 has no output signal, and therefore the gain is the smallest.

(47) The following uses 6-bit gain control as an example to describe a current change of any differential input pair (for example, Q.sub.p2 and Q.sub.n1, or Q.sub.p1 and Q.sub.n2) in the variable gain amplifier 30 at each gain level with reference to Table 1. delta_Gain indicates again change relative to the maximum gain (Gmax), Gain_step indicates again adjustment step, and Gmin indicates the minimum gain.

(48) TABLE-US-00001 TABLE 1 Gain state delta_Gain Gain_step (Gain state) I.sub.p2/I.sub.n2 I.sub.n1/I.sub.p1 I.sub.sum (dB) (dB)  1 (Gmax) 64*I.sub.0 0 64*I.sub.0 0.000 0.000 2 63*I.sub.0  1*I.sub.0 64*I.sub.0 −0.276 −0.276 3 62*I.sub.0  2*I.sub.0 64*I.sub.0 −0.561 −0.285 4 61*I.sub.0  3*I.sub.0 64*I.sub.0 −0.855 −0.294 5 60*I.sub.0  4*I.sub.0 64*I.sub.0 −1.160 −0.305 6 59*I.sub.0  5*I.sub.0 64*I.sub.0 −1.476 −0.316 7 58*I.sub.0  6*I.sub.0 64*I.sub.0 −1.804 −0.328 8 57*I.sub.0  7*I.sub.0 64*I.sub.0 −2.144 −0.341 9 56*I.sub.0  8*I.sub.0 64*I.sub.0 −2.499 −0.355 10 55*I.sub.0  9*I.sub.0 64*I.sub.0 −2.868 −0.370 11 54*I.sub.0 10*I.sub.0 64*I.sub.0 −3.255 −0.386 12 53*I.sub.0 11*I.sub.0 64*I.sub.0 −3.659 −0.404 13 52*I.sub.0 12*I.sub.0 64*I.sub.0 −4.082 −0.424 14 51*I.sub.0 13*I.sub.0 64*I.sub.0 −4.528 −0.446 15 50*I.sub.0 14*I.sub.0 64*I.sub.0 −4.998 −0.470 16 49*I.sub.0 15*I.sub.0 64*I.sub.0 −5.494 −0.496 17 48*I.sub.0 16*I.sub.0 64*I.sub.0 −6.021 −0.527 18 47*I.sub.0 17*I.sub.0 64*I.sub.0 −6.581 −0.561 19 46*I.sub.0 18*I.sub.0 64*I.sub.0 −7.180 −0.599 20 45*I.sub.0 19*I.sub.0 64*I.sub.0 −7.824 −0.644 21 44*I.sub.0 20*I.sub.0 64*I.sub.0 −8.519 −0.695 22 43*I.sub.0 21*I.sub.0 64*I.sub.0 −9.275 −0.756 23 42*I.sub.0 22*I.sub.0 64*I.sub.0 −10.103 −0.828 24 41*I.sub.0 23*I.sub.0 64*I.sub.0 −11.018 −0.915 25 40*I.sub.0 24*I.sub.0 64*I.sub.0 −12.041 −1.023 26 39*I.sub.0 25*I.sub.0 64*I.sub.0 −13.201 −1.160 27 38*I.sub.0 26*I.sub.0 64*I.sub.0 −14.540 −1.339 28 37*I.sub.0 27*I.sub.0 64*I.sub.0 −16.124 −1.584 29 36*I.sub.0 28*I.sub.0 64*I.sub.0 −18.062 −1.938 30 35*I.sub.0 29*I.sub.0 64*I.sub.0 −20.561 −2.499 31 34*I.sub.0 30*I.sub.0 64*I.sub.0 −24.08 −3.522 32 33*I.sub.0 31*I.sub.0 64*I.sub.0 −30.103 −6.021 33 (Gmin) 32*I.sub.0 32*I.sub.0 64*I.sub.0

(49) It can be seen from Table 1 that, when the 6-bit gain control is adopted, again of the differential input pair in the variable gain amplifier 30 transits from the maximum gain Gmax to the minimum gain Gmin, which may include 33 gain states in total, namely, gain states 1, 2, . . . 33. The gain state 1 represents the maximum gain Gmax of the differential input pair, the gain state 33 represents the minimum gain Gmin of the differential input pair, and the gain states 2 to 32 separately correspond to transition states from Gmax to Gmin. For ease of description below, again state Gmax and again state Gmin are also used. For details, refer to Table 1 and the description herein. Details are not described subsequently.

(50) In Table 1, by comparing the gain state 1 and the gain state 33, it can be seen that a dynamic range of the gain change may reach about 30 decibels (dB). In addition, Gain_step of the variable gain amplifier 30 is mainly determined by a quantity of bits for gain control. Theoretically, a larger the quantity of bits for the gain control indicates more precise adjustment of Gain_step.

(51) Further, it can be seen from Table 1 that, a bias current of one amplifying circuit of the differential input pair increments, while a bias current of the other amplifying circuit decrements. In addition, the current change of each level is fixed at I.sub.0 when the current increments or decrements. When the dynamic range is large, Gain_step is also large. To make adjustment of Gain_step more precise, different current change amounts may be set for each level. In other words, a current distribution policy with unequal current steps is used. For example, when the dynamic range is large, a current change amount of each step may be reduced, to reduce Gain_step. If the current distribution policy with unequal current steps is used, linear (linear-dB) gain adjustment can be theoretically implemented.

(52) The foregoing description is how the variable gain amplifier 30 implements the gain control. The following further describes a reason why linearity of a transistor deteriorates with a gain change, and an improved solution provided in this embodiment.

(53) In a radio frequency or microwave frequency band, when the bias current I.sub.c of the transistor is changed, a power (P_IM3) of a third-order inter-modulation signal output by the transistor changes as shown in FIG. 6. It can be seen that, when a size of the transistor is fixed, regardless of the large-sized transistor or the small-sized transistor, as the bias current I.sub.c increases, the third-order inter-modulation power P_IM3 of the transistor gradually decreases, and therefore relatively good linearity is presented. This is caused by different parasitic parameters of the transistor under different current density, which an inherent physical characteristic of the transistor. To be specific, a characteristic frequency f.sub.t of the transistor increases with current density of I.sub.c. In a high-frequency application scenario, this phenomenon of a transistor is more obvious.

(54) It can be seen from FIG. 6 that, when a bias current flowing through the transistor is relatively small, the third-order inter-modulation power of the transistor is relatively high, and correspondingly, the linearity is relatively poor. Therefore, the third-order inter-modulation power of the transistor becomes a key factor that restricts the linearity of the variable gain amplifier.

(55) FIG. 7 shows an equivalent circuit of the variable gain amplifier 30 shown in FIG. 3a to FIG. 3c. As shown in FIG. 7, in the maximum gain state Gmax, the first amplifying circuit Q.sub.p1 is turned off, all the bias currents flow through the second amplifying circuit Q.sub.p2, and the linearity of the variable gain amplifier is determined by the second amplifying circuit Q.sub.p2. When the bias current is relatively large, the third-order inter-modulation power of the second amplifying circuit Q.sub.p2 is relatively low. In this case, the linearity of the variable gain amplifier 30 is relatively good. However, when the gain switches from the maximum gain state to a lower gain state, a bias current of the third amplifying circuit Q.sub.n1 gradually increases from 0. In this case, because the bias current flowing through the third amplifying circuit Q.sub.n1 is relatively small, the third amplifying circuit Q.sub.n1 generates a relatively large third-order inter-modulation power. After the current i.sub.n1 generated by the third amplifying circuit Q.sub.n1 and the current i.sub.p2 generated by the second amplifying circuit Q.sub.p2 are combined to obtain i.sub.out−, a third-order inter-modulation power of the entire variable gain amplifier is determined by the third amplifying circuit Q.sub.n1. Because the bias current is relatively small, the linearity of the transistor is relatively poor, and consequently, the linearity of the variable gain amplifier 30 is reduced relative to the maximum gain state.

(56) Further, as shown in FIG. 8, when the variable gain amplifier implements gain switching by switching a Gm stage, within a certain range of switching downward from the highest gain state, the linearity of the variable gain amplifier is mainly determined by a transistor with a small current. As a result, an obvious pit of the linearity of the variable gain amplifier is displayed in the entire dynamic range (as shown in a linearity bottleneck range in FIG. 8). IIP3 is an input third-order intercept point, and Gain is the gain. Particularly, it can be seen from FIG. 8 that, as a frequency (Freq) increases (for example, 30 GHz.fwdarw.40 GHz.fwdarw.60 GHz), the linearity of the variable gain amplifier decreases more, and the pit is more obvious. This is an inherent defect of the variable gain amplifier shown in FIG. 3. When the transistor uses a MOS transistor or a bipolar junction transistor (BJT) technology, a same problem also exists. With the popularization of the fifth-generation mobile communications (5G) applications, a working frequency is continuously increased to the microwave frequency band. This problem will become more serious. To be specific, as the frequency increases, the linearity of the variable gain amplifier decreases more.

(57) It can be seen from the foregoing analysis that a main reason why the linearity of the variable gain amplifier has a performance bottleneck is that a current flowing through a transistor of the variable gain amplifier is relatively small. It should be noted that, to better reflect superiority of the technical solutions of this application, in the foregoing descriptions of FIG. 6 to FIG. 8 and the corresponding gain control principles, it is assumed that the first amplifying circuit Q.sub.p1, the second amplifying circuit Q.sub.p2, the third amplifying circuit Q.sub.n1, and the fourth amplifying circuit Q.sub.n2 separately uses one transistor are described. Because in a conventional Gm-stage circuit, a differential input pair is formed by a pair of transistors.

(58) In this embodiment, the first amplifying circuit Q.sub.p1, the second amplifying circuit Q.sub.p2, the third amplifying circuit Q.sub.n1, and the fourth amplifying circuit Q.sub.n2 are separately split into the plurality of parallel transistors. A bias of each transistor is controlled independently, a conduction current of each transistor is determined based on a specific gating policy, therefore a worst linearity point (namely, the pit) of the variable gain amplifier can be avoided. In addition, advantages of a large dynamic (delta_Gain) and a small step (Gain_step) of the variable gain amplifier during the gain control are maintained.

(59) FIG. 9 shows a half-side equivalent circuit corresponding to the second amplifying circuit Q.sub.p2 and the third amplifying circuit Q.sub.n1 in FIG. 3. The following describes a gating policy in detail with reference to FIG. 9.

(60) It is assumed that in a conventional Gm-stage circuit, the second amplifying circuit Q.sub.p2 and the third amplifying circuit Q.sub.n1 each use one transistor, and sizes of the transistors are both W. For ease of description, the following describes a case in which each amplifying circuit in a conventional Gm-stage circuit uses one transistor by using a non-splitting manner for a transistor. Under each gain state of a variable gain amplifier, magnitudes of currents flowing through respective transistors of the second amplifying circuit Q.sub.p2 and the third amplifying circuit Q.sub.n1 are shown in Table 2. It should be noted that a current variation at each level in Table 2 is I.sub.0 by default. For simplicity, only a number indicating a current magnitude is shown in the table. It should be known that, using a Gmax state as an example, a current iQ.sub.p2 flowing through the second amplifying circuit Q.sub.p2 should be 2.sup.N*I.sub.0. Currents in a subsequent table are expressed in a similar manner. Details are not described again.

(61) TABLE-US-00002 TABLE 2 Q.sub.p2 Q.sub.n1 Gain state Current 2.sup.N 0 Gmax 2.sup.N − 1 1 . . . 2.sup.N − 2 2 Gmin 2.sup.N − 3 3 . . . . . . 2.sup.N − 1 2.sup.N − 1 Size W W

(62) Refer to FIG. 3a, if the second amplifying circuit Q.sub.p2 and the third amplifying circuit Q.sub.n1 are equally split into two parts based on the transistor sizes, in other words, the second amplifying circuit Q.sub.p2 is split into a transistor Q.sub.P2<0> and a transistor Q.sub.p2<1> that are connected in parallel, and the third amplifying circuit Q.sub.n1 is split into a transistor Q.sub.n1<0> and a transistor Q.sub.n1<1> that are connected in parallel. Sizes of the transistor Q.sub.P2<0>, the transistor Q.sub.P2<1>, the transistor Q.sub.n1<0>, and the transistor Q.sub.n1<1> are all W/2. In this case, in each gain state of the variable gain amplifier, magnitudes of currents that separately flow through the transistor Q.sub.P2<0>, Q.sub.p2<1>, Q.sub.n1<0>, and Q.sub.n1<1> may be shown in Table 3.

(63) TABLE-US-00003 TABLE 3 Q.sub.p2<1> Q.sub.p2<0> Q.sub.n1<1> Q.sub.n1<0> Gain state Current 2.sup.N−1 2.sup.N−1 0 0 Gmax 2.sup.N−1 2.sup.N−1−1 0 1 . . . 2.sup.N−1 2.sup.N−1−2 0 2 Gmin . . . . . . . . . . . . 2.sup.N−1 1 0 2.sup.N−1−1 2.sup.N−1 0 0 2.sup.N−1 Size W/2 W/2 W/2 W/2

(64) It can be seen from Table 3 that, in a current distribution policy provided in this embodiment, when a gain of any differential input pair (namely, Q.sub.p2 and Q.sub.n1, or Q.sub.p1 and Q.sub.n2) is switched, for example, when the current distribution policy is switched downward from a highest gain state, in the differential input pair, a total bias current output by the transistors in one amplifying circuit decrements, while a total bias current output by the transistors in the other amplifying circuit increments. A total current of the differential input pair remains unchanged. For example, in Table 3, a bias current output by the second amplifying circuit Q.sub.p2 is i.sub.Qp2=i.sub.Qp2<1>+i.sub.Qp2<0>, and a bias current output by the third amplifying circuit Q.sub.n1 is i.sub.Qn1=i.sub.Qn1<1>+i.sub.Qn1<0>, where i.sub.Qp2 decrements, and i.sub.Qn1 increments. An increment or decrement amplitude, namely, a step value of current adjustment, is I.sub.0.

(65) It can be seen from Table 3 that, when the gain state is switched from Gmax to Gmin, the second state in the table (refer to Table 1, Gmax is a first state, and the second state is equivalent to that a control bit corresponding to the gain state Gmax changes by 1 bit) is taken as an example, where, i.sub.Qn1<1>=0, i.sub.Qn1<0>=1*I.sub.0. Compared with the second state in Table 2 (where i.sub.Qn1=1*I.sub.0), the total current i.sub.Qn1 flowing through the third amplifying circuit Q.sub.n1 remains unchanged and is still 1*I.sub.0. Because the transistor Q.sub.n1<0> and the transistor Q.sub.n1<1> are connected in parallel, and i.sub.Qn1=i.sub.Qn1<1>+i.sub.Qn1<0>, a current relationship between another amplifying circuit and each of a plurality of transistors obtained after being split from the amplifying circuit is similar. Details are not described again. However, in Table 3, 1*I.sub.0 flows through only one transistor Q.sub.n1<0> in the third amplifying circuit Q.sub.n1, the size of the transistor Q.sub.n1<0> is W/2, and the other transistor Q.sub.n1<1> is turned off. Therefore, it can be learned that, when the third amplifying circuit Q.sub.n1 is split into the two parallel transistors, current density flowing through the third amplifying circuit Q.sub.n1 is two times that in a case in which the third amplifying circuit Q.sub.n1 is not split. It can be learned from FIG. 6 and the foregoing analysis that, for a same size, a larger current flowing through the transistor indicates a smaller third-order inter-modulation power. Correspondingly, linearity is better. Therefore, in this embodiment, the amplifying circuit in which one transistor is used in a conventional solution is split into the two parallel transistors. This improves the current density in the amplifying circuit, and further improves the linearity of the variable gain amplifier.

(66) Further, as shown in FIG. 3b and Table 4, if a transistor size of the amplifying circuit is equally split into four parts, for example, the second amplifying circuit Q.sub.p2 is split, from one transistor in the conventional solution, into four transistors Q.sub.p2<0>, Q.sub.p2<1>, Q.sub.p2<2> and Q.sub.p2<3> that are connected in parallel, and the third amplifying circuit Q.sub.n1 is split into four transistors Q.sub.n1<0>, Q.sub.n1<1>, Q.sub.n1<2> and Q.sub.n1<3> that are connected in parallel. Sizes of Q.sub.p2<0>, Q.sub.p2<1>, Q.sub.p2<2>, Q.sub.p2<3>, Q.sub.n1<0>, Q.sub.n1<1>, Q.sub.n1<2> and Q.sub.n1<3> are all W/4. Therefore, when a gain is switched from the highest state Gmax to the lowest state Gmin, magnitude of a current flowing through each transistor is shown in Table 4.

(67) TABLE-US-00004 TABLE 4 Gain Q.sub.p2<3> Q.sub.p2<2> Q.sub.p2<1> Q.sub.p2<0> Q.sub.n1<3> Q.sub.n1<2> Q.sub.n1<1> Q.sub.n1<0> state Cur- 2.sup.N-2 2.sup.N-2 2.sup.N-2 2.sup.N-2 0 0 0 0 Gmax rent 2.sup.N-2 2.sup.N-2 2.sup.N-2 2.sup.N-2-1 0 0 0 1 2.sup.N-2 2.sup.N-2 2.sup.N-2 2.sup.N-2-2 0 0 0 2 . . . . . . 2.sup.N-2 2.sup.N-2 2.sup.N-2 2.sup.N-2 0 0 0 2.sup.N-2 2.sup.N-2 2.sup.N-2 2.sup.N-2 2.sup.N-2-1 0 0 1 2.sup.N-2 2.sup.N-2 2.sup.N-2 2.sup.N-2 2.sup.N-2-2 0 0 2 2.sup.N-2 . . . . . . 2.sup.N-2 2.sup.N-2 0 0 0 0 2.sup.N-2 2.sup.N-2 Gmin Size W/4 W/4 W/4 W/4 W/4 W/4 W/4 W/4

(68) It can be learned from the table that, for example, when the gain state changes from the first state (Gmax) to the second state, the current i.sub.Qn1 flowing through the third amplifying circuit Q.sub.n1 remains unchanged and is still 1*I.sub.0. However, 1*I.sub.0 flows through only ¼ of the transistors, and the other ¾ of the transistors are turned off. Therefore, current density flowing through Q.sub.n1 is four times that in a case in which the third amplifying circuit Q.sub.n1 is not split. It can be learned from the foregoing analysis that, compared with the bias current flowing through the second amplifying circuit Q.sub.p2, the bias current flowing through the third amplifying circuit Q.sub.n1 is relatively small. After the current iQ.sub.n1 generated by the third amplifying circuit Q.sub.n1 and the current i.sub.Qp2 generated by the second amplifying circuit Q.sub.p2 are combined to obtain i.sub.out−, a third-order inter-modulation power of the entire variable gain amplifier is determined by the third amplifying circuit Q.sub.n1. After the third amplifying circuit Q.sub.n1 is split into four equal parts, because the current density of the third amplifying circuit Q.sub.n1 is higher than that in the case in which the third amplifying circuit Q.sub.n1 is not split, correspondingly, a third-order inter-modulation power corresponding to the third amplifying circuit Q.sub.n1 is reduced. This further improves the linearity of the variable gain amplifier.

(69) Further, FIG. 10 shows a comparison curve of linearity of a variable gain amplifier in several cases such as in a halved splitting manner, a quartered splitting manner, and a non-splitting manner. It can be seen that, as a quantity of transistors after splitting increases, a problem that a pit exists when linearity of the VGA is switched with a gain is avoided. In this way, the performance bottleneck of the linearity of the VGA within a dynamic gain range is broken through, and overall circuit performance is improved. By analogy, the amplifying circuit may be split into 2N groups (N=1, 2, 3 . . . ) of transistors. After the splitting, the linearity of the VGA increases in sequence, where N is a positive integer.

(70) In this embodiment, when a transistor size is split into four parts, an unequal splitting manner may further be used. For example, a second amplifying circuit Q.sub.p2 may be split into four transistors Q.sub.p2<0>, Q.sub.p2<1>, Q.sub.p2<2>, and Q.sub.p2<3> that are connected in parallel. Sizes of the four transistors are sequentially W/8, W/8, W/4, W/2. In addition, a third amplifying circuit Q.sub.n1 is split into four transistors Q.sub.n1<0>, Q.sub.n1<1>, Q.sub.n1<2>, and Q.sub.n1<3> that are connected in parallel. Sizes of the four transistors are also sequentially W/8, W/8, W/4 and W/2. When a VGA gain is switched from a highest state to a lowest state, for magnitude of a current flowing through each transistor, refer to Table 5.

(71) TABLE-US-00005 TABLE 5 Gain Q.sub.p2<3> Q.sub.p2<2> Q.sub.p2<1> Q.sub.p2<0> Q.sub.n1<3> Q.sub.n1<2> Q.sub.n1<1> Q.sub.n1<0> state Cur- 2.sup.N-2 2.sup.N-2 2.sup.N-2 2.sup.N-2 0 0 0 0 Gmax rent 2.sup.N-2 2.sup.N-2 2.sup.N-2 2.sup.N-2-1 0 0 0 1 2.sup.N-2 2.sup.N-2 2.sup.N-2 2.sup.N-2-2 0 0 0 2 . . . . . . 2.sup.N-2 2.sup.N-2 2.sup.N-2 2.sup.N-2 0 0 0 2.sup.N-2 2.sup.N-2 2.sup.N-2 2.sup.N-2 2.sup.N-2-1 0 0 1 2.sup.N-2 2.sup.N-2 2.sup.N-2 2.sup.N-2 2.sup.N-2-2 0 0 2 2.sup.N-2 . . . . . . 2.sup.N-2 2.sup.N-2 0 0 0 0 2.sup.N-2 2.sup.N-2 Gmin Size W/2 W/4 W/8 W/8 W/2 W/4 W/8 W/8

(72) It can be seen that, in a second gain state (in other words, the gain state decreases by 1 bit from Gmax), a total current iQ.sub.n1 flowing through the third amplifying circuit Q.sub.n1 remains unchanged and is still 1*I.sub.0. However, 1*I.sub.0 flows through only the transistor Q.sub.n1<0>, and the size of Q.sub.n1<0> is W/8, which is equivalent to that 1*I.sub.0 flows through only ⅛ of the transistors in the third amplifying circuit Q.sub.n1, and the other ⅞ of the transistors are turned off. Therefore, current density of the total current i.sub.Qn1 flowing through the third amplifying circuit Q.sub.n1 is eight times that in a case in which the third amplifying circuit Q.sub.n1 is not split. In addition, compared with the quartered splitting manner of the third amplifying circuit Q.sub.n1, the current density is also improved by two times. Therefore, a non-quartered splitting manner can further improve the linearity of the VGA.

(73) FIG. 11 shows a comparison curve of the linearity of the variable gain amplifier in the non-splitting manner, the quartered splitting manner, and the non-quartered splitting manner. It can be seen that, compared with the non-splitting manner or the quartered splitting manner on the transistor size, the non-quartered splitting manner can better avoid the problem that the pit exists when the linearity of the VGA is switched with the gain, and further improve the linearity.

(74) By analogy, the amplifying circuit may be split from a conventional transistor into 2N (N=1, 2, 3 . . . ) parallel transistors. A size proportion of the 2N transistors may be adjusted based on a design requirement, to achieve an optimal linearity improvement effect. For example, four transistors that are connected in parallel are used as an example. As shown in Table 6, this embodiment provides several different split ratios.

(75) TABLE-US-00006 TABLE 6 2N = 4 Q.sub.p2<3> Q.sub.p2<2> Q.sub.p2<2> Q.sub.p2<2> Total size Split ratio 1 W/4 W/4 W/4 W/4 W Split ratio 2 W/2 W/4 W/8 W/8 W Split ratio 3 3W/4 W/8 W/16 W/16 W

(76) Further, as shown in FIG. 12, an embodiment of this application further provides an electronic apparatus 40. Specifically, the electronic apparatus 40 may be a phased array receiver, a phased array transmitter, or a phased array transceiver. Alternatively, the electronic apparatus 40 may be an electronic device to which the phased array receiver, the phased array transmitter, or the phased array transmitter is applied, for example, a mobile phone, a base station, or a personal computer. The electronic device 40 includes a plurality of antennas 41, a radio frequency front-end 42, and a combiner 43.

(77) For example, the plurality of antennas 41 may be an antenna 1, an antenna 2, . . . , and an antenna N, where N is a positive integer greater than 1.

(78) The radio frequency front-end 42 includes a plurality of radio frequency channels 42 that one-to-one correspond to the plurality of antennas 41, and the plurality of radio frequency channels 42 are separately coupled to the plurality of antennas 41. Each radio frequency channel includes at least one of a radio frequency receive channel or a radio frequency transmit channel, and the radio frequency receive channel or the radio frequency transmit channel separately includes the variable gain amplifier described in the foregoing embodiments. For a structure of the variable gain amplifier, refer to the foregoing embodiments. Details are not described herein again. In other words, if the electronic apparatus 40 is the phased array transmitter, each radio frequency channel includes the radio frequency transmit channel. If the electronic apparatus 40 is the phased array receiver, correspondingly, each radio frequency channel includes the radio frequency receive channel. If the electronic apparatus 40 is the phased array transceiver that integrates receiving and transmitting functions, each radio frequency channel includes the radio frequency receive channel and the radio frequency transmit channel.

(79) The combiner 43 is coupled to the plurality of radio frequency channels 42.

(80) Specifically, as shown in FIG. 11, the radio frequency receive channel may include a low-noise amplifier (LNA) 420, a variable gain amplifier (VGA) 421, an amplifier (Amp) 422, and a phase shifter (PS) 423. An input end of the LNA 420 is coupled to an antenna corresponding to the radio frequency receive channel, and an output end of the LNA 420 is coupled to an input end of the VGA 421. An output end of the VGA 421 is coupled to an input end of the amplifier 422, and an output end of the amplifier 422 is coupled to an input end of the phase shifter 423. An output end of the phase shifter 423 is coupled to the combiner 43. The LNA 420 is configured to amplify a weak signal received from the air by the antenna corresponding to the radio frequency receive channel, and reduce noise interference. The signal processed by the LNA 420 is further amplified by the VGA 421 and the amplifier 422, and then phase modulation is performed by the phase shifter 423.

(81) The radio frequency transmit channel may include a power amplifier (PA) 424, a VGA 425, an amplifier 426, and a phase shifter (PS) 427. An input end of the phase shifter 427 is coupled to the combiner 43, and an output end of the phase shifter 427 is coupled to an input end of the amplifier 426. An output end of the amplifier 426 is coupled to an input end of the variable gain amplifier 425, and an output end of the variable gain amplifier 425 is coupled to an input end of the power amplifier 424. An output end of the power amplifier 424 is coupled to an antenna corresponding to the radio frequency transmit channel. The phase shifter 427 is configured to perform phase modulation on one of a plurality of signals output by the combiner 43, and then the signal is amplified by the amplifier 426 and the VGA 425. Finally, the PA 424 amplifies the signal processed by the amplifier 426 and the VGA 425 to sufficient power, and then transmits the signal through the antenna 41.

(82) In the phased array transmitter, the combiner 43 is configured to divide an up-converted RF signal into a plurality of signals, and provide the plurality of signals for each radio frequency transmit channel. In the phased array receiver, the combiner 43 is configured to combine signals obtained after phase modulation is performed on the plurality of radio frequency receive channels, and then provide the combined signals for a next-stage circuit for down conversion.

(83) In this embodiment, because the VGAs 421 or 425 used can maintain good linearity in different gain states, the VGAs can not only amplify a signal, but also keep a phase of the amplified signal constant. Therefore, deterioration of performance of the phase shifters PS423 or 427 can be avoided or reduced, and a requirement of the electronic apparatus 40 for a constant phase can be met.

(84) Obviously, a person skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. This application is intended to cover these modifications and variations of this application provided that they fall within the scope of protection defined by the following claims and their equivalent technologies.