Resistance test method using kelvin structure

Abstract

The disclosure discloses a resistance test method using a Kelvin structure, which includes the following steps: step 1: providing a Kelvin test structure including a tested resistor, a first parasitic resistor, and a second parasitic resistor connected in series; step 2: applying first current to the two current test terminals and simultaneously testing first voltage in the two voltage test terminals; step 3: applying second current in a direction opposite to the direction of the first current to the two current test terminals and simultaneously testing second voltage in the two voltage test terminals; step 4: dividing a difference value obtained by subtracting the second voltage from the first voltage by a difference value between the first current and the second current to obtain the final test value of the tested resistor. The disclosure can reduce the resistance test error.

Claims

1. A resistance test method using a Kelvin test structure, the resistance test method comprising: step 1: providing the Kelvin test structure comprising a tested resistor, a first parasitic resistor, and a second parasitic resistor, a first end of the tested resistor being connected with a second end of the first parasitic resistor, and a second end of the tested resistor being connected with a first end of the second parasitic resistor; the tested resistor is a small resistor with resistance less than 1 ohm; the tested resistor is integrated on a semiconductor substrate; the first end and the second end of the tested resistor being two corresponding voltage test terminals; a first end of the first parasitic resistor and a second end of the second parasitic resistor being two corresponding current test terminals; step 2: applying a first current to the two current test terminals and simultaneously testing a first voltage in the two voltage test terminals; step 3: applying a second current to the two current test terminals and simultaneously testing a second voltage in the two voltage test terminals; the direction of the second current being opposite to the direction of the first current; and step 4: dividing a difference value obtained by subtracting the second voltage from the first voltage by a difference value between the first current and the second current to obtain the final test value of the tested resistor.

2. The resistance test method using the Kelvin test structure according to claim 1, wherein the tested resistor comprises at least one of a polysilicon resistor, a diffused resistor, and a metal resistor.

3. The resistance test method using the Kelvin test structure according to claim 1, wherein the semiconductor substrate comprises a silicon substrate.

4. The resistance test method using the Kelvin test structure according to claim 3, wherein in step 2, there is a first error value in the first test value of the tested resistor obtained by dividing the first voltage by the first current; wherein in step 3, there is a second error value in the second test value of the tested resistor obtained by dividing the second voltage by the second current; and wherein the first error value and the second error value are opposite in positivity and negativity, and are set off in step 4, such that the error value of the final test value of the tested resistor is reduced or eliminated.

5. The resistance test method using the Kelvin test structure according to claim 4, wherein the absolute value of the second current is equal to the absolute value of the first current.

6. The resistance test method using the Kelvin test structure according to claim 4, wherein a resistance test using the Kelvin test structure is realized in a wafer acceptance test.

7. The resistance test method using the Kelvin test structure according to claim 6, wherein the two voltage test terminals are formed with pads and the two current test terminals are formed with pads.

8. The resistance test method using the Kelvin test structure according to claim 7, wherein each pad is connected with probes on a probe card of a wafer acceptance tester.

9. The resistance test method using the Kelvin test structure according to claim 8, wherein the first parasitic resistor is a parasitic resistor from the first end of the tested resistor to the current applying end of the wafer acceptance tester; and wherein the second parasitic resistor is a parasitic resistor from the second end of the tested resistor to the current applying end of the wafer acceptance tester.

10. The resistance test method using the Kelvin test structure according to claim 9, wherein a source of the first error value and the second error value comprises an error caused by offset voltage formed by conducting wires and a probe card in a test loop.

11. The resistance test method using the Kelvin test structure according to claim 10, wherein the source of the first error value and the second error value further comprises an error caused by offset voltage corresponding to voltage drift formed at the two voltage test terminals by transient voltage produced when a relay in the wafer acceptance tester is on and off in the test process.

12. The resistance test method using the Kelvin test structure according to claim 11, wherein the order of magnitude of the first error value and the second error value is equivalent to the order of magnitude of the final test value.

13. The resistance test method using the Kelvin test structure according to claim 7, wherein all of the pads are formed by a front metal layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The disclosure will be further described below in detail in combination with the specific embodiments with reference to the drawings.

(2) FIG. 1 is a schematic diagram of an existing Kelvin test structure.

(3) FIG. 2 is a test curve of a resistance test method using an existing Kelvin structure.

(4) FIG. 3 is a flowchart of a resistance test method using a Kelvin structure according to one embodiment of the disclosure.

(5) FIG. 4 is a test curve of the resistance test method using the Kelvin structure according to one embodiment of the disclosure.

DETAILED DESCRIPTION OF THE DISCLOSURE

(6) Referring to FIG. 3, it is a flowchart of a resistance test method using a Kelvin structure according to one embodiment of the disclosure. Referring to FIG. 4, it is a test curve of the resistance test method using the Kelvin structure according to one embodiment of the disclosure. The resistance test method using the Kelvin structure according to one embodiment of the disclosure includes the following steps:

(7) In step 1, a Kelvin test structure is provided and includes a tested resistor Rx, a first parasitic resistor Rc1, and a second parasitic resistor Rc2. A first end 3 of the tested resistor Rx is connected with a second end of the first parasitic resistor Rc1, and a second end 4 of the tested resistor Rx is connected with a first end of the second parasitic resistor Rc2.

(8) The first end 3 and the second end 4 of the tested resistor Rx are two corresponding voltage test terminals.

(9) The first end 1 of the first parasitic resistor Rc1 and the second end 2 of the second parasitic resistor Rc2 are two corresponding current test terminals.

(10) In FIG. 1, a current source connected with the two current test terminals are illustrated and are used to provide test current Ix for the tested resistor Rx, the first parasitic resistor Rc1 and the second parasitic resistor Rc2.

(11) In FIG. 1, a voltmeter connected with the two voltage test terminals are further illustrated and are used to test voltage Vx.

(12) In the method according to the embodiment of the disclosure, the tested resistor Rx is a small resistor with resistance less than 1 ohm.

(13) The tested resistor Rx includes a polysilicon resistor, a diffused resistor, and a metal resistor.

(14) The tested resistor Rx is integrated on a semiconductor substrate.

(15) The semiconductor substrate includes a silicon substrate.

(16) In step 2: first current I1 is applied to the two current test terminals and first voltage Vx1 is simultaneously tested in the two voltage test terminals.

(17) There is a first error value in the first test value of the tested resistor Rx obtained by dividing the first voltage Vx1 by the first current I1.

(18) From FIG. 4, it can be seen that curve 202 corresponds to the true value curve of the tested resistor Rx. However, since the first test value is the value obtained by dividing the first voltage Vx1 by the first current I1, the first test value is the slope corresponding to curve 201. Accordingly, it can be seen that the first test value is greater than the true value, so there is the first error value.

(19) Curve 201 corresponds to the test curve when offset voltage Voffset is 0V, so curve 201 is an ideal curve. However, in fact, the offset voltage Voffset is not zero, so curve 202 is the curve corresponding to the true value. Obviously, through step 2, curve 202 cannot be obtained and only curve 201 can be obtained.

(20) In step 3, second current I2 is applied to the two current test terminals and second voltage Vx2 is simultaneously tested in the two voltage test terminals. The direction of the second current I2 is opposite to the direction of the first current I1.

(21) There is a second error value in the second test value of the tested resistor Rx obtained by dividing the second voltage Vx2 by the second current I2.

(22) From FIG. 4, it can be seen that curve 204 corresponds to the true value curve of the tested resistor Rx. However, since the second test value is the value obtained by dividing the second voltage Vx2 by the second current I2, the second test value is the slope corresponding to curve 203. Accordingly, it can be seen that the second test value is smaller than the true value, so there is the second error value.

(23) Curve 203 corresponds to the test curve when offset voltage Voffset is 0V, so curve 203 is an ideal curve. However, in fact, the offset voltage Voffset is not zero, so curve 204 is the curve corresponding to the true value. Obviously, through step 3, curve 204 cannot be obtained and only curve 203 can be obtained.

(24) In the method according to the embodiment of the disclosure, the absolute value of the second current I2 is equal to the absolute value of the first current I1. In the method according to other embodiments, the absolute value of the second current I2 may be greater than or smaller than the absolute value of the first current I1.

(25) In step 4, a difference value obtained by subtracting the second voltage Vx2 from the first voltage Vx1 is divided by a difference value between the first current I1 and the second current I2 to obtain the final test value of the tested resistor Rx.

(26) The first error value and the second error value are opposite in positivity and negativity, and are set off in step 4, such that the error value of the final test value of the tested resistor Rx is reduced or eliminated.

(27) From FIG. 4, it can be seen that, since the offset voltage Voffset remains unchanged, the curve corresponding to the final test value obtained by averaging the first test value and the second test value is the curve formed by connecting curve 202 and curve 204. Referring to FIG. 4, it can be seen that curve 204 is an extension line of curve 202. Obviously, curve 202 is a curve corresponding to the final test value, so the final test value is no longer the test value corresponding to the ideal state when the offset voltage Voffset is 0V, but reflects the offset voltage Voffset and the true value formed after the influence of the offset voltage Voffset is removed.

(28) In the method according to the embodiment of the disclosure, a resistance test using the Kelvin structure is realized in a wafer acceptance test.

(29) The two voltage test terminals are formed with pads and the two current test terminals are formed with pads.

(30) Each pad is connected with probes on a probe card of a wafer acceptance tester.

(31) The first parasitic resistor Rc1 is a parasitic resistor from the first end 3 of the tested resistor Rx to the current applying end of the wafer acceptance tester.

(32) The second parasitic resistor Rc2 is a parasitic resistor from the second end 4 of the tested resistor Rx to the current applying end of the wafer acceptance tester.

(33) A source of the first error value and the second error value includes an error caused by offset voltage formed by conducting wires and a probe card in a test loop.

(34) The source of the first error value and the second error value further includes an error caused by offset voltage corresponding to voltage drift formed at the two voltage test terminals by transient voltage produced when a relay in the wafer acceptance tester is on and off in the test process.

(35) The order of magnitude of the first error value and the second error value is equivalent to the order of magnitude of the final test value.

(36) All of the pads are formed by a front metal layer.

(37) Under the condition of keeping the Kelvin test structure unchanged, the embodiment of the disclosure combines the current in the positive and negative directions to test, and takes the average value of the resistance values formed by the two tests as the final test value of the tested resistor Rx. Since the offset voltage of the two test voltages formed by the test can set off each other, the resistance test error can be reduced to make the test result close to the true value.

(38) The disclosure has been described above in detail through the specific embodiments, which, however, do not constitute restrictions on the disclosure. Without departing from the principle of the disclosure, those skilled in the art may also make many modifications and improvements, which should also be regarded as included the protection scope of the disclosure.