DISTORTION COMPENSATION APPARATUS AND DISTORTION COMPENSATION METHOD

Abstract

A DPD (1) includes: a polynomial structure including a pseudo-interpolation/sub-sample-shift processing unit (101) configured to operate at a sampling rate for sampling an input signal not upsampled in a previous stage of the DPD (1), pseudo-interpolate a sample point between sample points of the input signal, and shift the pseudo-interpolated sample point by a sub-sample and a multiplexer (109) configured to select a combination of a sub-sample shift amount; and an FIR filter (107) configured to be provided in a subsequent stage of the polynomial structure and include a sub-sample delay filter delaying a sample point of the input signal by a sub-sample. The DPD (1) compensates for distortion due to a sample point of the input signal and compensates for distortion due to a sub-sample point between sample points of the input signal for the DPD (1), by using the polynomial structure and the FIR filter (107).

Claims

1. A distortion compensation apparatus configured to compensate for non-linear distortion of a power amplifier, the distortion compensation apparatus comprising: an AD converter configured to feed back and analog/digital (AD) convert an output signal of the power amplifier and output the AD converted signal as a feedback signal; a digital predistorter configured to perform distortion compensation processing on an input signal by using the feedback signal and output the signal undergoing distortion compensation processing; and a DA converter configured to be provided between the digital predistorter and the power amplifier, digital/analog (DA) convert an output signal of the digital predistorter, and output the DA converted signal to the power amplifier, wherein the digital predistorter operates at a sampling rate for sampling the input signal not upsampled in a previous stage of the digital predistorter, includes: a polynomial structure configured to include a pseudo-interpolation/sub-sample-shift processing unit configured to pseudo-interpolate a sample point between sample points of the input signal and shift the pseudo-interpolated sample point by a sub-sample and include a multiplexer configured to select a combination of a sub-sample shift amount in complex-multiplication of a signal itself acquired by processing the input signal by the pseudo-interpolation/sub-sample-shift processing unit by an output of a look up table related to an amplitude address corresponding to an amplitude of a signal acquired by processing the input signal by the pseudo-interpolation/sub-sample-shift processing unit; and a finite impulse response (FIR) filter configured to be provided in a subsequent stage of the polynomial structure and include a sub-sample delay filter delaying a sample point of the input signal by a sub-sample, and compensates for distortion due to a sample point of the input signal and compensates for distortion due to a sub-sample point between sample points of the input signal for the digital predistorter, by using the polynomial structure and the FIR filter.

2. The distortion compensation apparatus according to claim 1, wherein the digital predistorter includes: a plurality of the FIR filters; and a first adder configured to add and output respective output signals of a plurality of the FIR filters and has a configuration in which a plurality of first paths of the polynomial structure are branched in parallel from an input stage of the digital predistorter, a plurality of the FIR filters are placed in a subsequent stage of a plurality of the first path, respectively, and the first adder is placed in a subsequent stage of a plurality of the FIR filters, and the pseudo-interpolation/sub-sample-shift processing unit is placed in the first path.

3. The distortion compensation apparatus according to claim 2, wherein a plurality of the first paths include: the first path in which the pseudo-interpolation/sub-sample-shift processing unit is placed; and the first path in which the pseudo-interpolation/sub-sample-shift processing unit is not placed.

4. The distortion compensation apparatus according to claim 3, wherein the pseudo-interpolation/sub-sample-shift processing unit is a filter with a fixed tap coefficient, and a first delay device with an amount of delay determined by the number of taps of the pseudo-interpolation/sub-sample-shift processing unit is placed in the first path in which the pseudo-interpolation/sub-sample-shift processing unit is not placed.

5. The distortion compensation apparatus according to claim 4, wherein the multiplexer selects a signal to be complex-multiplied by an output of the look up table from either of an output of the pseudo-interpolation/sub-sample-shift processing unit in a plurality of the first paths and an output of the first delay device.

6. A distortion compensation method by a distortion compensation apparatus configured to compensate for non-linear distortion of a power amplifier, the distortion compensation method comprising: in a digital predistorter, performing distortion compensation processing on an input signal by using a feedback signal acquired by feeding back and analog/digital (AD) converting an output signal of the power amplifier, and outputting the signal undergoing distortion compensation processing; and digital/analog (DA) converting an output signal of the digital predistorter and outputting the DA converted signal to the power amplifier, wherein the digital predistorter operates at a sampling rate for sampling the input signal not upsampled in a previous stage of the digital predistorter, includes: a polynomial structure configured to include a pseudo-interpolation/sub-sample-shift processing unit configured to pseudo-interpolate a sample point between sample points of the input signal and shift the pseudo-interpolated sample point by a sub-sample and include a multiplexer configured to select a combination of a sub-sample shift amount in complex-multiplication of a signal itself acquired by processing the input signal by the pseudo-interpolation/sub-sample-shift processing unit by an output of a look up table related to an amplitude address corresponding to an amplitude of a signal acquired by processing the input signal by the pseudo-interpolation/sub-sample-shift processing unit; and a finite impulse response (FIR) filter configured to be provided in a subsequent stage of the polynomial structure and include a sub-sample delay filter delaying a sample point of the input signal by a sub-sample, and compensates for distortion due to a sample point of the input signal and compensates for distortion due to a sub-sample point between sample points of the input signal for the digital predistorter, by using the polynomial structure and the FIR filter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0215] FIG. 1A is a block diagram illustrating a configuration example of a DPD according to an example embodiment of the present disclosure.

[0216] FIG. 1B is a block diagram illustrating a configuration example of an FIR filter in the DPD according to the example embodiment of the present disclosure.

[0217] FIG. 2 is a block diagram illustrating a configuration example of a distortion compensation apparatus according to a related art.

[0218] FIG. 3 is a block diagram illustrating a functional example of an interpolation DA converter.

[0219] FIG. 4 is a block diagram illustrating a configuration example of a DPD in the distortion compensation apparatus according to the related art illustrated in FIG. 2.

[0220] FIG. 5 is a block diagram illustrating a configuration example of a DPD acquired by applying a measure for reducing the number of coefficients to the DPD according to the related art illustrated in FIG. 4.

[0221] FIG. 6 is a block diagram illustrating a configuration example of a distortion compensation apparatus in which an interpolation circuit is deleted and DPD upsampling is not performed.

[0222] FIG. 7 is a diagram illustrating a comparison example between amplitude changes of a signal in an 800 MHz bandwidth at a sampling frequency of 983.04 MHz before interpolation and amplitude changes of a signal acquired by twofold-upsampling the signal at a sampling frequency of 1.96608 GHz by twofold interpolation processing.

[0223] FIG. 8 is a diagram illustrating a comparison example between amplitude changes of a signal twofold-upsampled at a sampling frequency of 1.96608 GHz by twofold interpolation processing and amplitude changes of a signal acquired by further fourfold-upsampling the signal at a sampling frequency of 3.93216 GHz by twofold interpolation processing.

[0224] FIG. 9 is a block diagram illustrating a configuration example of a DPD disclosed in Patent Literature 3.

[0225] FIG. 10 is a diagram illustrating an example of tap coefficients of a twofold-interpolation half-band FIR filter incorporated in an interpolation DA converter.

[0226] FIG. 11 is a timing chart illustrating an example of twofold interpolation processing in the interpolation DA converter.

[0227] FIG. 12 is a diagram illustrating an example of a procedure for acquiring tap coefficients of a pseudo-interpolation filter for acquiring sub-sample memory taps=±0.5 for a DPD operating at a non-upsampled sampling rate.

[0228] FIG. 13A is a diagram illustrating an example of an impulse response of a 0.5-sample delay filter in a case of a delay being a non-integer relative to a sample.

[0229] FIG. 13B is a diagram illustrating an example of a frequency characteristic of an amount of filter attenuation for the number of taps when a 0.5-sample delay filter is configured with an FIR filter.

DESCRIPTION OF EMBODIMENTS

[0230] An example embodiment of the present disclosure is described below with reference to drawings.

Configuration of Example Embodiment

[0231] FIG. 1A and FIG. 1B illustrate block diagrams of a configuration example of a DPD 1 according to the present example embodiment. FIG. 1A illustrates a configuration example of the DPD 1 according to the present example embodiment, and FIG. 1B illustrates a configuration example of an FIR filter.sub.0 107a, an FIR filter.sub.1 107b, and an FIR filter.sub.2 107c in the DPD 1 according to the present example embodiment.

[0232] The DPD 1 according to the present example embodiment illustrated in FIG. 1A and FIG. 1B includes a multiplexer.sub.0 109a, a multiplexer.sub.1 109b, and a multiplexer.sub.2 109c in addition to the DPD 1 according to Patent Literature 3 illustrated in FIG. 9.

[0233] The multiplexer.sub.0 109a is a multiplexer that can select a signal to be complex-multiplied by an output of a LUT 105a by a complex multiplier 106a in a path related to a memory tap l.sub.s=0, that is, a path in which the pseudo-interpolation/sub-sample-shift filter 101a, an amplitude address calculation circuit 104a, and the LUT 105a are placed from among an output of a pseudo-interpolation/sub-sample-shift filter 101a, an output of an i/2-sample delay device 102, and an output of a pseudo-interpolation/sub-sample-shift filter 101b.

[0234] The multiplexer.sub.1 109b is a multiplexer that can select a signal to be complex-multiplied by an output of a LUT 105b by a complex multiplier 106b in a path related to a memory tap l.sub.s=1, that is, a path in which the i/2-sample delay device 102, an amplitude address calculation circuit 104b, and the LUT 105b are placed from among the output of the pseudo-interpolation/sub-sample-shift filter 101a, the output of the i/2-sample delay device 102, and the output of the pseudo-interpolation/sub-sample-shift filter 101b.

[0235] The multiplexer.sub.2 109c is a multiplexer that can select a signal to be complex-multiplied by an output of a LUT 105c by a complex multiplier 106c in a path related to a memory tap l.sub.s=2, that is, a path in which the pseudo-interpolation/sub-sample-shift filter 101b, an amplitude address calculation circuit 104c, and the LUT 105c are placed from among the output of the pseudo-interpolation/sub-sample-shift filter 101a, the output of the i/2-sample delay device 102, and the output of the pseudo-interpolation/sub-sample-shift filter 101b.

[0236] A multiplexer is generally a circuit mechanism selecting or aggregating two or more inputs and outputting one resulting signal. Each of the multiplexer.sub.0 109a, the multiplexer.sub.1 109b, and the multiplexer.sub.2 109c according to the present disclosure is a multiplexer as a data selector and, for example, includes three lines of data inputs and one line of a data output. Each of the multiplexer.sub.0 109a, the multiplexer.sub.1 109b, and the multiplexer.sub.2 109c selects one line from among the three lines of input signals and set the selected one line as an output signal in accordance with each of selection control signals SEL.sub.0, SEL.sub.1, and SEL.sub.2.

[0237] In a path related to a memory tap l.sub.s(l.sub.s=0, 1, or 2), a memory tap of, in sampling after twofold interpolation, a signal selected by a multiplexer for each path from among the output of the pseudo-interpolation/sub-sample-shift filter 101a, the output of the i/2-sample delay device 102, and the output of the pseudo-interpolation/sub-sample-shift filter 101b, is expressed as m.sub.ls.

[0238] Specifically, the memory tap of a signal output selected by the multiplexer.sub.0 109a for the path related to l.sub.s=0 is m.sub.ls=m.sub.0. The memory tap of a signal output selected by the multiplexer.sub.1 109b for the path related to l.sub.s=1 is m.sub.ls=m.sub.l. The memory tap of a signal output selected by the multiplexer.sub.2 109c for the path related to l.sub.s=2 is m.sub.ls=m.sub.2. One of 0, 1, and 2 is selected as m.sub.ls in the example in FIG. 1A and FIG. 1B.

Operation of Example Embodiment

[0239] In the configuration according to the present example embodiment, based on LUT amplitude addresses for signals corresponding to delaying in steps of one sample in sampling after twofold interpolation, the LUTs 105a, 105b, and 105c are referred to, and output signals of the LUTs 105a, 105b, and 105c related to the LUT amplitude addresses, respectively, are acquired. Then, the complex multipliers 106a, 106b, and 106c complex-multiply the output signals of the LUTs by signals corresponding to delaying in steps of one sample in sampling after twofold interpolation, respectively. The result of complex-multiplication by the complex multipliers 106a, 106b, and 106c in the DPD 1 according to the present example embodiment, that is, an output for each term of the memory tap l.sub.s in a polynomial structure is as follows.

[00046] $x (n - \frac{i}{2} + \frac{1 - m_{l_{s}}}{2}) .Math. K_{l_{s}} (.Math. x (n - \frac{i}{2} + \frac{1 - l_{s}}{2}) .Math.)$

The memory tap m.sub.ls (m.sub.ls=0, 1, or 2) in the path related to the memory tap l.sub.s (l.sub.s=0, 1, or 2) can be selected by the multiplexer.sub.0 109a for the path related to l.sub.s=0, the multiplexer.sub.1 109b for the path related to l.sub.s=1, or the multiplexer.sub.2 109c for the path related to l.sub.s=2.

[0240] The results of complex-multiplication by the complex multipliers 106a, 106b, and 106c are input to the FIR filter.sub.0 107a, the FIR filter.sub.1 107b, and the FIR filter.sub.2 107c, respectively, as a polynomial

[00047] $x (n - \frac{i}{2} + \frac{1 - m_{l_{s}}}{2}) .Math. K_{l_{s}} (.Math. x (n - \frac{i}{2} + \frac{1 - l_{s}}{2}) .Math.)$

for each term of the memory tap l.sub.s=0, 1, or 2 in sampling after twofold interpolation. The FIR filter.sub.0 107a is related to the memory tap l.sub.s=0 in sampling after twofold interpolation. The FIR filter.sub.1 107b is related to the memory tap l.sub.s=1 in sampling after twofold interpolation. The FIR filter.sub.2 107c is related to the memory tap l.sub.s=2 in sampling after twofold interpolation.

[0241] From an input signal

[00048] $x (n - \frac{i}{2} + \frac{1 - m_{l_{s}}}{2}) .Math. K_{l_{s}} (.Math. x (n - \frac{i}{2} + \frac{1 - l_{s}}{2}) .Math.),$

each of the FIR filter.sub.0 107a, the FIR filter.sub.1 107b, and the FIR filter.sub.2 107c outputs signals described below related to FIR taps r.sub.s=0, 1, 2, 3, and 4, respectively, in sampling after twofold interpolation.

[0242] At the FIR tap r.sub.s=0,

[00049] $x (n - \frac{i}{2} + \frac{1 - m_{l_{s}}}{2} - \frac{j}{2} + 1) .Math. K_{l_{s}} (.Math. x (n - \frac{i}{2} + \frac{1 - l_{s}}{2} - \frac{j}{2} + 1) .Math.)$

corresponding to a signal delayed by (j-2) samples by a (j/2-1)-sample delay device 112 in sampling after twofold interpolation is output.

[0243] At the FIR tap r.sub.s=1,

[00050] $x (n - \frac{i}{2} + \frac{1 - m_{l_{s}}}{2} - \frac{j}{2} + \frac{1}{2}) .Math. K_{l_{s}} (.Math. x (n - \frac{i}{2} + \frac{1 - l_{s}}{2} - \frac{j}{2} + \frac{1}{2}) .Math.)$

corresponding to a signal delayed by (j−1) samples by a sub-sample delay filter 111 configured with a j-tap FIR filter in sampling after twofold interpolation is output.

[0244] At the FIR tap r.sub.s=2,

[00051] $x (n - \frac{i}{2} + \frac{1 - m_{l_{s}}}{2} - \frac{j}{2}) .Math. K_{l_{s}} (.Math. x (n - \frac{i}{2} + \frac{1 - l_{s}}{2} - \frac{j}{2}) .Math.)$

corresponding to a signal delayed by j samples by a 1-sample delay device 113a in a subsequent stage of the (j/2−1)-sample delay device 112 in sampling after twofold interpolation is output.

[0245] At the FIR tap r.sub.s=3,

[00052] $x (n - \frac{i}{2} + \frac{1 - m_{l_{s}}}{2} - \frac{j}{2} - \frac{1}{2}) .Math. K_{l_{s}} (.Math. x (n - \frac{i}{2} + \frac{1 - l_{s}}{2} - \frac{j}{2} - \frac{1}{2}) .Math.)$

corresponding to a signal delayed by (j+1) samples by a 1-sample delay device 113c in a subsequent stage of the sub-sample delay filter 111 in sampling after twofold interpolation is output.

[0246] At the FIR tap r.sub.s=4,

[00053] $x (n - \frac{i}{2} + \frac{1 - m_{l_{s}}}{2} - \frac{j}{2} - 1) .Math. K_{l_{s}} (.Math. x (n - \frac{i}{2} + \frac{1 - l_{s}}{2} - \frac{j}{2} - 1) .Math.)$

corresponding to a signal delayed by (j+2) samples by a 1-sample delay device 113b in a subsequent stage of the 1-sample delay device 113a in sampling after twofold interpolation is output.

[0247] A generalized expression of the output from each of the aforementioned five taps in the FIR.sub.ls related to each memory tap l.sub.s with the memory tap l.sub.s(=0, 1, or 2) and the FIR tap r.sub.s (=0, 1, 2, 3, or 4) as variables is as follows.

[00054] $x (n + \frac{3 - i - j - m_{l_{s}} - r_{s}}{2}) .Math. K_{l_{s}} (.Math. x (n + \frac{3 - i - j - l_{s} - r_{s}}{2}) .Math.)$

[0248] In other words, the output signal of each FIR tap r.sub.s corresponding to delaying in steps of one sample in the aforementioned sampling after twofold interpolation is expressed as follows.

[00055] $x (n + \frac{3 - i - j - m_{l_{s}} - r_{s}}{2}) .Math. K_{l_{s}} (.Math. x (n + \frac{3 - i - j - l_{s} - r_{s}}{2}) .Math.)$

[0249] Each of the complex multipliers 114a, 114d, 114b, 114e, and 114c complex-multiplies the output signal of the related FIR tap r.sup.s by a filter (complex) coefficient W.sub.ls,0, W.sub.ls,1, W.sub.ls,2, W.sub.ls,3, or W.sub.ls,4 related to the FIR tap r.sub.s=0, 1, 2, 3, or 4. Subsequently, the signals respectively complex-multiplied by the complex multipliers 114a, 114d, 114b, 114e, 114c are added by an adder 115. The signal added by the adder 115 is output from each of the FIR filter.sub.0 107a, the FIR filter.sub.1 107b, and the FIR filter.sub.2 107c as

[00056] ${.Math.}_{r_{s} = 0}^{4} W_{l_{s}, r_{s}} .Math. x (n + \frac{3 - i - j - m_{l_{s}} - r_{s}}{2}) .Math. K_{l_{s}} (.Math. x (n + \frac{3 - i - j - l_{s} - r_{s}}{2}) .Math.)$

for each memory tap l.sub.s.

[0250] At this time, the output signal of the FIR filter.sub.0 107a related to the memory tap l.sub.s=0 is as follows.

[00057] ${.Math.}_{r_{s} = 0}^{4} W_{0, r_{s}} .Math. x (n + \frac{3 - i - j - m_{0} - r_{s}}{2}) .Math. K_{0} (.Math. x (n + \frac{3 - i - j - r_{s}}{2}) .Math.)$

[0251] The output signal of the FIR filter.sub.1 107b related to the memory tap l.sub.s=1 is as follows.

[00058] ${.Math.}_{r_{s} = 0}^{4} W_{1, r_{s}} .Math. x (n + \frac{3 - i - j - m_{1} - r_{s}}{2}) .Math. K_{1} (.Math. x (n + \frac{2 - i - j - r_{s}}{2}) .Math.)$

[0252] The output signal of the FIR filter.sub.2 107c related to the, memory tap l.sub.s=2 is as follows.

[00059] ${.Math.}_{r_{s} = 0}^{4} W_{2, r_{s}} .Math. x (n + \frac{3 - i - j - m_{2} - r_{s}}{2}) .Math. K_{2} (.Math. x (n + \frac{1 - i - j - r_{s}}{2}) .Math.)$

[0253] The output signals of the FIR filter.sub.0 107a, the FIR filter.sub.1 107b, and the FIR filter.sub.2 107c are eventually added by an adder 108. The result of the addition by the adder 108 corresponds to the equation (20) in the DPD 1 according to Patent Literature 3 illustrated in FIG. 9 and is output from the DPD 1 as a polynomial with a reduced number of coefficients expressed by the following equation (23) in the DPD 1 according to the present example embodiment.

[00060] $\begin{matrix} y (n - \frac{i}{2} - \frac{j}{2}) = {.Math.}_{l_{s} = 0}^{2} {.Math.}_{r_{s} = 0}^{4} W_{l_{s}, r_{s}} .Math. x (n + \frac{3 - i - j - m_{l_{s}} - r_{s}}{2}) .Math. & (23) \end{matrix}$ $K_{l_{s}} (.Math. x (n + \frac{3 - i - j - l_{s} - r_{s}}{2}) .Math.)$

[0254] As described above, the DPD 1 according to the present example embodiment can freely select a value of a memory tap m.sub.ls (m.sub.ls=0, 1, or 2) being identical to or different from a value of is for a path related to a memory tap l.sub.s (l.sub.s=0, 1, or 2) by a polynomial structure including a multiplexer selecting a combination of sub-sample shift amounts and selection control on the multiplexer.

[0255] Accordingly, while being a distortion compensation apparatus not performing DPD upsampling processing in a previous stage of the DPD 1 and operating at a low sampling rate, the distortion compensation apparatus according to the present example embodiment can reduce an amount of coefficient calculation and can reduce the operating frequency of the DPD 1 and the sampling rates of the DA converter 2 and the AD converter 7, compared with the upsampling distortion compensation apparatus according to the related art. Furthermore, in compensation for a memory effect within a carrier band due to a sub-sample memory tap between sample points in the DPD 1, a degree of freedom can be given to a combination of complex-multiplication configurations based on cross terms with different memory taps (=sub-sample shift amounts) by a polynomial structure including a multiplexer selecting a combination of sub-sample shift amounts and selection control on the multiplexer, without increasing the number of coefficients and with a small amount of circuit addition. Therefore, a power amplifier model optimum for distortion compensation can be constructed, and target compensation performance can be achieved.

[0256] While various aspects of the present disclosure have been described above with reference to the example embodiments, the present disclosure is not limited to the aforementioned example embodiments. Various changes and modifications in each aspect of the present disclosure that may be understood by a person skilled in the art may be made to the configurations and details of the present invention within the scope of the present invention.

[0257] For example, the number of memory taps l.sub.s and m.sub.ls, and the number of FIR taps r.sub.s indicated in the aforementioned example embodiment are examples and are not restrictive. For example, while the number of memory taps l.sub.s and m.sub.ls are set to 3, and the number of FIR taps r.sub.s is set to 5 as an example of approximating a seventh-order memory polynomial model in the aforementioned example embodiment, the seventh-order memory polynomial model may be approximated by setting the number of memory taps l.sub.s and m.sub.ls to 5 and the number of FIR taps r.sub.s to 3. Further, permitting increase in the circuit size and the amount of coefficient calculation, the aforementioned number of taps may be increased.

[0258] This application claims priority based on Japanese Patent Application No. 2020-083960 filed on May 12, 2020, the disclosure of which is hereby incorporated by reference thereto in its entirety.

REFERENCE SIGNS LIST

[0259] 1 DIGITAL PREDISTORTER (DPD) [0260] 2 DIGITAL/ANALOG (DA) CONVERTER [0261] 3 TRANSMISSION UPCONVERTER [0262] 4 POWER AMPLIFIER [0263] 5 DIRECTIONAL COUPLER [0264] 6 FEEDBACK DOWNCONVERTER [0265] 7 ANALOG/DIGITAL (AD) CONVERTER [0266] 101a, 101b PSEUDO-INTERPOLATION/SUB-SAMPLE-SHIFT FILTER [0267] 102 i/2-SAMPLE DELAY DEVICE [0268] 103 1-SAMPLE DELAY DEVICE [0269] 104a, 104b, 104c AMPLITUDE ADDRESS CALCULATION CIRCUIT [0270] 105a, 105b, 105c LOOK UP TABLE (LUT) [0271] 106a, 106b, 106c COMPLEX MULTIPLIER [0272] 107a FIR FILTER.sub.0 [0273] 107b FIR FILTER.sub.1 [0274] 107c FIR FILTER.sub.2 [0275] 108 ADDER [0276] 109a MULTIPLEXER.sub.0 [0277] 109b MULTIPLEXER.sub.1 [0278] 109c MULTIPLEXER.sub.2 [0279] 111 SUB-SAMPLE DELAY FILTER [0280] 112 (j/2−1)-SAMPLE DELAY DEVICE [0281] 113a, 113b, 113c 1-SAMPLE DELAY DEVICE [0282] 114a, 114b, 114c, 114d, 114e COMPLEX MULTIPLIER [0283] 115 ADDER [0284] 201, 202 HALF-BAND FILTER.sub.1 [0285] 203, 204 HALF-BAND FILTER.sub.2 [0286] 205 NUMERICAL CONTROLLED OSCILLATOR (NCO) [0287] 206, 207 COMPLEX MULTIPLIER [0288] 208 ADDER [0289] 209 DA CONVERSION UNIT

DISTORTION COMPENSATION APPARATUS AND DISTORTION COMPENSATION METHOD

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H04B1/0483

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Abstract

Claims

Description