Error unbiased approximate multiplier for normalized floating-point numbers and implementation method of error unbiased approximate multiplier

Abstract

The present invention discloses an error unbiased approximate multiplier for normalized floating-point numbers and an implementation method of the error unbiased approximate multiplier. The error unbiased approximate multiplier includes a symbol and exponent bit module, a mantissa approximation module and a normalization module, wherein the symbol and exponent bit module processes symbolic operation and exponent bit operation of the floating-point numbers; the mantissa approximation module obtains a mantissa approximation result under different accuracy requirements by summing a result of multilevel error correction modules; and the normalization module adjusts an exponent bit according to the operation result of the mantissa and processes the overflow of the exponent bit to obtain the final product result. According to the present invention, for the multiply operation of the normalized floating-point numbers under the IEEE 754 standard, under the controllable accuracy levels, error distribution is unbiased, and area, speed and energy efficiency are obviously improved.

Claims

1. An error unbiased approximate multiplier for normalized floating-point numbers for image processing or machine learning, the error unbiased approximate multiplier comprising a processor, wherein the processor is configured to: perform Exclusive OR operation on symbol bits of the normalized floating-point numbers to obtain a current symbol bit; perform add operation on exponent bits of the normalized floating-point numbers and subtraction of an offset 2.sup.n−1 to obtain a current exponent bit, where n is a bit number of the exponent bits; generate an enable signal to enable a 0-level approximation circuit; generate at least one further enable signal to enable at least one error correction circuit of a plurality of multilevel error correction circuits; wherein the 0-level approximation circuit and the plurality of multilevel error correction circuits take the mantissas of the floating-point numbers as input and operate independently from one another in parallel; wherein the 0-level approximation circuit is configured to generate a basic approximate mantissa multiplication result, i.e. a.sub.0=1.5×(X+Y)−2.25, where X and Y are actual values of mantissa bits of the normalized floating-point numbers and are in a range of [1,2); wherein the plurality of multilevel error correction circuits are configured to perform at least one error correction in progressive by using the at least one further enable signal to obtain at least one error correction output result, wherein each of the at least one error correction is summation of the mantissa bits shifted and a constant, i.e. a.sub.i=±(X>>A)±(Y>>B)+C, where a.sub.i is a i-th error correction output result of the at least one error correction output result, A and B are right shift numbers, and C is an offset value of the normalized floating-point numbers; perform summation of the basic approximate mantissa multiplication result and the at least one error correction output result to obtain an approximate mantissa product result; adjust the approximate mantissa product result for normalization to obtain a to-be-output mantissa result in the range of [1,2) and adjust the current exponent bit correspondingly at the same time to obtain a to-be-output exponent result; perform overflow judgment on the to-be-output exponent result to obtain a final result; wherein the final result is assigned to be infinity under the IEEE 754 standard if the to-be-output exponent result overflows upwards, and the final result is assigned to be 0 under the IEEE 754 standard if the to-be-output exponent result overflows downwards; and output the final result if overflow does not occur on the to-be-output exponent result, wherein the current symbol bit, the to-be-output exponent result and the to-be-output mantissa result serve as the final result.

2. The error unbiased approximate multiplier for the normalized floating-point numbers according to claim 1, wherein the subtraction of the offset 2.sup.n−1 from the exponent bits is specifically as follows: n=8 for the normalized floating-point numbers are 32-bit under the IEEE 754 standard; and n=11 for the normalized floating-point numbers are 64-bit.

3. The error unbiased approximate multiplier for the normalized floating-point numbers according to claim 1, wherein the processor is further configured to adjust an approximate accuracy in the computing process by using different numbers of the at least one enable signal.

4. The error unbiased approximate multiplier for the normalized floating-point numbers according to claim 1, wherein the processor is further configured to perform bit extension toward on the highest two bits of the current exponent bit to obtain the to-be-output exponent result for the overflow judgment; wherein in case of upward overflow, the highest two bits of the to-be-output exponent result are 01, and at this time, z.sub.e−(2.sup.n−1)>(2.sup.n−1), the final result is too large to express, such that plus or minus infinity, where z.sub.e representing the to-be-output exponent result; in case of downward overflow, the highest two bits of the to-be-output exponent result are 11, and at this time, z.sub.e−(2.sup.n−1)<0, the final result is too small to express, such that plus or minus 0; and in case of no overflow, the highest two bits of the to-be-output exponent result are 00.

5. The error unbiased approximate multiplier for the normalized floating-point numbers according to claim 1, wherein the processor is further configured to: complement the mantissa bits by 1 to obtain the actual values of the mantissa bits in the range of [1,2), and perform bit extension on the highest bit by complementing by 0, such that a express range of the mantissa bits is [0,4); perform a linear processing method on the mantissa bits; and determine the symbols, the right shift numbers and the offset value in the at least one error correction by a number of the at least one enable signal and a range of the mantissa bits.

6. The error unbiased approximate multiplier for the normalized floating-point numbers according to claim 1, wherein the processor is further configured to: perform square division on an interval of the mantissa bits such that divide the range [1,2) of the mantissa bits into 2.sup.k equal intervals in a k-th of the at least one error correction; and judge the interval of the mantissa bits by the previous k bits of the mantissa bits; wherein the interval division of the mantissas bits are independent of each other, such that an interval [1,2)×[1,2) of two mantissa bits are divided into 4.sup.k identical squares; meanwhile, all of the at least one error correction are independent of each other.

7. The error unbiased approximate multiplier for the normalized floating-point numbers according to claim 6, wherein the processor is further configured to perform a linearized approximation method on the mantissa bits to obtain a lowest mean square error result and an error unbiased distribution in the square division according to a minimization problem principle in linear algebra.

8. The error unbiased approximate multiplier for the normalized floating-point numbers according to claim 1, wherein in the normalization, the processor is further configured to: adjust the approximate mantissa product result in the range of [1,2) by multiplying by 2, dividing by 2 or not processing; shift the approximate mantissa product result to right to obtain the to-be-output mantissa result and subtract the current exponent bit by 1 to obtain the to-be-output exponent result when the approximate mantissa product result is greater than or equal to 2; shift the approximate mantissa product result to left to obtain the to-be-output mantissa result and add the current exponent bit by 1 to obtain the to-be-output exponent result when the approximate mantissa product result is less than 1; serve the approximate mantissa product result as the to-be-output mantissa result and serve the current exponent bit as the to-be-output exponent result when the approximate mantissa product result is in the range of [1,2).

9. The error unbiased approximate multiplier for the normalized floating-point numbers according to claim 1, wherein when the highest two bits of the to-be-output exponent result are 01, it indicates that upward overflow occurs and the final result is assigned to be infinity under the IEEE 754 standard, such that exponent bits of the final result are all 1 and mantissa bits of the final result are all 0; when the highest two bits of the to-be-output exponent result are 11, it indicates that downward overflow occurs and the final result is assigned to be zero under the IEEE 754 standard, such that the exponent bits of the final result and the mantissa bits of the final result are all 0; and when the highest two bits of the to-be-output exponent are 00, it indicates that overflow does not occur, and the current symbol bi, the to-be-output exponent result with the highest two bits removed, and the to-be-output mantissa result with the highest two bits removed serves as the final result.

10. A method for implementing an error unbiased approximate multiplier for normalized floating-point numbers for image processing or machine learning, the error unbiased approximate multiplier comprising a processor including a 0-level approximation circuit and a plurality of multilevel error correction circuits, the method comprising: performing Exclusive OR operation on symbol bits of the normalized floating-point numbers to obtain a current symbol bit, extending the highest two bits of exponent bits of the normalized floating-point numbers, performing add operation on the exponent bit and subtraction of an offset 2.sup.n−1 to obtain a current exponent bit; generating, by the processor, an enable signal to enable a 0-level approximation circuit and at least one further enable signal to enable at least one error correction circuit of a plurality of multilevel error correction circuits; generating, by the 0-level approximation circuit, a basic approximate mantissa multiplication result a.sub.0=1.5×(X+Y)−2.25; generating, by the plurality of multilevel error correction circuits, at least one error correction output result a.sub.i=±(X>>A)±(Y>>B)+C by using the at least one further enable signal, wherein the 0-level approximation circuit and the plurality of multilevel error correction circuits take the mantissas of the floating-point numbers as input and operate independently from one another in parallel; and performing, by the processor, summation of the basic approximate mantissa multiplication result and the at least one of error correction output result to obtain an approximate mantissa product result; where X and Y are actual values of mantissa bits of the normalized floating-point numbers, A and B are right shift numbers, and C is an offset value of the normalized floating-point numbers; adjusting, by the processor, the current exponent bit and the approximate mantissa product result in a range of [1,2) by multiplying the approximate mantissa product result by 2, dividing by 2 or not processing; when the approximate mantissa product result is divided by 2, adding the current exponent bit by 1; when the approximate mantissa product result is multiplied by 2, subtracting the current exponent bit by 1; when the approximate mantissa product result and the current exponent bit are not processed, serving the approximate mantissa product result as a to-be-output mantissa result and serving the current exponent bit as a to-be-output exponent result; and performing, by the processor, overflow judgment on the highest two bits of the to-be-output exponent result; wherein when the highest two bits are 01, it indicates that upward overflow occurs and a final result is assigned to be infinity under the IEEE 754 standard; when the highest two bits are 11, it indicates that downward overflow occurs and the final result is assigned to be 0 under the IEEE 754 standard; and when the highest two bits are 00, it indicates that overflow does not occur and the current symbol bit, the to-be-output exponent result with the highest two bits removed, and the to-be-output mantissa result with the highest two bits removed serve as the final result.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 shows a schematic diagram of an overall architecture of an error unbiased approximate multiplier for normalized floating-point numbers according to the present invention, including three modules: a) a symbol and exponent bit module; b) a mantissa approximation module; and c) a normalization module;

(2) FIG. 2 shows structural difference of an approximate multiplier according to the present invention and ApproxLP at a mantissa approximate part, wherein a) is a structural diagram of a mantissa approximation module of the ApproxLP; and b) is a structural diagram of a mantissa approximation module of the approximate multiplier according to the present invention; and

(3) FIG. 3 shows a schematic diagram of mean square error MSE, mean absolute error MAE and maximum error Max Error of an approximate multiplier according to the present invention under different approximate levels for the input of the uniformly distributed random floating-point numbers.

DETAILED DESCRIPTION OF EMBODIMENTS

(4) The present invention will be further described in detail with reference to the accompanying drawings and the specific embodiments.

(5) As shown in FIG. 1, the present invention provides an error unbiased approximate multiplier for normalized floating-point numbers, including the following modules:

(6) (1) A symbol and exponent bit module, configured to: perform Exclusive OR processing on symbol bits of the input normalized floating-point numbers:
z.sub.s=x.sub.s⊕y.sub.s

(7) x.sub.s and y.sub.s respectively represent symbol bits of the input two multipliers, and z.sub.s is the result of Exclusive OR operation on the symbol bits.

(8) The input exponent bits are subjected to sum operation and an offset is subtracted to acquire the exponent result t.sub.e of the symbol bits and the exponent bits:
t.sub.e=x.sub.e+y.sub.e−(2.sup.n−1)

(9) x.sub.e and y.sub.e respective represent the input exponent bits of the two multipliers and the result is extended to n+2 bits for overflow judgment: when upward overflow occurs, that is, x.sub.e+y.sub.e−(2.sup.n−1)>(2.sup.n−1), the highest two bits are 01; and if downward overflow occurs, that is, x.sub.e+y.sub.e−(2.sup.n−1)<0, the highest two bits are 11, wherein n is the bit number of the exponent bit; for the 32-bit floating-point number under the IEEE 754 standard, n=8; and for the 64-bit floating-point number under the IEEE 754 standard, n=11.

(10) (2) The mantissa approximation module includes a 0-level approximation module and multilevel error correction modules which all take the mantissas of the floating-point numbers as input, wherein each error correction module needs an enable signal; the error unbiased approximate multiplier adjusts approximate accuracy in real time in the calculation process by enabling different numbers of error correction modules; and the mantissa approximation module approximates non-linear multiplication operation through linear operation on the input mantissa. The linear operation refers to Z=XY≈A′X+B′Y+C′, wherein A′, B′, C′ are constants, Z is an approximation result, X and Y represent actual values represented by mantissas of the input floating-point numbers, and for the normalized floating-point numbers, the range is [1,2). To avoid reintroduction of the multiplication operation of the constants and the input, the first two coefficients must be restricted to be power of 2 or combination of a small number of powers of 2, and the multiplication operation is converted into shift and addition operation for input. The mantissa approximation module sums the result outputs of the 0-level approximation module and the enabled error correction module to obtain an approximate mantissa product result.

(11) According to the approximate multiplier provided by the present invention, the k-level approximation divides the range [1,2) of the input mantissa into 2.sup.k equal intervals and judges that the intervals of the mantissa needs the first k bits; the interval division of the two input mantissas is independent of each other, that is the module divides the input interval of [1,2)×[1,2) into 4.sup.k identical squares; the actual values represented by the first k bits are expressed as X.sub.k and y.sub.k, and the midpoint values of the intervals of the mantissas are

(12) $X_k+\frac{1}{2^{k+1}}\mathrm{and}{Y}_k+\frac{1}{2^{k+1}},$
that is, complementation is performed in the k+1th decimal place, recorded as and . For example, the input mantissa X=1.101011 . . . (represented by binary decimals), the fourth-level approximation needs the first four decimal places of X, X.sub.4=1.1010, the interval of X is [1.1010, 1.1011), and the midpoint value of the interval is

(13) $=X_4+\frac{1}{2^{4+1}}=1.10101.$
The approximate multiplication result under the k-level approximation is recorded as s.sub.k, and according to the minimization problem, the following may be acquired:
s.sub.k=×X+×Y−×

(14) Specifically, when the 0-level approximation module is k=0, a.sub.0=1.5x+1.5y−2.25. When k≠0, a.sub.k=s.sub.k−s.sub.k+1 May ensure the sum

(15) $\underset{k}{.Math.}{a}_i=s_k$
of the result of each level of module. Further, an expression for calculating a.sub.i is as follows:
a.sub.i=X[i]?(1):(−1)×(Y>>(i+1))+Y[i]?(1):(−1)×(X>>(i+1))+(×−×)

(16) Each level of error correction module only involves the shift operation of the input mantissa, the i-level error correction module shifts the input to the right by i+1 bits; the X[i]?(1):(−1) expression represents that when X[i] is 1, the result of the expression is 1, and when X[i] is 0, the result of the expression is −1, that is, the plus or minus is determined by the value of the i bit of another input. The offset item ×−× is relevant to the interval of the input. If i is not large, it is calculated as a constant in advance, such that a logic unit can be saved.

(17) For example, for the 1-level error correction module, the input interval is divided into four intervals {[1, 1.5], [1.5, 2)}×{[1, 1.5], [1.5, 2)}. The values of the offset items under different intervals are as follows:

(18) TABLE-US-00001 TABLE 1 The values of the offset items under different intervals Input the interval of Input the interval of x y Offset [1, 1.5] [1, 1.5] −0.6875 [1, 1.5] [1.5, 2) −0.0625 [1.5, 2) [1, 1.5] −0.0625 [1.5, 2) [1.5, 2) 0.8125

(19) As shown in FIG. 2, it is a schematic diagram of structural difference of an approximate multiplier according to the present invention and ApproxLP at a mantissa approximate part. a) in FIG. 2 is a structural diagram of a mantissa approximation module of the ApproxLP, and the higher level of error correction module depends on the judgment result of the lower level of error correction module. b) in FIG. 2 is a structural diagram of a mantissa approximation module of the approximate multiplier according to the present invention, and there is no dependency relationship among different levels of modules. Compared with the ApproxLP approximate multiplier, the approximate multiplier according to the present invention performs independent judgment on the input of the two floating-point numbers, the judgment on different levels of module is independent, the higher level of error correction module does not depend on the judgment result of the lower level of error correction module, and it is unnecessary for each module to judge the area with all the bits, thereby simplifying judgment logic and circuit delay. Moreover, as shown in FIG. 3, for the input of the uniformly distributed random floating-point numbers, under different approximate levels, the more the approximate levels are, the smaller the mean square error MSE, the mean absolute error MAE and maximum error Max Error of the approximate multiplier according to the present invention are.

(20) For each interval number, a preset offset value is required, which is very convenient and simple for the lower level of modules. However, the number is exponentially related to the complexity of the module level. For the higher level of error correction modules, the following optimization method is proposed:

(21) The i-level error correction result is equivalent to the following form:
a.sub.i=Y[i]?(−1):(1)×((−X)>>(i+1))+X[i]?(−1):(1)×((−Y)>>(i+1))+(X[i]⊕Y[i])?(1):(−1)>>(2i+2)

(22) The approximation module adopting the above expression adds two addition operations and one shift and Exclusive OR operation, but it is unnecessary to calculate the offset value in advance, such that the complexity of the circuit can be greatly reduced when the approximation level is higher.

(23) (3) The normalization module adjusts the range of the output result of the mantissa approximation module to meet the normalization requirement. The mantissas of the normalization floating-point numbers are in a range of [1,2). Due to the approximate calculation, the approximate product of the two mantissas is in a range of (0.5, 4). When the product result of the mantissas is in a range of (0.5, 4), the higher two bits are 00, the result is shifted to the left by one bit to serve as a to-be-output mantissa result, and one is subtracted from the exponent result t.sub.e of the symbol bit and the exponent bit to serve as a to-be-output exponent result z.sub.e, that is, z.sub.e. When the product result of the mantissas is in a range of [2, 4), the highest bit is 1, the result is shifted to the right by one bit to serve as a to-be-output mantissa result, and one is added to the exponent result of the symbol bit and the exponent bit to serve as a to-be-output exponent result, that is, z.sub.e=t.sub.e+1. When the product result of the mantissas is in a range of [1,2), the highest two bits are 01, the result directly serves as a to-be-output mantissa result without shifting, and the exponent result of the exponent bit directly serves as a to-be-output exponent result, that is, z.sub.e=t.sub.e.

(24) After the above operation, the to-be-output exponent results are judged as follows: when the higher two bits of the to-be-output exponent result is 01, it indicates that upward overflow occurs, that is, a number which is too large to be express, the result is assigned to be infinity meeting the IEEE 754 standard, that is, the exponent bits are all 1 and the mantissa bits are all 0; and when the higher two bits of the final exponent result are 11, it indicates that downward overflow occurs, that is a number which is too small to express, the result is assigned to be 0 meeting the IEEE 754 standard, that is, the exponent bits and the mantissa bits are all 0. If no overflow occurs, the symbol bit in the output of the symbol and exponent bit module serves as an output symbol bit, the higher two bits are removed from the to-be-output exponent result to serve as an output exponent bit, and a decimal part output by the mantissa approximation module serve as an output mantissa bit.

(25) The present invention further provides an implementation method of the error unbiased approximate multiplier for the normalized floating-point numbers, which is specifically implemented by the following steps:

(26) (1) the symbol and exponent bit module performs Exclusive OR processing on symbol bits of a multiplier and a multiplicand in the input normalized floating-point numbers, extends the high bit of the exponent bits by 2 bits, sums the exponent bits of the multiplier and the multiplicand and subtracts the offset 2.sup.n−1 to obtain an exponent bit result of the symbol and exponent bit module;

(27) (2) the 0-level approximation module and the multilevel error correction modules in the mantissa approximation module all take the mantissas of the floating-point numbers as input, each error correction module needing an enabling signal; the output of the 0-level approximation module is: a.sub.0=1.5×(X+Y)−2.25; the output of the i-level error correction module is a.sub.i±(X>>A)±(Y>>B)+C; the mantissa approximation module sums the result output of the 0-level approximation module and the enabled error correction module to obtain an approximate mantissa product result;

(28) (3) the normalization module takes the output of the symbol and exponent bit module and the mantissa approximate module as input, and the value of the output result of the mantissa approximate module is in a range of [1,2) by multiplying the output result of the mantissa approximate module by 2, dividing by 2 or not processing; when the output of the mantissa approximate module is divided by 2, 1 is added to the exponent part in the output of the symbol and exponent bit module; when the output of the mantissa approximate module is multiplied by 2, 1 is subtracted from the exponent part in the output of the symbol and exponent bit module; when the output of the mantissa approximate module is not processed, the exponent part in the output of the symbol and exponent bit module is not processed, the normalization module obtains a to-be-output mantissa result and the to-be-output exponent result; and

(29) (4) the higher two bits of the to-be-output exponent result is subjected to overflow judgment: when the higher two bits are 01, upward overflow occurs and the result is assigned to be infinity under the IEEE 754 standard; when the higher two bits are 11, downward overflow occurs and the result is assigned to be 0 under the IEEE 754 standard; when the higher two bits are 00, overflow does not occur and the symbol bit in the output of the symbol and exponent bit module is an output symbol bit, the to-be-output exponent result with higher two bits removed serves as an output exponent bit, and the to-be-output mantissa result with higher two bits removed serve as an output mantissa bit.

(30) This patent is not limited to the preferred embodiments above. Any person may obtain other forms of configurable approximate multipliers and the implementation methods thereof under the enlightenment of this patent. All equivalent changes and modifications made according to the patent scope of the present invention shall be covered within the scope of the patient.