Signal acquisition circuit, a single-housed device as well as method of acquiring data of an input signal

Abstract

A signal acquisition circuit for acquiring data of an input signal comprising at least n acquisition units, wherein n is integer greater than one, the n acquisition units comprising k inputs, wherein k is integer greater than one, and wherein at least two inputs are assigned to one channel and the corresponding acquisition units run time interleaved, and at least one trigger unit, wherein the number 1 of the at least one trigger unit is integer and wherein 1 is smaller than k. Further, a single-housed device as well as a method of acquiring data of an input signal are described.

Claims

1. A signal acquisition circuit for acquiring data of an input signal, said signal acquisition circuit comprising: at least N acquisition circuits, wherein N is an integer greater than one, said N acquisition circuits comprising K inputs, wherein K is an integer greater than one, and wherein at least two inputs are assigned to one channel and the corresponding acquisition circuits run time interleaved, and wherein the signal acquisition circuit comprises only one trigger circuit, wherein the only one trigger circuit is a common trigger circuit, wherein at least two of the N acquisition circuits are operated in parallel, wherein the at least two acquisition circuits operated in parallel share the common trigger circuit such that data outputted by the respective acquisition circuits is directly forwarded to the common trigger circuit that applies a respective trigger on the data outputted by the respective acquisition circuits, and wherein the common trigger circuit is implemented on a single chip, wherein said signal acquisition circuit further comprises a signal bus connecting each of said N acquisition circuits with said only one trigger circuit such that data outputted by the N acquisition circuits is directly forwarded to said only one trigger circuit.

2. The signal acquisition circuit according to claim 1, wherein each of said N acquisition circuits has at least one input.

3. The signal acquisition circuit according to claim 1, wherein each of said N acquisition circuits has at least two inputs that are assigned to different channels of said signal acquisition circuit.

4. The signal acquisition circuit according to claim 1, wherein each channel has a maximum sampling rate, and wherein the maximum sampling rate divided by the number of inputs is constant.

5. The signal acquisition circuit according to claim 1, wherein said signal acquisition circuit further comprises a signal bus connecting each of said N acquisition circuits with said at least one trigger circuit.

6. The signal acquisition circuit according to claim 1, wherein at least one of said n acquisition circuits comprises a quantizer configured to quantize a K-th input signal and to output a quantized input signal.

7. The signal acquisition circuit according to claim 5, wherein at least one of said n acquisition circuits comprises a quantizer configured to quantize a K-th input signal and to output a quantized input signal, and wherein said signal bus communicates said quantized input signal.

8. The signal acquisition circuit according to claim 1, wherein said signal acquisition circuit further comprises at least one filter.

9. The signal acquisition circuit according to claim 8, wherein said at least one filter is provided in one of said N acquisition circuits.

10. The signal acquisition circuit according to claim 1, wherein said signal acquisition circuit has two acquisition circuits and one trigger circuit, and wherein two inputs are provided.

11. The signal acquisition circuit according to claim 1, wherein said signal acquisition circuit has four acquisition circuits and one trigger circuit, and wherein four inputs are provided.

12. The signal acquisition circuit according to claim 1, wherein each of said N acquisition circuits is established on a separately formed chip.

13. The signal acquisition circuit according to claim 1, wherein the signal acquisition circuit relates to an interleaved acquisition system.

14. A single-housed device comprising the signal acquisition circuit according to claim 1.

15. A signal acquisition circuit for acquiring data of an input signal, said signal acquisition circuit comprising: at least N acquisition circuits, wherein N is an integer greater than one, said N acquisition circuits comprising K inputs, wherein K is an integer greater than one, and wherein at least two inputs are assigned to one channel and the corresponding acquisition circuits run time interleaved, and wherein the signal acquisition circuit comprises only one trigger circuit wherein the only one trigger circuit is a common trigger circuit, wherein the N acquisition circuits are operated in parallel, and wherein the N acquisition circuits operated in parallel share the common trigger circuit that applies a respective trigger on data outputted by the respective acquisition circuits, and wherein the common trigger circuit is implemented on a single chip, wherein said signal acquisition circuit further comprises a signal bus connecting each of said N acquisition circuits with said only one trigger circuit such that data outputted by the N acquisition circuits is directly forwarded to said only one trigger circuit.

Description

DESCRIPTION OF THE DRAWINGS

(1) The foregoing aspects and many of the attendant advantages of the claimed subject matter will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

(2) FIG. 1 shows a schematic overview of a single-housed device according to the present disclosure, which comprises a signal acquisition circuit according to the present disclosure;

(3) FIG. 2 shows an example of a signal acquisition circuit according to another embodiment;

(4) FIG. 3 shows an example of a signal acquisition circuit according to a further embodiment; and

(5) FIG. 4 shows a flow-chart illustrating a method of acquiring data of an input signal according to the present disclosure.

DETAILED DESCRIPTION

(6) The detailed description set forth below in connection with the appended drawings, where like numerals reference like elements, is intended as a description of various embodiments of the disclosed subject matter and is not intended to represent the only embodiments. Each embodiment described in this disclosure is provided merely as an example or illustration and should not be construed as preferred or advantageous over other embodiments. The illustrative examples provided herein are not intended to be exhaustive or to limit the claimed subject matter to the precise forms disclosed.

(7) In FIG. 1, a single-housed device 10 is shown that is a measurement device, for instance an oscilloscope or a spectrum analyzer. The single-housed device 10 has a housing 12 that encompasses a signal acquisition circuit 14 that is assigned to at least one signal input 16 of the single-housed device 10, which is located at a front end of the device 10. In the shown embodiment, the device 10 comprises two different signal inputs 16 for receiving signals with different bandwidths.

(8) The single-housed device 10 and, therefore, the signal acquisition circuit 14 receives an input signal via at least one of the signal inputs 16. The input signal inputted via the respective signal input 16 is processed internally by the signal acquisition circuit 14 that relates to an interleaved acquisition system as will be described later. Generally, the input signal may have a bandwidth up to 128 GHz.

(9) In the shown embodiment, the signal input 16 used is assigned to a (single) channel 18, for example an analog channel, that is enabled to process signals up to a data rate of 320 GSamples per second.

(10) As mentioned above, the signal acquisition circuit 14 relates to an interleaved acquisition system. Hence, the channel 18 is connected with or rather split into four sub-channels 20 for acquiring data from the high bandwidth input signal in an interleaved manner. For example, each of the sub-channels 20 receives different samples of the high bandwidth input signal, namely every fourth sample of the input signal inputted via the respective signal input 16.

(11) Accordingly, the first sub-channel 20 receives the samples with the indices 0, 4, 8 and so on, whereas the second sub-channel 20 receives the samples with the indices 1, 5, 9 and so on. In a similar manner, the third sub-channel 20 receives the samples with the indices 2, 6, 10 and so on, whereas the fourths sub-channel 20 receives the samples with the indices 3, 7, 11 and so on.

(12) For acquiring the respective samples processed by the different sub-channels 20, the signal acquisition circuit 14, namely the interleaved acquisition system, comprises a first acquisition unit 22, a second acquisition unit 24, a third acquisition unit 26 and a fourth acquisition unit 28, wherein each of the acquisition units 22-28 is assigned to a respective sub-channel 20.

(13) In the shown embodiment, each of the acquisition units 22-28 has an input 29 that is assigned to the respective sub-channel 20. The acquisition units 22-28 receive the respective interleaved input signal processed by the respective sub-channel 20 via their respective input 29. Accordingly, all inputs 29 are assigned to the same channel 18, wherein the corresponding acquisition units 22-28 run time interleaved.

(14) Furthermore, the signal acquisition circuit 14 comprises at least one trigger unit 30, wherein the number of the at least one trigger unit 30, labelled by l, is integer. For example, the number of the at least one trigger unit 30, namely l, is smaller than the number of the inputs 29, labelled by k. Alternatively or additionally, the number of the at least one trigger unit 30, namely l, is smaller than the number of the acquisition units 22-28, labelled by n.

(15) In the shown embodiment, a single trigger unit 30 is provided wherein all of the acquisition units 22-28 are connected with the at least one trigger unit 30 as will be described later in more detail.

(16) In some embodiments, each of the four sub-channels 20 may have a sample rate of 80 GS per second and a resolution of 12 Bit resulting in under-sampled interleaved input signals processed by the respective acquisition units 22-28.

(17) The first acquisition unit 22 is assigned to an acquisition memory 32 in which the respective acquired samples can be stored for offline post-processing. The other acquisition units 24-28 may be assigned to the same acquisition memory 32 or rather a separate acquisition memory. In other words, each of the sub-channels 20 may be assigned to their own acquisition memories. Alternatively, the sub-channels 20 are assigned to the common acquisition memory 32 that is internally divided in memory portions.

(18) As shown in FIG. 1, each of the acquisition units 22-28 is connected with the trigger unit 30 via a signal bus 34 such that data outputted by the respective acquisition units 22-28 is directly forwarded to the trigger unit 30. In other words, data is exchanged via the signal bus 34.

(19) For example, the data exchanged relates to the respective interleaved input signals that were previously processed by the corresponding acquisition units 22-28. The previously processed interleaved input signals are forwarded to the single trigger unit 30 via the signal bus 34 wherein the single trigger unit 30 applies the respective trigger (scenario) on the different interleaved input signals previously processed by the different acquisition units 22-28.

(20) In other words, the single trigger unit 30 is configured to apply a certain trigger (scenario) on the interleaved input signals processed by at least two different or rather separately formed acquisition units 22-28. Thus, the single trigger unit 30 interacts with two different or rather separately formed acquisition units 22-28.

(21) Each of the acquisition units 22-28 may have a quantizer 36 and/or a filter 38 for quantizing and/or filtering the interleaved input signals received via their inputs 29 while processing the respective interleaved input signals. Accordingly, each of the acquisition units 22-28 may output a pre-filtered and/or quantized interleaved input signal that is forwarded via the signal bus 34 towards the single trigger unit 30.

(22) In general, the single trigger unit 30 may be implemented on a single chip separately formed with respect to the acquisition units 22-28. Alternatively, the single trigger unit 30 may be provided on a common chip with one of the acquisition units 22-28. However, each of the acquisition units 22-28 is implemented on a separately formed chip.

(23) The respective chips may be established by an application-specific integrated circuit (ASIC) or rather a field-programmable gate array (FPGA). Other analog or digital circuits, programmed processors, etc., may be also employed to carry out its functionality.

(24) In FIG. 2, another embodiment of the signal acquisition circuit 14 is shown that comprises two (analog) channels 18 assigned to two different signal inputs 16 of the single-housed device 10. The channels 18 are each assigned to two acquisition units 22-28. Thus, one channel 18 is assigned to two different acquisition units 22-28 wherein one trigger unit 30 is provided per analog channel 18.

(25) The signal acquisition circuit 14 according to the embodiment of FIG. 2 is configured to process input signals with a bandwidth up to 64 GHz per channel 18 while the input signals having a sample rate of 160 GSamples per second.

(26) In a similar manner to the embodiment shown in FIG. 1, the first acquisition unit 22, 26 of each channel 18 forwards a previously processed interleaved input signal to the respective trigger unit 30 that is assigned to the other acquisition unit 24, 28 of the respective channel 18, particularly the second acquisition unit 24, 28.

(27) The embodiments of the signal acquisition circuit 14 shown in FIG. 1 and FIG. 2 differ from each other in the number of acquisition units and inputs of the respective signal acquisition circuit per channel 18. However, two inputs of the acquisition units together form one analog channel 18 wherein the respective acquisition units run time interleaved. Further, the number of the at least one trigger unit 30 is smaller than the number of the inputs of the acquisition units. Accordingly, the inputs 29 of two acquisition units 22-28 are assigned to a common channel 18, wherein the corresponding acquisition units 22-28 run time interleaved.

(28) Similar to the embodiment shown in FIG. 1, each of the acquisition units 22-28 comprises the quantizer 36 and/or the filter 38 for quantizing and/or filtering the interleaved input signals received via their inputs 29 while processing the respective interleaved input signals.

(29) Accordingly, each of the acquisition units 22-28 may output a pre-filtered and/or quantized interleaved input signal that is forwarded via the signal bus 34 towards the single trigger unit 30 of the respective channel 18.

(30) In FIG. 3, another embodiment is shown according to which each of the acquisition units 22-28 has at least two inputs 29 that are assigned to different (analog) channels 18 of the signal acquisition circuit 14. Put differently, each of the acquisition units 22-28 is assigned to at least two different signal inputs 16 yielding different configurations.

(31) In the shown embodiment, the signal acquisition circuit 14 also comprises four acquisition units 22-28. The acquisition units 22-28 or rather the respective chips are generally configured to process input signals with a bandwidth up to 128 GHz per channel 18 as well as a sample rate of 320 GSamples per second per channel 18.

(32) However, the same signal acquisition circuit 14 is also configured to process two different signals via two different channels 18 wherein the different signals may have a bandwidth up to 64 GHz per channel 18 while providing a sample rate of 160 GS per second per channel 18. This depends, for example, on the respective signal input 16 used for forwarding the input signal(s) to the signal acquisition circuit 14.

(33) As shown in FIG. 3, one of the signal inputs 16 is assigned to a channel 18 that splits into four sub-channels 20 similar to the embodiment shown in FIG. 1. This single channel 18 is enabled to process input signals with a bandwidth up to 128 GHz or rather a sample rate of 320 GSamples per second.

(34) However, the other two signal inputs 16 are each assigned to a respective channel 18 that only splits into two sub-channels 20 similar to the embodiment shown in FIG. 2. These single channels 18 each are enabled to process input signals with a bandwidth up to 64 GHz or rather a sample rate of 160 GSamples per second.

(35) Accordingly, the embodiment shown in FIG. 3 relates to a mixture of the embodiments shown in FIGS. 1 and 2 wherein each of the each of the acquisition units 22-28 has at least two inputs 29 that are assigned to different channels 18 of the signal acquisition circuit 14.

(36) Should the operator of the device 10 shown in FIG. 3 select the signal input 16 assigned to the single channel 18 interacting with all acquisition units 22-28, namely the one illustrated by dashed lines, one of the generally two trigger units 30 may be deactivated as illustrated by the dashed lines in FIG. 3. The respective signal input 16 may relate to a signal input enabled to process input signals with a bandwidth up to 128 GHz whereas the other both signal inputs 16 shown are only enabled to process input signals with a bandwidth up to 64 GHz.

(37) Hence, all acquisition units 22-28 forward their respective previously processed interleaved input signals via the signal bus 36 to the single trigger unit 30, namely the quantized and/or filtered interleaved input signals.

(38) Generally, the signal acquisition circuit 14 of all embodiments shown previously is configured to perform a method of acquiring data of the input signal inputted into one of the respective signal inputs 16.

(39) In a first step S1, the input signal inputted is received via the corresponding channel 18. The input signal may have a bandwidth up to 128 GHz.

(40) In a second step S2, the input signal is converted by one or more time interleaved analog-to-digital converters ADCs into interleaved input signals. This step relates to the interleaving of the input signal.

(41) In a third step S3, the interleaved input signals are forwarded to and received by the corresponding acquisition units 22-28 that also run time interleaved.

(42) In a fourth step S4, the acquisition units 22-28, particularly integrated quantizers 36 and/or filters 38, quantize and/or filter each interleaved input signal respectively in order to obtain quantized and/or filtered interleaved input signals.

(43) In a fifth step S5, the quantized and/or filtered interleaved input signals are forwarded to the trigger unit 30 via the signal bus 34.

(44) In a sixth step S6, the trigger unit 30 triggers on events in the de-interleaved quantized and/or filtered input signal received via the signal bus 34. Hence, the trigger unit 30 may apply complex trigger scenarios on the input signal received.

(45) In a seventh step S7, trigger information is outputted.

(46) Accordingly, the signal acquisition circuit 14 as well as the method ensure that input signals with a high bandwidth can be processed in an appropriate manner without any limitation concerning the bandwidth and without discarding any signal edges due to the interleaved signal acquisition system provided.

(47) The present application may reference quantities and numbers. Unless specifically stated, such quantities and numbers are not to be considered restrictive, but exemplary of the possible quantities or numbers associated with the present application. Also in this regard, the present application may use the term “plurality” to reference a quantity or number. In this regard, the term “plurality” is meant to be any number that is more than one, for example, two, three, four, five, etc. The terms “about,” “approximately,” “near,” etc., mean plus or minus 5% of the stated value. For the purposes of the present disclosure, the phrase “at least one of A, B, and C,” for example, means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C), including all further possible permutations when greater than three elements are listed.

(48) The principles, representative embodiments, and modes of operation of the present disclosure have been described in the foregoing description. However, aspects of the present disclosure which are intended to be protected are not to be construed as limited to the particular embodiments disclosed. Further, the embodiments described herein are to be regarded as illustrative rather than restrictive. It will be appreciated that variations and changes may be made by others, and equivalents employed, without departing from the spirit of the present disclosure. Accordingly, it is expressly intended that all such variations, changes, and equivalents fall within the spirit and scope of the present disclosure, as claimed.