Ultra-high speed optical transport employing LDPC-coded modulation with non-uniform signaling
09735921 · 2017-08-15
Assignee
Inventors
Cpc classification
H03M13/1102
ELECTRICITY
H04L1/005
ELECTRICITY
H03M7/00
ELECTRICITY
H03M7/3084
ELECTRICITY
International classification
Abstract
A low-density parity-check (LDPC) coded bit-interleaved coded modulation with iterative decoding (BICM-ID) scheme with nonuniform signaling which is effected by mapping simple variable-length prefix codes onto the constellation. By employing Huffman procedure(s), prefix codes can be designed to approach optimal performance. Experimental evaluations of the schemes demonstrate that the nonuniform scheme performs better than 8-QAM by at least 8.8 dB.
Claims
1. A method for transmitting data, comprising: receiving a set of information bits, encoding the set of information bits using one or more low density parity check (LDPC) encoders with nonuniform signaling, employing one or more signal constellations wherein variable-length prefix codes are mapped onto the set of constellation points, wherein said constellation points are chosen such that they exhibit a nonuniform probability distribution, and transmitting the encoded data over a transmission medium; wherein the constellation points are chosen according to a Maxwell-Boltzmann distribution; and wherein the nonuniform signaling is an arbitrary nonuniform signaling, wherein information bits and parity bits are transmitted with different modulation schemes.
2. The method according to claim 1 wherein the nonuniform signaling is effected by either Huffmann or Lempel-Zif encoding.
3. The method according to claim 1 further comprising performing a block interleaved coded modulation (BICM) with independent decoding (ID).
4. A system for transmitting data comprising: one or more low density parity check (LDPC) encoders configured to encode one or more streams of input data; a signal constellation generation module configure to generate one or more signal constellations wherein variable-length prefix codes are mapped onto the set of constellation points, wherein said constellation points are chosen such that they exhibit a nonuniform probability distribution, and a coherent optical-orthogonal frequency division multiplexing transmitter configured to transmit the encoded data over a transmission medium; wherein the constellation points are chosen according to a Maxwell-Boltzmann distribution; and wherein the nonuniform signaling is an arbitrary nonuniform signaling, wherein information bits and parity bits are transmitted with different modulation schemes.
Description
BRIEF DESCRIPTION OF THE DRAWING
(1) A more complete understanding of the present disclosure may be realized by reference to the accompanying drawing in which:
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(8) The illustrative embodiments are described more fully by the Figures and detailed description. Inventions according to this disclosure may, however, be embodied in various forms and are not limited to specific or illustrative embodiments described in the Figures and detailed description
DESCRIPTION
(9) The following merely illustrates the principles of the disclosure. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the disclosure and are included within its spirit and scope.
(10) Furthermore, all examples and conditional language recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions.
(11) Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.
(12) Thus, for example, it will be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the disclosure. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudo code, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.
(13) The functions of the various elements shown in the Figures, including any functional blocks labeled as “processors”, may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term “processor” or “controller” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read-only memory (ROM) for storing software, random access memory (RAM), and non-volatile storage. Other hardware, conventional and/or custom, may also be included.
(14) Software modules, or simply modules which are implied to be software, may be represented herein as any combination of flowchart elements or other elements indicating performance of process steps and/or textual description. Such modules may be executed by hardware that is expressly or implicitly shown.
(15) Unless otherwise explicitly specified herein, the FIGURES are not drawn to scale.
(16) We begin by again noting one key technology for next generation optical transport is the LDPC-coded super-channel orthogonal-frequency-division-multiplexed (OFDM). Such an approach is typically considered for single mode fiber (SMF) applications and it is based on conventional quadrature-amplitude-modulation (QAM) scheme(s). Also, it is noteworthy that some non-conventional approaches to achieve data rates beyond 1 Tb/s of serial optical transport over SMFs include generalized OFDM (GOFDM). Other approaches proposed the use of hybrid multidimensional coded modulation (CM), employing both electrical and optical degrees of freedom to address noted constraints in a simultaneous manner. Optical degrees of freedom include the polarization and spatial modes in few-mode fibers (FMFs) and few core fibers (FCF). The electrical degrees of freedom include orthogonal prolate spheroidal wave functions. These degrees of freedom are used and the basis functions for multidimensional signaling.
(17) Constellation Shaping with Huffman Code
(18) A method according to the present disclosure for achieving non-uniform signaling schemes for the transmission of binary data (constellation shaping with Huffman code) may be described as follows. Output of a uniform binary memoryless source is parsed into a sequence of blocks drawn from the set {0, 01, 11} and these blocks are represented as symbols such that they may be mapped onto a PAM constellation as shown in
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If we place two such 1D 3-PAM schemes along phase and quadrature components, we can obtain the 2D 9-QAM constellation set which can achieve an average bit rate of 3 bits/T. Notice that in this constellation set—which is shown in
(20) The tree representation of the Huffman code used to map the constellation is shown in
(21) LDPC Coded Modulation Scheme with Non-Uniform Signaling
(22) In order to maintain shaping gain brought about by non-uniform signaling and the possibility of using joint source-channel decoding (JSCD) techniques, an LDPC coded modulation scheme for arbitrary non-uniform signaling according to the present disclosure is introduced. As an illustrative example, we employ a quasi-cyclic LDPC code exhibiting a rate r≧0.8, codeword length n, and information word-length of k.
(23) One particularly noteworthy aspect of this scheme is the block interleaver. With initial reference to
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(25) First, binary information bits are first written into the last two rows of the interleaver. The interleaver size for non-uniform signaling is n×L.sub.M, where L.sub.M is the max source-codeword length of the corresponding Huffman code. Next, bits are read in column-wise fashion from bottom to top for the last two rows. If the two bits are not 00, then the information bits are written to the third row, otherwise that position is left blank. Next, the bits are read column-wise from bottom to top for the last three rows. If the three bits are in the set [101, 111] then continue writing the information bits to the fourth row, otherwise leave the position blank. Next, fill the blank position with puncture bits—according to Table 1. Finally, encode every row bits with QC-LDPC encoder and generate parity bit blocks.
(26) As may be observed from
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(28) On a receiver side of that telecommunications transmission system, a conventional polarization diversity receiver may advantageously be employed—with a small number of coefficients in digital backpropagation scheme to reduce channel memory so that the complexity of a sliding-window MAP equalizer that follows is not too high. The sliding-MAP equalizer provides soft symbol LLRs, which are used to determine bit LLRs and further passed to LDPC decoders.
(29) Accordingly, symbol LLRs calculation may be summarized as follows:
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where s=(I.sub.i, Q.sub.i) denotes the transmitted signal constellation point at time instant i, while r=(r.sub.i, r.sub.i) denotes the received point. Symbol LLRs are denoted by λ(s).
(31) Bit LLRs can be determined from symbol LLRs as:
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(33) Note that when performing the bit LLRs calculation, the punctured bits will be considered as normal bits in order to avoid ambiguities caused by the non-uniform signaling. The extrinsic LLRs for the next iteration in LDPC decoders are calculated by:
L.sub.M,e(ċ.sub.j)−L.sub.D,e(ċ.sub.j)
where L.sub.D,e(c.sub.j) is the LDPC decoder extrinsic LLRs which are forwarded to the sliding-MAP equalizer, so that the symbol a priori LLRs are calculated as:
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(35) The iteration occurring between the LDPC decoder extrinsic LLRs is performed until the maximum number of iterations is reached. Regarding the LDPC decoder, a sum-product algorithm is generally employed.
(36) Simulation Results
(37) To illustrate the efficiency of methods performed according to the present disclosure, Monte Carlo simulations have been performed and the results summarized graphically in
(38) TABLE-US-00001 TABLE 1 Probability of Each Symbol and Corresponding Punctured Bits Information Punctured Bits Probability Bits 00 0.25 01 010 0.125 0 110 0.125 1 011 0.125 0 100 0.125 1 1110 0.0625 N/A 1111 0.0625 N/A 1010 0.0625 N/A 1011 0.0625 N/A
(39) At this point, while we have presented this disclosure using some specific examples, those skilled in the art will recognize that our teachings are not so limited. Accordingly, this disclosure should be only limited by the scope of the claims attached hereto.