Hybrid switch including GaN HEMT and MOSFET

Abstract

A hybrid switch apparatus includes a gate drive circuit producing a gate drive signal, a GaN high electron mobility transistor (HEMT) having a first gate, a first drain, and a first source. A silicon (Si) MOSFET has a second gate, a second drain, and a second source. The GaN HEMT and the Si MOSFET are connected in a parallel arrangement so that (i) the first drain and the second drain are electrically connected and (ii) the first source and the second source are electrically connected. The second gate is connected to the gate drive circuit output to receive the gate drive signal. A delay block has an input connected to the gate drive circuit output and an delay block output is configured to produce a delayed gate drive signal for driving the GaN HEMT.

Claims

1. An apparatus comprising: a gate drive circuit having at least one gate drive output configured to produce a gate drive signal on said gate drive output; a wide-bandgap (WBG) switching device having a first gate, a first drain, and a first source; a semiconductor switch having a second gate, a second drain, and a second source, said WBG switching device and said semiconductor switch being connected in a parallel arrangement wherein (i) said first drain and said second drain are electrically connected and (ii) said first source and said second source are electrically connected, said second gate being connected to said gate drive circuit output to receive said gate drive signal; and a delay block having an input connected to said gate drive circuit output and an output configured to produce a delayed gate drive signal, said first gate of said WBG switching device being connected to said delay block output to receive said delayed gate drive signal.

2. The apparatus of claim 1 wherein said WBG switching device comprises a high electron mobility transistor (HEMT).

3. The apparatus of claim 2 wherein said HEMT comprises a GaN high electron mobility transistor (HEMT) device.

4. The apparatus of claim 1 wherein said semiconductor switch comprise a silicon (Si) MOSFET device.

5. The apparatus of claim 4 wherein said Si MOSFET comprises a body diode between said second source and said second drain.

6. The apparatus of claim 1 wherein said delay block comprises an resistor-capacitor (RC) circuit.

7. The apparatus of claim 1 wherein said gate drive signal comprises an on state and an off state, and wherein when said gate drive signal transitions from said OFF state to said ON state, said delay block delays a transition of said delayed gate drive signal from said OFF state to said ON state.

8. The apparatus of claim 7 further comprising an electronic control unit configured to control said gate drive circuit in accordance with a zero voltage switching (ZVS) strategy.

9. The apparatus of claim 8 wherein said electronic control unit is configured to control said gate drive circuit to output said gate drive signal in said on or off state.

10. The apparatus of claim 8 wherein said electronic control unit is configured to control said gate drive circuit in accordance with said ZVS strategy when transitioning said gate drive signal from said off state to said on state.

11. The apparatus of claim 2 wherein said HEMT and said semiconductor switch form a first hybrid switch arrangement, said apparatus further comprising a second hybrid switch arrangement replicating said first hybrid switch arrangement, and wherein said first and second sources of said first hybrid switch arrangement are connected to said first and second drains of said second hybrid switch arrangement at a common node.

12. The apparatus of claim 11 wherein said first and second arrangements are used in a bridge circuit.

13. The apparatus of claim 7 wherein when said gate drive signal transitions from said ON state to said OFF state, said delay block delays a transition of said delayed gate drive signal from said ON state to said OFF state, and wherein said delayed gate drive signal transitions to said OFF state when said gate drive signal is in said OFF state.

14. An apparatus comprising: a gate drive circuit having at least one gate drive output configured to produce a gate drive signal on said gate drive output wherein said gate drive signal comprises an ON state and an OFF state; a wide-bandgap (WBG) switching device having a first gate, a first drain, and a first source; a semiconductor switch having a second gate, a second drain, and a second source, said WBG switching device and said semiconductor switch being connected in a parallel arrangement wherein (i) said first drain and said second drain are electrically connected and (ii) said first source and said second source are electrically connected, said second gate being connected to said gate drive circuit output to receive said gate drive signal; and a delay block having an input connected to said gate drive circuit output and an output configured to produce a delayed gate drive signal, said first gate of said WBG switching device being connected to said delay block output to receive said delayed gate drive signal; wherein when said gate drive signal transitions from said OFF state to said ON state, said delay block delays a transition of said delayed gate drive signal from said OFF state to said ON state, and when said gate drive signal transitions from said ON state to said OFF state, said delay block delays a transition of said delayed gate drive signal from said ON state to said OFF state, and wherein said delayed gate drive signal transitions to said OFF state when said gate drive signal is in said OFF state.

15. The apparatus of claim 14 wherein said WBG switching device comprises one of a GaN high electron mobility transistor (HEMT) device and a SiC device.

16. The apparatus of claim 14 wherein said semiconductor switch comprise a silicon (Si) MOSFET device.

17. The apparatus of claim 14 wherein said delay block comprises an resistor-capacitor (RC) circuit.

18. The apparatus of claim 14 further comprising an electronic control unit configured to control said gate drive circuit in accordance with a zero voltage switching (ZVS) strategy.

19. The apparatus of claim 18 wherein said electronic control unit is configured to control said gate drive circuit in accordance with said ZVS strategy when transitioning said gate drive signal from said off state to said on state.

20. An apparatus comprising: means for producing (i) a gate drive signal on a gate drive output and (ii) a delayed gate drive signal that is delayed relative to said gate drive signal, wherein said gate drive signal comprises an ON state and an OFF state; a wide-bandgap (WBG) switching device having a first gate, a first drain, and a first source; a semiconductor switch having a second gate, a second drain, and a second source, said WBG switching device and said semiconductor switch being connected in a parallel arrangement wherein (i) said first drain and said second drain are electrically connected and (ii) said first source and said second source are electrically connected, said second gate being connected to said producing means to receive said gate drive signal; and said first gate of said WBG switching device being connected to said producing means to receive said delayed gate drive signal; wherein when said gate drive signal transitions from said OFF state to said ON state, said delay block delays a transition of said delayed gate drive signal from said OFF state to said ON state, and when said gate drive signal transitions from said ON state to said OFF state, said delay block delays a transition of said delayed gate drive signal from said ON state to said OFF state, and wherein said delayed gate drive signal transitions to said OFF state when said gate drive signal is in said OFF state.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is diagrammatic schematic and block diagram of an apparatus with paralleled transistors according to an embodiment of the instant disclosure.

(2) FIG. 2 is a schematic diagram of an alternate embodiment using a replication of the arrangement of FIG. 1.

(3) FIG. 3 illustrates simplified timing diagrams of a gate drive signal and a delayed gate drive signal reflecting the operation of the embodiment of FIG. 2.

(4) FIGS. 4-7 are schematic diagrams of the embodiment of FIG. 2 showing different modes of operation.

DETAILED DESCRIPTION

(5) Various embodiments are described herein to various apparatuses, systems, and/or methods. Numerous specific details are set forth to provide a thorough understanding of the overall structure, function, manufacture, and use of the embodiments as described in the specification and illustrated in the accompanying drawings. It will be understood by those skilled in the art, however, that the embodiments may be practiced without such specific details. In other instances, well-known operations, components, and elements have not been described in detail so as not to obscure the embodiments described in the specification. Those of ordinary skill in the art will understand that the embodiments described and illustrated herein are non-limiting examples, and thus it can be appreciated that the specific structural and functional details disclosed herein may be representative and do not necessarily limit the scope of the embodiments, the scope of which is defined solely by the appended claims.

(6) Reference throughout the specification to “various embodiments,” “some embodiments,” “one embodiment,” or “an embodiment,” or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases “in various embodiments,” “in some embodiments,” “in one embodiment,” or “in an embodiment,” or the like, in places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Thus, the particular features, structures, or characteristics illustrated or described in connection with one embodiment may be combined, in whole or in part, with the features, structures, or characteristics of one or more other embodiments without limitation given that such combination is not illogical or non-functional.

(7) Switching Losses.

(8) As described above, silicon switches (e.g., MOSFETs) generally experienced switching losses when, for example, they are switched off. As will be described below in greater detail, the Si MOSFET will be switched off while the GaN HEMT is still on—due to a time delay inserted into the respective gate drive signals. Accordingly, there is no switching losses for the Si MOSFETs.

(9) Reverse Conduction Loss.

(10) A so-called reverse conduction loss for GaN HEMT devices was described above. By way of explanation, the GaN HEMT devices, because of the absence of the body diode, will have a reverse conduction mode that is different from Si MOSFETs. In particular, when V.sub.gd is higher than a reverse threshold voltage V.sub.th.sub._.sub.gd, the two-dimensional electron gas (2DEG) of GaN HEMTs conducts the current with the voltage drop as shown in equation (1).
Vsd=Vth_gd−Vgs_off+id*Rdson  (1)

(11) In order to prevent a potential shoot-through in a bridge circuit, a negative V.sub.gs.sub._.sub.off is always preferred to turn off GaN HEMT switches, which however increases the dead-band loss. For example, for the 650V/60V GaN HEMT provided by GaN Systems Inc, the V.sub.th.sub._.sub.gd=2V. When V.sub.gs.sub._.sub.off=−5V to turn off the GaN HEMT switch, which is typical for normal for Si or SiC MOSFETs, the reverse voltage drop of the GaN HEMT will be at least 7V (e.g., as per equation (1)). To solve such issue of undue reverse conduction loss, options could include either reducing V.sub.gs.sub._.sub.off to zero, or alternatively to shrink the deadband (i.e., to shorten the time when the GaN HEMT switch is OFF). Both of these options may impair the proper operation of the system.

(12) To more fully utilize the merits of GaN HEMT switches and avoid its relatively large reverse conduction loss, accordingly to the teachings of the instant application, a hybrid switch is provided which uses a GaN HEMT switch paralleled with a Si MOSFET switch. As will be described below, such a hybrid switch apparatus overcomes the reverse conduction loss in the GaN HEMT switch while also overcoming switching losses in a Si MOSFET switch, when used in zero-voltage-switching (ZVS) turn-on applications.

(13) Referring now to the drawings wherein like reference numerals are used to identify identical or similar components in the various views, FIG. 1 is a diagrammatic view of an embodiment of a hybrid switch apparatus 10. Apparatus 10 comprises a paralleled switch arrangement suitable for use in a power electronics system. The embodiment of FIG. 1 may be considered a single switch arrangement that can be replicated for use in larger constructs, such as shown in FIG. 2 in the application of a bridge, to be connected with respect to a load(s) and/or power source in a variety of ways known in the art.

(14) In the illustrated embodiment, apparatus 10 includes a gate drive circuit 12 having at least one gate drive circuit output 14. The gate drive circuit 12 may comprise a semiconductor chip and further be configured to respond to a variety of input signals (e.g., voltage and/or current inputs) in order to output, among other things, a gate drive signal 16 (best shown in FIG. 3) at the gate drive circuit output 14. In particular, the gate drive circuit 12 may produce the gate drive signal 16 in accordance with a predetermined control approach. The art is replete with exemplary control strategies, and is dependent on the particular application. Alternatively, the processing needed to produce a gate drive signal may be performed by, an electronic control unit (ECU) as described below in greater detail.

(15) As shown in FIG. 3, the gate drive signal 16 includes at least an ON state 18 and an OFF state 20. In an embodiment, the ON state 18, when asserted by the gate drive circuit 12, is configured to turn on the target switch, while the OFF state 20, when asserted, is conversely configured to turn off the target switch.

(16) In an embodiment, the gate drive circuit 12 may comprise conventional apparatus commercially available in the art, for example, known MOSFET/GaN gate drive integrated circuits (“chip”). In the illustrated embodiment, for GaN HEMT devices, the gate drive circuit 12 may comprise a Half-Bridge Gate Driver for Enhancement Mode GaN FETs gate drive circuit (e.g., as in FIG. 2), model no. LM5113, commercially available from Texas Instruments, Dallas, Tex., U.S.A. In an embodiment, the gate drive signal 16, also sometimes designated V.sub.G.sub._.sub.MOS herein, may have its output voltage V.sub.G.sub._.sub.mos ranging between about +7 V for the ON state 18 to −5 V for the OFF state 20.

(17) While FIG. 1 shows a gate drive circuit 12, which can be a specific control device, apparatus 10 may additionally include, or may have as a substitute for the gate drive circuit 12, an electronic control unit (ECU) 100 that is configured to implement a desired control strategy for the operation of hybrid switch apparatus 10. ECU 100 includes a processor 102 and a memory 104. The processor 102 may include processing capabilities as well as an input/output (I/O) interface through which processor 102 may receive a plurality of input signals (input block 106 providing input signal(s) 108) and generate a plurality of output signals (e.g., gate drive signal(s), in an embodiment). Memory 104 is provided for storage of data and instructions or code (i.e., software) for processor 102.

(18) Memory 104 may include various forms of non-volatile (i.e., non-transitory) memory including flash memory or read only memory (ROM) including various forms of programmable read only memory (e.g., PROM, EPROM, EEPROM) and/or volatile memory including random access memory (RAM) including static random access memory (SRAM), dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

(19) In an embodiment, one approach for switching device turn-on control may be to employ a zero voltage switching (ZVS) strategy. As shown, the control strategy for turn-off control and turn-on control (including the ZVS control) can be implemented in terms of operating control logic 110, which comprises processor instructions that can be stored in memory 104 and are configured to be executed by processor 102. Alternatively, the operational control logic for controlling the operation of the hybrid switch apparatus 10 (i.e., turn-off and turn-on control) can be implemented in hardware. As shown, the ECU 100 may produce a control signal 112 that controls the gate drive circuit 12 to assert and de-assert the gate drive signal 16 (see FIG. 3 for timing diagram). The art is replete with teachings for implementing a zero voltage switching (ZVS) control strategy. Generally, in order to maintain zero voltage switching for switch turn-on, before the turning on action, current should reverse flow, which makes the switch voltage drop to zero. Thus, during the switch turn on, the switch only undertakes the current change with a voltage then-prevailing thereacross always being close to be zero, which in turn eliminates the turn-on loss to thereby reach the ZVS turn on. Further information may be seen by reference to U.S. application Ser. No. 14/744,988, filed 19 Jun. 2015 (the '988 application) entitled “GATE DRIVE CIRCUIT”. The '988 application is hereby incorporated by reference as though fully set forth herein.

(20) With continued reference to FIG. 1, hybrid switch apparatus 10 further includes a wide-bandgap switch, such as a GaN high electron mobility transistor (HEMT) 26 which includes a first gate 28, a first drain 30, and a first source 32. In an embodiment, the GaN HEMT switch 26 may comprise commercially available components, for example, an enhancement mode GaN transistor provided under the trade designation and/or part number GS66516T from GaN Systems Corp., Ann Arbor, Mich., USA.

(21) The hybrid switch apparatus 10 further includes one or more silicon switches, such as a silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) 34 which includes a second gate 36, a second drain 38, and a second source 40. In an embodiment, the MOSFET 34 may comprise commercially available components, for example, an N-Channel power MOSFET provided under the trade designation and/or part number STY139N65M5 from STMicroelectronics, Coppell, Tex., USA.

(22) The GaN HEMT 26 and the Si MOSFET 34 are electrically connected in a parallel arrangement to each other, wherein (i) the first drain 30 and the second drain 38 are electrically connected and (ii) the first source 32 and the second source 40 are also electrically connected. As shown in FIG. 1, the second gate 36 is electrically connected to the gate drive circuit output 14 in order to receive the gate drive signal 16 (V.sub.G.sub._.sub.MOS).

(23) The hybrid switch apparatus 10 still further includes a delay block 22 having an input connected to the gate drive circuit output 14, which input is configured to receive the gate drive signal 16 (V.sub.G.sub._.sub.MOS). The delay block 22 further includes an output configured to produce a delayed gate drive signal, which is designated V.sub.G.sub._.sub.GaN. The first gate 28 of the GaN HEMT 26 is electrically connected to the output of the delay block 22 in order to receive the delayed gate drive signal (V.sub.G.sub._.sub.GaN). As alluded to, the delay block 22 operates to insert a time delay between the gate signals of two switches 26, 34. In an embodiment, the delay block 22 may comprise a resistor-capacitor (RC) circuit of conventional design. In an embodiment, the delay block 22 may be configured to insert a time delay of not larger than about 100 nanoseconds (ns).

(24) FIG. 2 shows how the hybrid switch apparatus 10 may be used as part of a bridge circuit (see external circuit 42). It should be understood that the hybrid switch apparatus 10 may be used in other applications, such as, for example, a half-bridge, an H-bridge, a three-phase inverter, and the like. In this regard, as shown, the hybrid switch arrangement in the apparatus 10 of FIG. 1 is replicated, where an “upper” switch contains the same components as in the embodiment of FIG. 1 where its reference numerals include a subscript “1” while the “lower” switch contains the same components as in the embodiment of FIG. 1 where its reference numerals include a subscript “2”. The source terminal of the “upper” switch, namely, the source terminals 32.sub.1 and 40.sub.1, are electrically connected, at a common node 44, to the drain terminal of the “lower” switch, namely drain terminals 30.sub.2 and 38.sub.2. As further shown, the electronic control unit 100 is configured to generate control signals 112.sub.1 and 112.sub.2 for controlling operation of the “upper” and “lower” hybrid switch apparatus, respectively.

(25) FIG. 3 is a timing diagram of the of the gate drive signals and delayed gate drive signals applicable to the embodiment of FIG. 2. In particular, the time sequence of the gate drive signals 16.sub.1, 16.sub.2 (also shown as signals V.sub.G.sub._.sub.MOS1 and V.sub.G.sub._.sub.MOS2) are shown on a common time-line, as well as the corresponding delayed gate drive signals 24.sub.1, 24.sub.2 (also shown as signals V.sub.G.sub._.sub.GaN1 and V.sub.G.sub._.sub.GaN2).

(26) With reference now to FIGS. 4-7, a description of the operation of the embodiment of FIG. 2 according to the signal timing shown in FIG. 3 will now be set forth. Specifically, the operation of the embodiment of FIG. 2 can be broken down in to six separate time periods or modes.

(27) Mode 1: [t.sub.0, t.sub.1].

(28) During the time period between times t.sub.0, t.sub.1, all of the switches are off (i.e., switches 26.sub.1, 34.sub.1, 26.sub.2, 34.sub.2). This is because all the gate drive signals are de-asserted and are in the OFF state. In an exemplary zero voltage switching (ZVS) application, the current I.sub.L shown in FIG. 2 will be taken to be positive—this is shown in FIG. 4. Therefore, the current I.sub.L will flow through the “upper” switch comprising GaN HEMT 26.sub.1 and Si MOSFET 34.sub.1. However, since the GaN HEMT 26.sub.1 exhibits a roughly 7V drop—as described above in connection with equation (1)—as compared to the only roughly 1˜2V voltage drop of the body diode of Si MOSFET 34.sub.1, the current I.sub.L will flow through the body diode of Si MOSFET 34.sub.1, as shown in FIG. 4.

(29) Mode 2: [t.sub.1, t.sub.2].

(30) During the time period between times t.sub.1, t.sub.2, the upper Si MOSFET 34.sub.1 is on, while the other switches remain off (i.e., the other switches 26.sub.1, 26.sub.2, 34.sub.2 remain off). This is because (i) notwithstanding the assertion of the gate drive signal 16.sub.1 (V.sub.G.sub._.sub.MOS1), the delay block 22 has time delayed the corresponding assertion of the gate drive signal 24.sub.1 (V.sub.G.sub._.sub.GaN1); and (ii) the gate drive signals 16.sub.2, 24.sub.2 (V.sub.G.sub._.sub.MOS2, V.sub.G.sub._.sub.GaN2) are also both in the OFF state. ZVS application means that the current I.sub.L shown in FIG. 2 is positive—as also shown in FIG. 4. Therefore, the current I.sub.L will flow through the upper Si MOSFET 34.sub.1 channel. Since the GaN HEMT 26.sub.1 exhibits a roughly 7V drop in this example (see above in connection with Equation (1))—as compared to the much smaller voltage drop across the channel of the Si MOSFET 34.sub.1 (i.e., the MOSFET channel voltage drop is much smaller due to a small resistance—is ˜mΩ), the current I.sub.L will flow through the Si MOSFET 34.sub.1 channel.

(31) Mode 3: [t.sub.2, t.sub.3].

(32) During the time period between times t.sub.2, t.sub.3, both the upper GaN HEMT 26.sub.1 and the Si MOSFET 34.sub.1 are on, while the lower switches remain off (i.e., the lower switches 26.sub.2, 34.sub.2 remain off). This is because the turn-on delay inserted by the delay block 22 has passed and thus both the upper gate drive and upper delayed gate drive signals 16.sub.1, 24.sub.1 (V.sub.G.sub._.sub.MOS1, V.sub.G.sub._.sub.GaN1) are both asserted and in the ON state, while the lower gate drive and lower delayed gate drive signals 16.sub.2, 24.sub.2 (V.sub.G.sub._.sub.MOS2, V.sub.G.sub._.sub.GaN2) are de-asserted and in the OFF state. In an embodiment, the MOSFET channel resistance can be made to be much smaller than that of the GaN HEMT by paralleling further Si MOSFETs (not shown), which is relatively affordable. Accordingly, as shown in FIG. 5, most of the current I.sub.L will still flow through Si MOSFET 34.sub.1 channel, although a smaller portion of the current I.sub.L will flow through the GaN HEMT 26.sub.k. Accordingly, in modes 1-3 operation, a reverse conduction loss through the GaN HEMT 26.sub.1 that might have been occurred if the GaN HEMT 26.sub.1 were used alone is thus avoided.

(33) Mode 4: [t.sub.3, t.sub.4].

(34) During the time period between times t.sub.3, t.sub.4, the upper GaN HEMT 26.sub.1 is ON and the upper Si MOSFET 34.sub.1 is OFF, while the lower switches also remain off (i.e., the lower switches 26.sub.2, 34.sub.2 remain off). This is because (i) notwithstanding the de-assertion of the gate drive signal 16.sub.1 (V.sub.G.sub._.sub.MOS1) to turn OFF the “upper” Si MOSFET, the delay block 22 has time delayed the corresponding de-assertion of the gate drive signal 24.sub.1 (V.sub.G.sub._.sub.GaN1) controlling the upper GaN HEMT 26.sub.k. Also, the gate drive signals 16.sub.2, 24.sub.2 (V.sub.G.sub._.sub.MOS2, V.sub.G.sub._.sub.GaN2) are both de-asserted and thus in the OFF state. In sum, all switches are off except the upper GaN HEMT 26.sub.1. To realize ZVS for the lower hybrid switch arrangement, during this period, the polarity of the electrical current I.sub.L should be reversed, shown in FIG. 6. It should be appreciated that when the upper Si MOSFET 34.sub.1 is turned off by de-assertion of gate drive signal 16.sub.1 (V.sub.G.sub._.sub.MOS1) that the GaN HEMT 26.sub.1 is still on, by virtue of the time delay inserted by delay block 22. As a consequence, therefore, the Si MOSFET 34.sub.1 is ZVS turned off. There is no switching-off loss for the upper Si MOSFET 34.sub.1.

(35) In addition, although the upper GaN HEMT 26.sub.1 is hard turned off at t=t.sub.4, experimental results show that the GaN HEMT 26.sub.1 turn off is ignorable. More specifically, compared to the hard turn-on loss, the above-mentioned hard turn-off loss is much smaller. Therefore, embodiments consistent with the teachings of the present disclosure are able to run at a much higher switching frequency, since the Si MOSFET switching loss is zero.

(36) Mode 5: [t.sub.4, t.sub.5].

(37) During the time period between times t.sub.4, t.sub.5, all of the switches are off (i.e., switches 26.sub.k, 34.sub.k, 26.sub.2, 34.sub.2). This is because all the gate drive signals are de-asserted and are in the OFF state. Again, similar to mode 1, since the body diode of the lower Si MOSFET 34.sub.2 exhibits a much lower voltage drop than that of the GaN HEMT 26.sub.2, the current I.sub.L will go through body diode of lower MOSFET 34.sub.2 instead, which exhibits about a 1˜2V voltage drop only.

(38) Mode 6: [t.sub.5, t.sub.6].

(39) During the time period between times t.sub.5, t.sub.6, the lower Si MOSFET 34.sub.2 is on, while the other switches remain off (i.e., the other switches 26.sub.1, 26.sub.2, 34.sub.1 remain off). This is because (i) notwithstanding the assertion of the gate drive signal 16.sub.2 (V.sub.G.sub._.sub.MOS1), the delay block 22 has time delayed the corresponding assertion of the gate drive signal 24.sub.2 (V.sub.G.sub._.sub.GaN2); and (ii) the gate drive signals 16.sub.k, 24.sub.1 (V.sub.G.sub._.sub.MOS1, V.sub.G.sub._.sub.GaN1) are also both in the OFF state. Similar to mode 2 above, the current I.sub.L will flow through the lower Si MOSFET 34.sub.2 channel, as shown in FIG. 7. Since the GaN HEMT 26.sub.2 exhibits a roughly 7V drop in this example (see above in connection with Equation (1))—as compared to the much smaller voltage drop across the channel of the Si MOSFET 34.sub.2 (i.e., the MOSFET channel voltage drop is much smaller due to a small resistance—is ˜mΩ), the current I.sub.L will flow through the lower Si MOSFET 34.sub.2 channel. In sum, the lower Si MOSFET is ON, which makes all current go through its channel. At time t=t.sub.6, the lower GaN HEMT 16.sub.2 is ZVS ON—this occurs after the time delay inserted by the delay block has passed.

(40) Therefore, in summary, the following features of the hybrid switch apparatus can be described. First, there is no current going through GaN HEMTs when all of the switches are OFF. Therefore, the relatively large reverse conduction loss can be avoided for GaN HEMTs. Second, all the Si MOSFETs are turned off when the GaN HEMTs are still on. Therefore, there is no switching off loss for the Si MOSFETs. Third, all the switches are ZVS turned-on. Therefore, all the Si MOSFETs do not have any switching loss but only at most conduction losses. Fourth, all the GaN HEMTs will only undertake the switching off loss with very little forward/reverse conduction loss and zero switching on loss. Therefore, all the conduction loss is undertaken by the Si MOSFETs. All the switching off losses are undertaken by the GaN HEMTs. The foregoing described hybrid switch apparatus fully utilizes the advantages of both the Si MOSFET devices as well as the GaN HEMT devices.

(41) It should be understood that an electronic control unit as described herein may include conventional processing apparatus known in the art, capable of executing pre-programmed instructions stored in an associated memory, all performing in accordance with the functionality described herein. To the extent that the methods described herein are embodied in software, the resulting software can be stored in an associated memory and can also constitute the means for performing such methods. Implementation of certain embodiments, where done so in software, would require no more than routine application of programming skills by one of ordinary skill in the art, in view of the foregoing enabling description. Such an electronic control unit may further be of the type having both ROM, RAM, a combination of non-volatile and volatile (modifiable) memory so that any software may be stored and yet allow storage and processing of dynamically produced data and/or signals.

(42) Although only certain embodiments have been described above with a certain degree of particularity, those skilled in the art could make numerous alterations to the disclosed embodiments without departing from the scope of this disclosure. It is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative only and not limiting. Changes in detail or structure may be made without departing from the invention as defined in the appended claims.

(43) Any patent, publication, or other disclosure material, in whole or in part, that is said to be incorporated by reference herein is incorporated herein only to the extent that the incorporated materials does not conflict with existing definitions, statements, or other disclosure material set forth in this disclosure. As such, and to the extent necessary, the disclosure as explicitly set forth herein supersedes any conflicting material incorporated herein by reference. Any material, or portion thereof, that is said to be incorporated by reference herein, but which conflicts with existing definitions, statements, or other disclosure material set forth herein will only be incorporated to the extent that no conflict arises between that incorporated material and the existing disclosure material.

(44) While one or more particular embodiments have been shown and described, it will be understood by those of skill in the art that various changes and modifications can be made without departing from the spirit and scope of the present teachings.