SYSTEM FOR HANDLING SHORT CIRCUITS ON AN ELECTRICAL NETWORK

Abstract

A system for handling short circuits on an electrical network comprising parallel operated units which are droop controlled for active and reactive power sharing and connected to each other via impedances and protection switches for detecting and handling a short circuit on the electrical network and for disconnecting the faulty part of the electrical network, said units including a DC-source and a grid forming voltage source inverter controlled by a cascaded control structure with an inner voltage control loop and a short circuit control for limiting the output current by changing the output voltage at the output terminals of the inverter as a function of the measured output current and a desired droop voltage provided by a droop controller for voltage and frequency power sharing.

Claims

1. A system for handling short circuits on an electrical network comprising: parallel operated units which are droop controlled for active and reactive power sharing and connected to each other via impedances and protection switches for detecting a short circuit on the electrical network and for disconnecting the faulty part of the electrical network, said parallel operated units including a direct current source and a grid forming voltage source inverter controlled by a cascaded control structure with a voltage controller and a short circuit control for limiting output current and output voltage at output terminals of the inverter as a function of a measured output current and a desired droop voltage provided by a droop control for voltage and frequency power sharing.

2. The system of claim 1, wherein a voltage amplitude of a desired reference voltage provided to an inner voltage control loop is reduced as a function of the desired droop voltage of the droop control and an output current amplitude, such that the desired reference voltage is given by the offset of the desired droop voltage and a function dependent on the output current according to the following equations:
V.sub.2.sup.d({tilde over (V)}.sub.2.sup.d,I.sub.2)=(|{tilde over (V)}.sub.2.sup.d|−ƒ.sub.1(|I.sub.2|))sin(Φ.sub.{tilde over (V)}.sub.2.sub.d)
(|{tilde over (V)}.sub.2.sup.d|−f.sub.1(|I.sub.2|))=V.sub.2.sup.d|
sin(Φ.sub.{tilde over (V)}.sub.2.sub.d)={tilde over (V)}.sub.2.sup.d/|{tilde over (V)}.sub.2.sup.d| and sin(Φ.sub.{tilde over (V)}.sub.2.sub.d)ε custom-character .sup.3 for |{tilde over (V)}.sub.2.sup.d|≠0 wherein V.sub.2.sup.d is the desired reference voltage, |V.sub.2.sup.d| is the voltage amplitude of the desired reference voltage, {tilde over (V)}.sub.2.sup.d is the desired droop voltage, |I.sub.2| is the output current amplitude, and |{tilde over (V)}.sub.2.sup.d| is the offset of the desired droop voltage.

3. The system of claim 2, wherein the current dependent function is zero if the amplitude of the second measured output current is lower than a given current limit and greater than zero if the amplitude of the second measured output current rises above the given current limit.

4. The system of claim 3, wherein the current dependent function rises when the amplitude of the second measured output current rises above the given current limit and decreases more slowly due to a slew rate for falling values of the second measured output current amplitude.

5. The system of claim 1, wherein the second measured output current is limited by a virtual frequency independent and output current dependent impedance placed between a low-pass filter of the grid forming voltage source inverter and the output terminals of the inverter such that the desired reference voltage of the short circuit handled inverter depends on the desired droop voltage and the second measured output current according to V.sub.2.sup.d={tilde over (V)}.sub.2.sup.d+Z.sub.v(|I.sub.2|)I.sub.2, wherein Z.sub.v(|I.sub.2|) is the virtual frequency independent and output current dependent impedance and I.sub.2 is the second measured output current.

6. The system of claim 5, wherein the virtual frequency independent impedance is a piecewise constant impedance which, according to $Z_{v} (.Math. I_{2} .Math.) = {\begin{matrix} Z_{K} & if .Math. .Math. .Math. I_{2} .Math. \geq I_{2}^{N} .Math. \\ 0 & else \end{matrix}$ is zero as long as the second measured output current is below a given threshold value, in particular a nominal second output current, and which is switched to a constant value if the second measured output current exceeds the given threshold value, wherein |I.sub.2.sup.N| is the given threshold value and I.sub.2.sup.N is the nominal second output current.

7. The system of claim 6, wherein after clearing the short circuit, the virtual impedance decreases with a slew rate such that the output voltage of the inverter increases as the virtual impedance becomes smaller.

8. The system of claim 6, wherein after clearing the short circuit, the virtual impedance is set to zero and a function is activated ensuring that the value of the virtual impedance is changed only if the second measured output current is below a certain threshold for the respective period.

9. The system of claim 5, wherein the virtual frequency independent impedance is a current dependent impedance with a piecewise affine, polynomial, exponential, spline, or a sinusoidal function.

10. The system of claim 9, wherein the current dependent impedance (Z.sub.v(|I.sub.2|)) with a piecewise affine function changes with the amplitude of the second measured output current (I.sub.2) according to $Z_{v} (.Math. I_{2} .Math.) = {\begin{matrix} \frac{V^{N}}{I_{2}^{K} - I_{2}^{N}} .Math. (.Math. I_{2} .Math. - I_{2}^{N}) & if .Math. .Math. .Math. I_{2} .Math. \geq I_{2}^{N} \\ 0 & else \end{matrix}$ wherein V.sup.N is a nominal output voltage of the inverter, I.sub.2.sup.N is a current threshold of the inverter, |I.sub.2| is the amplitude of the second measured output current of the inverter and I.sub.2.sup.K is the short circuit current to be provided of the second measured output current of the inverter.

11. The system of claim 10, wherein the change of the value of the virtual current dependent impedance is limited to obtain a more sinusoidal waveform during nonsymmetrical short circuits.

12. The system of claim 9, wherein the virtual frequency independent and current dependent impedance follows a polynomial, exponential, spline, or sinusoidal function.

13. The system of claim 1, wherein the unit with grid forming inverters comprises controllable power electronic devices having an input terminal, an output terminal and a control terminal, a low pass filter connected to the output terminals of the power electronic devices and a discrete time controller, wherein the control terminals of the power electronic devices receiving switching pulses from an output of the time controller, the input terminals of which are exposed to a measured input voltage of the DC-source, an output voltage of the grid forming inverter, a measured output current of the power electronic devices or a measured output current of the grid forming inverter, and a desired droop control voltage from a next control cascade, wherein the discrete time controller comprises a pulse width modulator providing the switching pulses to the control terminals of the power electronic devices, a voltage controller for controlling the output voltage of the inverter, and a short circuit controller for limiting the output voltage of the inverter.

14. The system of claim 13, wherein the low pass filter of the inverter is connected to an impedance or primary winding of a transformer, wherein the transformer includes a secondary winding connected to the electrical network.

15. The system of claim 14, wherein the low pass filter comprises filter inductances between the output terminals of the power electronic devices and the primary winding of the transformer and a series connection of filter resistances and filter capacitors in the interconnection between the filter inductances.

16. The system of claim 13, wherein the voltage controller receives a first input signal corresponding to the output voltage of the inverter, a second input signal corresponding to the measured second output current in the interconnection of the filter inductances of the low pass filter and the impedance or primary winding of the transformer and the desired output voltage provided by the output of the short circuit controller, wherein the voltage controller provides the desired input voltage to the input of the pulse width modulator, and wherein the short circuit controller receives a first input signal corresponding to the second measured output current on the interconnection of the filter inductances of the low pass filter and the primary winding of the transformer and a second input signal corresponding to the desired droop voltage from a next control cascade.

17. The system of claim 13, wherein the voltage controller receives a first input signal corresponding to the output voltage of the inverter, a second input signal corresponding to the first measured output current in the interconnection of the output terminals of the power electronic devices and the filter inductances of the low pass filter and a desired reference voltage provided by the output of the short circuit controller, wherein the voltage controller provides the desired input voltage to the input of the pulse width modulator, and wherein the short circuit controller receives a first input signal corresponding to the first measured output current in the interconnection of the output terminals of the power electronic devices and the filter inductances of the low pass filter and a second input signal corresponding to the desired droop control voltage from a next control cascade.

18. The system of claim 13, wherein the voltage controller receives a first input signal corresponding to the output voltage of the inverter, a second input signal corresponding to the second measured output current in the interconnection of the filter inductances of the low pass filter and the impedance or primary winding of the transformer and the desired droop control voltage from a next control cascade, wherein the short circuit controller receives an input signal corresponding to the second measured output current in the interconnection of the filter inductances of the low pass filter and the primary winding of the transformer and a first reference input voltage provided at the output of the voltage controller and wherein the short circuit controller provides a desired input voltage to the input of the pulse width modulator.

19. The system of claim 13, wherein the voltage controller receives a first input signal corresponding to the output voltage of the inverter, a second input signal corresponding to the first measured output current in the interconnection of the output terminals of the power electronic devices and the filter inductances of the low pass filter and the desired droop control voltage from a next control cascade, wherein the short circuit controller receives an input signal corresponding to the first measured output current in the interconnection of the output terminals of the power electronic devices and the filter inductances of the low pass filter and a first reference input voltage provided at the output of the voltage controller and wherein the short circuit controller provides a desired input voltage to the input of the pulse width modulator.

20. The system of claim 1, wherein the desired droop control voltage is generated using droop control for both synchronizing the grid forming inverters connected to the electrical network and to achieve short circuit power sharing among the grid forming inverters and one or more conventional generators connected to the electrical network.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Further features and advantages of the present application will become apparent from the following detailed description, taken in combination with the appended drawings, in which:

[0043] FIG. 1 is a schematic block diagram of an electric distribution network or grid comprising a plurality of droop controlled inverters, conventional generators, renewable energy sources and loads distributed among the grid in a decentralized way;

[0044] FIG. 2 is a schematic block diagram of a part of an electrical network comprising a plurality of units with voltage source inverters running in parallel while a short circuit occurs;

[0045] FIG. 3 is a schematic circuit diagram of a single-line representation of a switching inverter;

[0046] FIG. 4 is a schematic circuit and block diagram of a first embodiment of a control structure of a grid forming unit wherein the output voltage of an inverter is controlled as function of the output current of the inverter and a desired droop control voltage;

[0047] FIG. 5 is a schematic graph of a reduction of a voltage amplitude as function of a current amplitude used to limit a short circuit current of an inverter;

[0048] FIG. 6 is a schematic circuit diagram of an inverter with a virtual frequency independent output impedance;

[0049] FIG. 7 is a schematic graph of a virtual, piecewise constant frequency independent impedance as function of a current used to limit a short circuit current of an inverter;

[0050] FIG. 8 is a schematic graph of a virtual, piecewise affine (solid line) and polynomial (dashed line) impedance as function of a current used to limit a short circuit current of an inverter;

[0051] FIG. 9 is a schematic circuit and block diagram of a second embodiment of a control structure of a grid forming unit wherein the output voltage of an inverter is controlled as a function of the current of the lines between the output terminals of the power electronic devices and the low-pass filter of the inverter and a desired droop control voltage;

[0052] FIG. 10 is a schematic circuit and block diagram of a third embodiment of a control structure of a grid forming unit wherein the input voltage of an inverter is controlled as a function of the output current and output voltage of the inverter and a desired droop control voltage and

[0053] FIG. 11 is a schematic circuit and block diagram of a fourth embodiment of a control structure of a grid forming unit wherein the input voltage of an inverter is controlled as a function of the current on the lines between the output terminals of the power electronic devices and the low-pass filter of the inverter and a desired droop control voltage.

DETAILED DESCRIPTION

[0054] The various embodiments will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or alike parts. References made to particular examples and implementations are for illustrative purposes, and are not intended to limit the scope of the application or the claims.

[0055] As used herein, the terms “about” or “approximately” for any numerical values or ranges indicates a suitable dimensional tolerance that allows the part or collection of components to function for its intended purpose as described herein. Furthermore, the number N of inverter units, generator units etc. may be equal or different, i.e. there may be M inverter units, N generator units, O bus bars, P photovoltaic power units etc.

[0056] FIG. 3 illustrates a schematic circuit diagram of a single-line representation of a switching voltage source inverter 3 according to FIG. 4 which is applied in a unit with parallel running inverters 3.1-3.N according to the schematic block diagram of FIG. 2. The single-line representation of the switching voltage source inverter 3 shows two semiconductor switches 31, 32 of a power electronic device the input terminals of which are connected to a DC-source providing a DC input voltage V.sub.DC and DC input current I.sub.DC via an input capacitor 30. The output terminals of the semiconductor switches 31, 32 are commonly connected to a first (semiconductor terminal) of a filter inductance 51 of a low-pass filter 5 the second terminal of which is connected to a series connection of a filter resistor 52 and a filter capacitor 53 connected to ground.

[0057] A first output voltage V.sub.1 and a first measured output current I.sub.1 are delivered at the interconnection of the output terminals of the semiconductor switches 31, 32 of the power electronic device. A second output voltage V.sub.2 is provided at the series connection of the filter resistors 52 and the filter capacitor 53 of the low-pass filter 5 and a second output current I.sub.2 (in case of a short circuit the short circuit current) is provided on the line between the low-pass filter 5 and the transformer 7 at the output terminal of the inverter 3 according to FIG. 2.

[0058] As mentioned above there are three main tasks to be solved to safely provide short circuit currents, namely: the current of the inverters has to be limited during short circuit; the provided current has to be as high as possible to trip the protection devices; and the inverters have to stay synchronized in order to provide the desired current jointly.

[0059] As to the first and second technical requirement of a short circuit handling the limits for the semiconductor switches 31 and 32 of the switching, controlled voltage source inverter 3 must not be exceeded when a short circuit occurs, during the whole time of the short circuit and after the short circuit, in order to protect these components. These limits are the instantaneous values of current and voltage of every phase. For the single line representation of the switching voltage source inverter 3 according to FIG. 3 this means that the absolute values V.sub.1, V.sub.2, I.sub.1 and I.sub.2 stay below the maximum value in symmetrical and unsymmetrical fault conditions. The current of the corresponding phase(es) should be as big as possible in order to trip the protection devices as fast as possible.

[0060] As to the third technical requirement of an optimized short circuit handling the inverters 3 have to share the short circuit currents. Hence, the phase angles and amplitudes of the voltages on the AC terminals of the inverters 3 have to stay synchronized in order to achieve this power sharing property. The need for synchronization results from a small drift of the internal clocks of the inverters 3. This drift ε leads to an error in the integration of the phase angle δ(t) according to the following equation:

δ(t)=∫.sub.0.sup.tω(τ)+εdτ=∫.sub.0.sup.tω(τ)dτ+εt

[0061] from the frequency ω(τ). As the error is integrated with ω(τ), the phase angles δ(t) of the inverters 3 would drift away from each other even if they had the same frequency and initial phase angle. Through the inductive coupling of the units connected to the electrical network this would lead to an undesired power flow between the units and in the short circuit case in a reduction of the current for tripping the protection devices. To cope with this lack of accuracy, droop control is used to keep the difference in phase angles constant in a decentralized fashion

[0062] Droop control is commonly applied to generators or inverters for primary frequency and voltage control to allow parallel operation and load sharing. Since, in inductive grids, active power has a large influence on the phase angle and reactive power has a large influence on the voltage difference, the phase angle and voltage can be used to control active and reactive power. Furthermore, for classical generators, from the swing equation it is known that frequency is related to the phase angle, such that by controlling active power, frequency and hereby the phase angle is controlled. This forms the basis of frequency and voltage droop control where active and reactive power are adjusted according to linear characteristics.

[0063] Thus, the power sharing property of the units connected to the electrical network has be preserved during short circuit such that the provided currents of the units sum up. Also, it is important to keep the inverters synchronized during short circuit to prevent cross currents between the units that result from different phase angles and, hence limit the power delivery of the inverters.

[0064] In the following different cascaded control structures with short circuit handling will be explained in connection with FIGS. 4 and 9 to 11.

[0065] The inner loop of the cascaded control structure of a discrete time controller 1 according to FIG. 4 consists of a voltage controller 8 and an inverter unit 2 which comprises a DC-source 10, a (grid forming) inverter 3, a transformer 7 and a pulse width modulator 6. The inverter 3 includes controllable power electronic devices 31-36 and a low pass filter 5 comprising filter inductances 51, filter resistors 52 and filter capacitors 53. Alternatively, the capacitor could also be connected in star connection and not in triangle as in FIG. 4, and FIG. 9-11. The pulse width modulator 6 provides switching pulses SP to the control terminals of the power electronic devices 31-36 depending on a measured input voltage V.sub.DC of the DC-source 10 measured by a voltage sensor 11 and a desired mean value of the input voltage V.sub.1.sup.dε custom-character .sup.3 over one switching instant on the power electronic side of the low-pass filter 5.

[0066] This voltage V.sub.1.sup.dε custom-character .sup.3 is provided by the output terminal of the voltage controller 8 the input terminals of which receive a first input signal corresponding to the output voltage V.sub.2 of the inverter 3 (i.e. the instantaneous voltage at the beginning of the discrete time control cycle), optionally a second input signal corresponding to a second measured output current I.sub.2ε custom-character .sup.3 on the interconnection of the filter inductances 51 of the low pass filter 5 and the primary winding 71 of the transformer 7 measured by a current sensor 12. The secondary winding 72 of the transformer is connected to the point of common coupling in form of the bus bar B1 of the electrical network or grid which may also contain inverters and conventional generators with a similar control structure as the controlled inverter 3 of the unit 2 or other control as is the case for renewable energy sources.

[0067] A short circuit controller 9 is added to the inner loop for changing the reference voltage amplitude V.sub.2.sup.dε custom-character .sup.3 of the inverter terminals measured by a second voltage sensor 13. The short circuit controller 9 receives at its input terminals an input signal corresponding to a measured output current I.sub.2 of the grid forming inverter 3 between the low-pass filter 5 and the primary winding 71 of the transformer 7, and a desired voltage {tilde over (V)}.sub.2.sup.d from the next control cascade. At its output terminal the short circuit controller 9 provides a reference voltage V.sub.2.sup.d to an input terminal of the voltage controller 8.

[0068] The pulse width modulator 6, voltage controller 8 and short circuit controller 9 together with the part that provides the reference signal {tilde over (V)}.sub.2.sup.d form a discrete time controller 1 for handling normal operation as well as a short circuit on the electrical network or transmission line TL1, respectively.

[0069] In order to limit the output current I.sub.2ε custom-character .sup.3, the output voltage V.sub.2 on the terminals of the inverter 3 is reduced as a function of the measured current I.sub.2 on the lines between the low-pass filter 5 of the inverter 3 and the transformer 7. Through the pulse width modulator 6 and the voltage controller 8 this voltage V.sub.2.sup.d=ƒ({tilde over (V)}.sub.2.sup.d, I.sub.2) is transformed to switching pulses SP for the power electronic devices 4.

[0070] The desired voltage {tilde over (V)}.sub.2.sup.d is e.g. generated using droop control as described above to synchronize the inverters and achieve power sharing among the units 2.1 to 2.N according to FIG. 2.

[0071] In the following it is assumed that short circuits that occur before the electrical bus B1 are handled by local protection of the units by switching them off i.e. short circuit voltage on the terminals of the inverter 3 V.sub.2 will be at least the short circuit voltage of the transformer 7, the desired droop control voltage {tilde over (V)}.sub.2.sup.d(t) is always given by a three phase symmetrical voltage, that can be written by the following equation:

[00003] ${\tilde{V}}_{2}^{d} (t) = (\begin{matrix} {\tilde{v}}_{2, 1}^{d} (t) \\ {\tilde{v}}_{2, 2}^{d} (t) \\ {\tilde{v}}_{2, 3}^{d} (t) \end{matrix}) = .Math. {\tilde{V}}_{2}^{d} (t) .Math. .Math. (\begin{matrix} \sin .Math. .Math. (δ (t)) \\ \sin .Math. .Math. (δ (t) - 2 / 3 .Math. .Math. π) \\ \sin .Math. .Math. (δ (t) + 2 / 3 .Math. .Math. π) \end{matrix}) .Math.$ $with .Math.$ $.Math. .Math. {\tilde{V}}_{2}^{d} .Math. = .Math. \sqrt{\frac{2}{3} .Math. ({({\tilde{v}}_{2, 1}^{d})}^{2} + {({\tilde{v}}_{2, 2}^{d})}^{2} + {({\tilde{v}}_{2, 3}^{d})}^{2})}$

[0072] In the sequel a Clarke transformation for a three phase signal X(t)ε custom-character .sup.3 is used which is defined as:

[00004] $X^{αβ} (t) = \frac{2}{3} .Math. (\begin{matrix} 1 & - \frac{1}{2} & \frac{1}{2} \\ 0 & \frac{\sqrt{3}}{2} & - \frac{\sqrt{3}}{2} \end{matrix}) .Math. X (t)$

[0073] with X.sup.αβ(t)ε custom-character .sup.3 and

[00005] $T = \frac{2}{3} .Math. (\begin{matrix} 1 & - \frac{1}{2} & \frac{1}{2} \\ 0 & \frac{\sqrt{3}}{2} & - \frac{\sqrt{3}}{2} \end{matrix})$

wherein Tε custom-character .sup.2×3. The vector X.sup.αβ(t) can be interpreted as a rotating phasor in a fixed Cartesian coordinate system. The length of the phasor X(t)ε.sup.3 with X(t)=(x.sub.1(t),x.sub.2 (t),x.sub.3(t)).sup.τ is defined as

[00006] $.Math. X .Math. (t) .Math. = {.Math. TX (t) .Math.}_{2} .Math. \Leftrightarrow .Math. X (t) .Math. = \sqrt{\frac{2}{3} .Math. (x_{1}^{2} (t) + x_{2}^{2} (t) + x_{3}^{2} (t))}$

[0074] In the following, the separation into amplitude and phase information of the quantities is used for some short circuit strategies. Hence, it is exemplary introduced for the desired droop control voltage {tilde over (V)}.sub.2.sup.d and the second measured output current I.sub.2. Of course, the decomposition can be done in a similar way for other quantities, e.g. for the desired reference voltage V.sub.2.sup.d. The separation can be achieved using the above term, to calculate the voltage and current amplitudes

[00007] $.Math. {\tilde{V}}_{2}^{d} .Math. = .Math. \sqrt{\frac{2}{3} .Math. ({({\tilde{v}}_{2}^{d})}^{2} + ({\tilde{v}}_{2, 2}^{d}) + {({\tilde{v}}_{2, 3}^{d})}^{2})}$ $.Math. I_{2} .Math. = .Math. \sqrt{\frac{2}{3} .Math. (i_{2, 1}^{2} + i_{2, 2}^{2} + i_{2, 3}^{2})}$

[0075] The phase information can be calculated by sin (Φ.sub.{tilde over (V)}di .sub.d)={tilde over (V)}.sub.2.sup.d/|{tilde over (V)}.sub.2.sup.d| and sin Φ.sub.I.sub.2=I.sub.2/|I.sub.2| wherein sin (Φ.sub.{tilde over (V)}.sub.2.sub.d), sin Φ.sub.I.sub.2ε custom-character .sup.3 under the assumption that |{tilde over (V)}.sub.2.sup.d|≠0 and |I.sub.2|≠0. The signals can then be restored using the connection:

{tilde over (V)}.sub.2.sup.d=|{tilde over (V)}.sub.2.sup.d|(sin Φ.sub.{tilde over (V)}.sub.2.sub.d)

I.sub.2=|I.sub.2|(sin Φ.sub.I.sub.2)

[0076] Referring to the control structure according to FIG. 4 the short circuit controller has two input signals, namely {tilde over (V)}.sub.2.sup.d=({tilde over (v)}.sub.2,1.sup.d, {tilde over (v)}.sub.2,2.sup.d, {tilde over (v)}.sub.2,3.sup.d).sup.T and I.sub.2=(i.sub.2,1, i.sub.2,2, i.sub.2,3).sup.T, and one output signal, namely the desired reference voltage V.sub.2.sup.d=(v.sub.2,1.sup.d, v.sub.2,2.sup.d, v.sub.2,3.sup.d).sup.T. In the sequel different solutions for the functions V.sub.2.sup.d=ƒ({tilde over (V)}.sub.2.sup.d, I.sub.2) for limiting the short circuit current by changing the desired reference voltage V.sub.2.sup.d at the input of the voltage controller 8 will be presented. Note, that the presented functions could also be used to limit the voltage amplitude V.sub.1.sup.d as a function of the current I.sub.2 or the current I.sub.1 as described in connection with FIGS. 9 to 11.

[0077] A first solution for limiting the short circuit current is a reduction of the voltage amplitude |V.sub.2.sup.d| of the desired reference voltage V.sub.2.sup.d as a function of the amplitude |I.sub.2| of the output current I.sub.2 (the second output current I.sub.2 is measured between the low-pass filter 5 and the transformer 7) such that the output voltage V.sub.2.sup.d is:

V.sub.2.sup.d({tilde over (V)}.sub.2.sup.d,I.sub.2)=(|{tilde over (V)}.sub.2.sup.d|ƒ.sub.1(|I.sub.2|))sin(Φ.sub.{tilde over (V)}.sub.2.sub.d) wherein (|{tilde over (V)}.sub.2.sup.d|−f.sub.1(|I.sub.2|))=|V.sub.2.sup.d|

[0078] The voltage amplitude |{tilde over (V)}.sub.2.sup.d| is then given by the offset of |{tilde over (V)}.sub.2.sup.d| and a current dependent function f.sub.1(|I.sub.2|).

[0079] A possible form of the current dependent function f.sub.1(|I.sub.2|) is shown in FIG. 5 of the drawings.

[0080] If the amplitude of the measured output current I.sub.2 raises above a given limit |i.sub.2.sup.N|, the function ƒ.sub.1(|I.sub.2|) becomes greater than zero. In terms of the desired reference voltage V.sub.2 according to the above equitation, the voltage amplitude |V.sub.2.sup.d| of the desired reference voltage V.sub.2.sup.d decreases. The arrows in FIG. 5 denote that the function ƒ.sub.1(|I.sub.2|) raises fast and decreases slow, due to a slew/ramp rate for falling values of the measured output current I.sub.2. Hence, when the short circuit is cleared, the function ƒ.sub.1(|I.sub.2|) slowly decreases, i.e. the voltage amplitude |V.sub.2.sup.d| of the desired reference voltage V.sub.2.sup.d slowly increases. This is due to reduce inrush currents into the transformer 7 and possible overvoltage.

[0081] The solution described before in connection with the control structure according to FIG. 4 is in compliance with the technical requirements of a limitation of current and voltage as well as with a synchronization and load sharing.

[0082] As to a limitation of current and voltage the proposed reduction of the voltage amplitude |V.sub.2.sup.d| of the desired reference voltage V.sub.2.sup.d, a short circuit can be limited to a desired value. The fact that the output voltage V.sub.2 is reduced for all phases in the same way, even in case of an unsymmetrical short circuit, does not limit the ability to deliver the desired short circuit current for the concerned phase(s), since the decrease in the voltage amplitude |V.sub.2.sup.d| of the desired reference voltage V.sub.2.sup.d is a function of the current of the faulty phase(s). Hence, the decrease of voltage of the non-faulty phase(s) has no negative effect on the short circuit behavior. Furthermore, a change of the voltage amplitude during one period in case of unsymmetrical faults can be reduced by adjusting the rising edge slew rate of the function ƒ.sub.1(|I.sub.2|).

[0083] Synchronization and short circuit power sharing can be achieved if the voltage amplitude on the so called point of common coupling, where the transformers of the units 2.1 to 2.N are connected is not too small. If the voltage on the point of common coupling is below a certain value in the range of approximately 10% of the nominal value V.sup.N, this property cannot be guaranteed. In this case, the inverters cannot synchronize, which leads to an increase or decrease of the phase angle differences between the droop controlled inverters. This change of the phase angle differences has two effects: a) There is an undesired current flow between the inverters and b) the short circuit power decreases as phase angle differences are not constant any more. Still, if the drift is not too high, the phase angles will not increase to a risky value, and the inverters can still synchronize. Simulations showed that for the time of a short circuit, which is typically below approximately five seconds the phase angle drift does not result in problems for the power sharing during and after a short circuit. The slow increase of the voltage amplitude after the short circuit can additionally reduce the load swing between the units as the power flow increases with the voltage amplitude.

[0084] A second solution for limiting the short circuit current is by introducing a virtual output impedance and, herewith take into account the phase information of the current for limitation. Figuratively speaking, the virtual output impedance Z.sub.v(|I.sub.2|) is placed between the low-pass filter 5 and the output terminals of the power electronic devices 4 of the inverter 3, as shown in FIG. 6. The schematic single-line representation of the switching, voltage source inverter 3 with a virtual frequency independent output impedance Z.sub.v(|I.sub.2|) mainly corresponds to the diagram according to FIG. 3 wherein the input terminals of two semiconductor switches 31, 32 of the power electronic device are connected to a DC-source providing a DC input voltage V.sub.DC and a DC input current I.sub.DC and a DC bus input capacity 30. The output terminals of the semiconductor switches 31, 32 are commonly connected to a first (semiconductor terminal) of a filter inductance 51 of a low-pass filter 5 the second terminal of which is connected to a series connection of a filter resistor 52 and a filter capacitor 53 connected to ground as well as to the virtual frequency independent output impedance Z.sub.v(|I.sub.2|).

[0085] A first output voltage V.sub.1 and a first measured output current I.sub.1 are delivered at the interconnection of the output terminals of the semiconductor switches 31, 32 of the power electronic device. A desired droop control voltage {tilde over (V)}.sub.2.sup.d from the next control cascade is provided at the series connection of the filter resistor 52 and filter capacitor 53 of the low-pass filter 5 and a second output current I.sub.2 (in case of a short circuit, the short circuit current) is provided on the line between the virtual frequency independent output impedance Z.sub.v(|I.sub.2|) and the output terminal of the inverter 3 with the output voltage V.sub.2 of the inverter 3.

[0086] The virtual output impedance Z.sub.v(|I.sub.2|) could also be placed in series with the filter inductance 51 of the low-pass filter 5, resulting in a very similar behavior. The impedance is virtual in the sense that it is part of a control software, with the advantage that it has more degrees of freedom in the design than a real passive component. For a different control structure the virtual output impedance Z.sub.v(|I.sub.2|) can be placed in another part of the inverter 3 or electrical network and not as shown in FIG. 6.

[0087] The virtual output impedance Z.sub.v(|I.sub.2|) is preferably designed as a frequency independent impedance, but the reactance could be extended to a real frequency dependent impedance with its own state. The impedance is assumed to be a resistor, but could be extended to any impedance (ohmic/inductive/capacitive or mixed). In compliance with the circuit in FIG. 6, the output of the inverter with short circuit handling is:

V.sub.2.sup.d={tilde over (V)}.sub.2.sup.d+Z.sub.v(|I.sub.2|)I.sub.2

[0088] where the term Z.sub.v(|I.sub.2|) represents a current dependent virtual output impedance. In the sequel, two impedance models will be presented as examples for the functional principle of the solution.

[00008] $Z_{v} (.Math. I_{2} .Math.) = {\begin{matrix} Z_{K} & if .Math. .Math. .Math. I_{2} .Math. \geq I_{2}^{N} .Math. \\ 0 & else \end{matrix}$

[0090] Hence, the virtual, piecewise constant impedance Z.sub.v(|I.sub.2|) is zero as long as the output current amplitude |I.sub.2| is below a certain threshold, for example a nominal current I.sub.2.sup.N. If the current |I.sub.2| exceeds this value, the impedance Z.sub.v is switched to a constant value Z.sub.K. If the short circuit clears, the impedance Z.sub.v can be decreased in two ways: Instantaneously or with a slew or ramp rate.

[0091] If the virtual impedance Z.sub.v is decreased with a slew rate, the voltage V.sub.2.sup.d increases for as the impedance Z.sub.v becomes smaller. In case the impedance Z.sub.v is set to zero instantaneously, there needs to be a function that ensures that the impedance value is not changed all the time in case of an unsymmetrical short circuit. Therefore, a function is used that changes the value of Z.sub.v only if the current |I.sub.2| is below the threshold or nominal current I.sub.2.sup.N for a certain time period. This is done to evite switching the impedance Z.sub.v on and off during an unsymmetrical short circuit, as that could excite the dynamical system, and hence lead to overvoltages or overcurrents. Combining the last two equations the desired reference voltage V.sub.2.sup.d can easily be calculated as

[00009] $V_{2}^{d} = {\begin{matrix} {\tilde{V}}_{2}^{d} + Z_{K} .Math. I_{2} & if .Math. .Math. .Math. I_{2} .Math. \geq I_{2}^{N} .Math. \\ {\tilde{V}}_{2}^{d} & else \end{matrix}$

[0092] where the output current I.sub.2 is oriented according to FIG. 6, i.e. from the output terminal of the inverter to the virtual impedance Z.sub.v.

[0093] A limitation of the short circuit current of the inverter by means of a virtual, piecewise constant impedance Z.sub.v(|I.sub.2|)=ƒ(|I.sub.2|) as a function of the output current amplitude |I.sub.2.sup.N| is in compliance with the technical requirements of a limitation of current and voltage as well as with synchronization and load sharing.

[0094] As to a limitation of current and voltage the proposed reduction of the voltage amplitude |V.sub.2.sup.d| of the desired reference voltage V.sub.2.sup.d, a short circuit can be limited to a desired amount. Since only the faulty phase(s) have an increased current and therefore a voltage drop over the virtual impedance Z.sub.v, unsymmetrical short circuits result in a voltage imbalance. Still, this is not a problem, as the desired short circuit currents are delivered. (a voltage imbalance occurs all the time during short circuit of conventional generators not leading to problems in this case).

[0095] Synchronization and short circuit power sharing can be achieved if the voltage amplitude on the point of common coupling, where the transformers of the units are connected is not too small. If the voltage on the point of common coupling is below a certain value in the range of approximately 10% of the nominal value V.sup.N, this property cannot be guaranteed. However, if the voltage is above this value, the proposed strategy leads to power sharing during short circuits. If the voltage at the point of common coupling is below about 10% of the nominal value V.sup.N, the drift cannot be influenced by the decentralized synchronization, but is in a range, where the short circuit currents can still be served.

[0096] In a second impedance model a current dependent impedance is used to limit the short circuit currents instead of a virtual, piecewise constant impedance Z.sub.v. The current dependent impedance Z.sub.v(|I.sub.2|) could have a piecewise affine or polynomial gradient, as depicted in FIG. 8. In case of a piecewise affine function, the virtual impedance Z.sub.v changes according to the output current I.sub.2, such that:

[00010] $Z_{v} (.Math. I_{2} .Math.) = {\begin{matrix} \frac{V^{N}}{I_{2}^{K} - I_{2}^{N}} .Math. (.Math. I_{2} .Math. - I_{2}^{N}) & if .Math. .Math. .Math. I_{2} .Math. \geq I_{2}^{N} \\ 0 & else \end{matrix}$

[0097] Hence, the virtual impedance Z.sub.v(|I.sub.2|) changes all the time with the short circuit current amplitude |I.sub.2|. Instead of a linear function (solid line) as depicted in FIG. 8 the virtual impedance Z.sub.v(|I.sub.2|) can follow a polynomial (dashed line), exponential, sinusoidal, spline, exponential, etc. form.

[0098] Furthermore, the change of the value of the virtual impedance Z.sub.v(|I.sub.2|) can be limited in order to obtain a more sinusoidal waveform during unsymmetrical short circuits. As stated before, this slew rate must not limit the rising, but only the falling edge of the virtual impedance Z.sub.v(|I.sub.2|), as a limitation of the rising edge might lead to overcurrents if the voltage is not reduced enough if overcurrents occur.

[0099] A limitation of the short circuit current of the inverter by means of a virtual, current dependent impedance Z.sub.v(|I.sub.2|)=ƒ(|I.sub.2|) as a function of the output or short circuit current amplitude |I.sub.2.sup.N| is in compliance with the technical requirements of both a limitation of a short circuit current and voltage and with synchronization and power sharing.

[0100] With the proposed reduction of the voltage amplitude, the short circuit can be limited to a desired amount. As only the faulty phase(s) have an increased current and therefore a voltage drop over the virtual current dependent impedance Z.sub.v(|I.sub.2|), unsymmetrical short circuits lead to an additional voltage imbalance as Z.sub.v(|I.sub.2|)=ƒ(|I.sub.2|) changes all the time with the current amplitude. This phenomenon can be reduced by adjusting the falling edge slew rate of Z.sub.v(|I.sub.2|)=ƒ(|I.sub.2|). However, the short circuit currents can reliably be served.

[0101] As with a limitation of the short circuit current of the inverter by means of a virtual current dependent impedance Z.sub.v(|I.sub.2|)=ƒ(|I.sub.2|) synchronization can be achieved if the voltage amplitude on the point of common coupling, where the transformers of the units are connected is not too small.

[0102] The solutions to comply with the technical requirements both of a limitation of short circuit current and voltage as well as with a synchronization and load sharing described before in connection with the control structure according to FIG. 4 are likewise adoptable to the control structures of FIGS. 9 to 11.

[0103] FIG. 9 depicts a schematic circuit and block diagram of a second embodiment of a discrete time controller 1 for a grid forming unit 2 for handling normal operation as well as a short circuit on the electrical network or transmission line. The discrete time controller 1 comprises a pulse width modulator 6, a voltage controller 8 and a short circuit controller 9. In contrast to the control structure according to FIG. 4 the mean output voltage V.sub.2 is not controlled as a function of the second measured output current I.sub.2 on the lines between the low-pass filter 5 of the grid forming inverter 3 and the transformer 7 but as a function of the first measured output current I.sub.1 on the lines between the output terminals of the power electronic devices 4 and the low-pass filter 5 of the inverter 3 and the desired droop control voltage {tilde over (V)}.sub.2.sup.d from the next control cascade.

[0104] In accordance with the cascaded control structure of FIG. 4 the inner loop consists of the voltage controller 8 and the unit 2 which comprises a DC-source 10, an inverter 3, a transformer 7 and a pulse width modulator 6. The primary winding 71 of the transformer 7 is connected to a low-pass filter 5 and the secondary winding 72 of the transformer 7 is connected to the bus bar B1 of the network or grid which may also contain inverters and conventional generators with a similar control structure as the controlled inverter 3. The inverter 3 includes controllable power electronic devices 31-36, the low pass filter 5 and the pulse width modulator 6 which provides switching pulses SP to the control terminals of the power electronic devices 31-36 depending on the measured input voltage V.sub.DC of the DC-source 10 and the desired mean value over one switching period of the input voltage V.sub.1.sup.dε custom-character .sup.3 on the power electronic side of the low-pass filter 5 provided by the output terminal of the voltage controller 8 which is used to control the output voltage V.sub.2 according to the desired reference voltage V.sub.2.sup.d.

[0105] The input terminals of the voltage controller 8 receive a first input signal corresponding to the output voltage V.sub.2 of the inverter 3 at the beginning of the calculations of the discrete time controller, a second input signal corresponding to the measured output current I.sub.1ε custom-character .sup.3 on the lines between the output terminals of the power electronic devices 31-36 and the low-pass filter 5 of the grid forming inverter 3.

[0106] The short circuit controller 9 is added to the inner loop for changing the reference voltage amplitude V.sub.2.sup.d ε custom-character .sup.3 of the inverter terminals. The short circuit controller 9 receives at its input terminals an input signal corresponding to the measured output current I.sub.1 on the lines between the output terminals of the power electronic devices 31-36 and the low-pass filter 5 of the grid forming inverter 3 and a desired droop control voltage {tilde over (V)}.sub.2.sup.d from the next control cascade. At its output terminal the short circuit controller provides a reference voltage V.sub.2.sup.d to an input terminal of the voltage controller 8.

[0107] In order to limit the short circuit current, the output voltage V.sub.2 on the terminals of the inverter 3 is reduced as a function of the first measured output current I.sub.1 on the lines between the output terminals of the power electronic devices 31-36 and the low-pass filter 5 of the inverter 3. Through the voltage controller 8 the desired voltage V.sub.2.sup.d=ƒ({tilde over (V)}.sub.2.sup.d, I.sub.1) is controlled, using the measured values for the voltage V.sub.2 and the current I.sub.1, such that V.sub.1.sup.d is changed and transformed to switching pulses SP from the pulse width modulator 6 for the power electronic devices 31-36.

[0108] The desired droop control voltage {tilde over (V)}.sub.2.sup.d is generated using droop control as described above to synchronize the inverters and achieve power sharing among the units 2.1 to 2.N according to FIG. 2.

[0109] FIG. 10 depicts a schematic circuit and block diagram of a third embodiment of a control structure of the discrete time controller 1 of the grid forming unit 2 for handling normal operation as well as a short circuit on the electrical network or transmission line. The discrete time controller 1 comprises a pulse width modulator 6, a voltage controller 8 and a short circuit controller 9. The input voltage of the inverter 3 is controlled as a function of the second measured output current I.sub.2 on the lines between the low-pass filter 5 of the inverter 3 and a transformer 7, an output voltage V.sub.2 of the inverter 3 and a desired droop control voltage {tilde over (V)}.sub.2.sup.d from the next control cascade.

[0110] The unit 2 comprises a DC-source 10, the inverter 3, the transformer 7 and a pulse width modulator 6. The primary winding 71 of the transformer 7 is connected to the low-pass filter 5 through a closed switch and the secondary winding 72 of the transformer 7 is connected to the electrical transmission line TL.sub.1 of the network or grid which may also contain inverters and conventional generators with a similar control structure as the controlled inverter 3. The inverter 3 includes controllable power electronic devices 31-36 and the low pass filter 5.

[0111] As with the control structure of FIGS. 4 and 9 the switching pulses SP provided by the pulse width modulator 6 to the control terminals of the power electronic devices 4 depend on the measured input voltage V.sub.DC of the DC-source and a desired input voltage V.sub.1.sup.dε custom-character .sup.3 on the power electronic side of the low-pass filter 5. However, unlike the cascaded control structures of FIGS. 4 and 9 the desired input voltage V.sub.1.sup.dε.sup.3 a is not provided by the output terminal of the voltage controller 8 but by an output of the short circuit controller 9 the input terminals of which receive both a first input signal corresponding to the second measured output current I.sub.2 on the lines between the low-pass filter 5 of the inverter 3 and the transformer 7 and a first reference input voltage {tilde over (V)}.sub.1.sup.d provided by the output of the voltage controller 8.

[0112] The input terminals of the voltage controller 8 receive both a first input signal corresponding to the output voltage V.sub.2 of the inverter 3, a second input signal corresponding to the second measured output current I.sub.2ε custom-character .sup.3 on the lines between the low-pass filter 5 of the inverter 3 and the transformer 7 and a third input signal corresponding to the desired droop control voltage {tilde over (V)}.sub.2.sup.d from the next control cascade.

[0113] Thus, in order to limit the short circuit current, the input voltage V.sub.1 on the power electronic elements 31-36 side of the filter 5 is reduced as a function of the second measured output current I.sub.2ε custom-character .sup.3 and the desired droop control voltage {tilde over (V)}.sub.2.sup.d generated using droop control as described above to synchronize the inverters 3.1 to 3.N and achieve power sharing among the units 2.1 to 2.N.

[0114] FIG. 11 is a schematic circuit and block diagram of a fourth embodiment of the control structure of the grid forming unit 2 which mainly corresponds to the control structure according to FIG. 10. The discrete time controller 1 for handling normal operation as well as a short circuit on the electrical network or transmission line comprises a pulse width modulator 6, a voltage controller 8 and a short circuit controller 9.

[0115] In accordance with the cascaded control structures of FIGS. 4, 9 and 10 the inner loop consists of the voltage controller 8 and the unit 2 which comprises a DC-source 10, an inverter 3, a transformer 7 and the pulse width modulator 6. The primary winding 71 of the transformer 7 is connected by a switch to the low-pass filter 5 and the secondary winding 72 of the transformer 7 is connected to the electrical bus B1 of the network or grid which may also contain inverters and synchronous generators with a similar control structure as the controlled inverter 3. The inverter 3 includes controllable power electronic devices 31-36 and the low pass filter 5. The pulse width modulator 6 provides switching pulses SP to the control terminals of the power electronic devices 4 depending on the measured input voltage V.sub.DC of the DC-source and the desired input voltage V.sub.1.sup.dε custom-character .sup.3 on the power electronic elements 31-36 side of the low-pass filter 5.

[0116] As with the control structure of FIG. 10 the desired input voltage V.sub.1.sup.dε custom-character .sup.3 is not provided by the output terminal of the voltage controller 8 but by an output of the short circuit controller 9 the input terminals of which receive both a first input signal corresponding to the first measured output current I.sub.1ε.sup.3 on the lines between the output terminals of the power electronic devices 31-36 and the low-pass filter 5 of the inverter 3 and a first reference input voltage {tilde over (V)}.sub.1.sup.d provided by the output of the voltage controller 8.

[0117] The input terminals of the voltage controller 8 receive both a first input signal corresponding to the output voltage V.sub.2 of the inverter 3, a second input signal corresponding to the first measured output current I.sub.1ε custom-character 3 on the lines between the output terminals of the power electronic devices 31-36 and the low-pass filter 5 of the inverter 3 and a third input signal corresponding to the desired droop control voltage {tilde over (V)}.sub.2.sup.d from the next control cascade.

[0118] In order to limit the short circuit current, the output voltage V.sub.1 on the power electronic side of the low-pass filter 5 is reduced as a function of the first measured output current I.sub.1ε custom-character .sup.3 and the desired droop control voltage {tilde over (V)}.sub.2.sup.d generated using droop control as described above to synchronize the inverters 3.1 to 3.N according to FIG. 2 and achieve power sharing among the units 2.1 to 2.N.

TABLE-US-00001 REFERENCE SIGNS 1 (discrete) time controller 2; 2.1-2.N (inverter) units 3; 3.1-3.N (grid forming, droop controlled) inverters 4.1-4.N conventional generator units 5 low-pass filter 6 (pulse width) modulator 7; 7.1-7.N transformers 8 voltage controller 9 short circuit controller 10; 10.1-10.N DC-source (storage units) 11 DC voltage sensor 12 current sensor 13 second voltage sensor 14, 15 protection switches 17 summing element 30 DC input capacitor 31-36 semiconductor switches 40.1-40.N conventional generation units 41.1-41.N Transformers of the corresponding conventional generation units 53 filter capacitor 51 filter inductance 52 filter resistor 71 primary winding of the transformer 72 secondary winding of the transformer B.sub.1-B.sub.N bus bar I.sub.1 first measured current |I.sub.1| first short circuit current amplitude I.sub.DC Current from DC source I.sub.2 second measured current |I.sub.2| Second measured current amplitude I.sub.2.sup.N Threshold current, where the short circuit handling starts I.sub.2.sup.K Short circuit current I.sub.2.sup.K1 Maximum short circuit current L.sub.1-L.sub.N loads PV.sub.1-PV.sub.N photovoltaic (solar) power units SC Short circuit SP Switching pulses TL.sub.1-TL.sub.N transmission lines V.sub.1 first output voltage V.sub.1.sup.d Desired mean voltage over one switching period {tilde over (V)}.sub.1.sup.d Desired voltage on power electronic terminals before short circuit handling V.sub.2 second measured voltage V.sub.2.sup.d desired reference voltage {tilde over (V)}.sub.2.sup.d desired droop control voltage ΔV.sub.2.sup.d second reference input voltage V.sub.DC DC capacitor voltage V.sup.N Nominal voltage WP.sub.1-WP.sub.N wind power units Z.sub.k Short circuit impedance Z.sub.v virtual impedance

SYSTEM FOR HANDLING SHORT CIRCUITS ON AN ELECTRICAL NETWORK

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Abstract

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