SYSTEMS AND METHODS FOR CONTROLLING MULTI-LEVEL DIODE-CLAMPED INVERTERS USING SPACE VECTOR PULSE WIDTH MODULATION (SVPWM)

Abstract

Control systems for a multi-level diode-clamped inverter and corresponding methods include a processor and a digital logic circuit forming a hybrid controller. The processor identifies sector and region locations based on a sampled reference voltage vector V* and angle θ.sub.e*. The processor then selects predefined switching sequences and pre-calculated turn-on time values based on the identified sector and region locations. The digital logic circuit generates PWM switching signals for driving power transistors of a multi-level diode-clamped inverter based on the turn-on time values and the selected switching sequences. The control system takes care of the existing capacitor voltage balancing issues of multi-level diode-clamped inverters while supplying both active and reactive power to an IT load. Using the control system, one can generate a symmetrical PWM signal that fully covers the linear under-modulation region.

Claims

1. A control system for a multi-level inverter, comprising: a digital logic circuit comprising: a plurality of digital logic comparators including a first comparator and a second comparator; a plurality of inverters coupled to respective outputs of a respective plurality of comparators, the plurality of inverters including a first inverter; and a plurality of AND gates including an AND gate, the AND gate having a first input and a second input, the first input coupled to the output of the first inverter and the second input coupled to the output of the second comparator; a digital up/down counter coupled to first inputs of the plurality of comparators, the up/down counter counting from 0 to Ts/2 and then from Ts/2 to 0, where Ts is a sampling period; and a processor and memory configured to: identify a sector location based on an actual angle of a reference voltage vector; convert the actual angle into a converted angle located in a first sector; identify a reference region location based on the magnitude of the reference voltage vector and the converted angle in the first sector; select a switching sequence and turn-on time values based on the corresponding actual region location and actual sector; transmit turn-on time values to second inputs of the plurality of comparators; and provide the output of the first comparator, the outputs of the plurality of AND gates, and the output of a last inverter of the plurality of inverters as switching signals, which are transmitted to gate drivers for driving power transistors of the multi-level inverter.

2. The control system of claim 1, wherein the logic circuit is a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC).

3. The control system of claim 1, wherein the processor and memory are implemented by a digital signal processor (DSP).

4. The control system of claim 1, wherein the number of the plurality of comparators and the number of the plurality of inverters is one less than the number of levels of the multi-level inverter.

5. The control system of claim 4, wherein the number of the plurality of AND gates is one less than the number of the plurality of comparators.

6. The control system of claim 1, wherein the processor and memory are further configured to: convert the reference voltage vector and the converted angle into X and Y coordinate point values in first sector; and identify a region location based on the X and Y coordinate point values.

7. The control system of claim 6, wherein the identifying a region location includes comparing the X and Y coordinate point values to segments of triangles, which represent regions, in a vector space.

8. The control system of claim 6, wherein the turn-on time values and switching sequence are predetermined for each sector and region, and stored in a look-up table stored in memory.

9. The control system of claim 1, wherein the sector locations are sectors A-F and the first sector is sector A.

10. The control system of claim 1, wherein the multi-level inverter is a five-level inverter, wherein the plurality of comparators further include a third comparator and a fourth comparator, wherein the plurality of inverters further include a second inverter, a third inverter, and a fourth inverter, wherein the plurality of AND gates further include a second AND gate, and a third AND gate, wherein a first input of the second AND gate is coupled to the output of the second inverter and a second input of the second AND gate is coupled to the output of the third comparator, wherein a first input of the third AND gate is coupled to the output of the third inverter and a second input of the third AND gate is coupled to the output of the fourth comparator, and wherein the output of the first comparator, the outputs of the plurality of AND gates, and the output of the fourth inverter provide the switching signals for an IGBT driver of a five-level inverter.

11. The control system of claim 1, wherein the multi-level inverter is a four-level inverter, wherein the plurality of comparators further include a third comparator, wherein the plurality of inverters further include a second inverter and a third inverter, wherein the plurality of AND gates further include a second AND gate, wherein a first input of the second AND gate is coupled to the output of the second inverter and a second input of the second AND gate is coupled to the output of the third comparator, wherein the output of the first comparator, the outputs of the plurality of AND gates, and the output of the third inverter provide the switching signals.

12. A method of controlling a multi-level inverter, comprising: identifying a sector location based on an actual angle of a reference voltage vector; converting the actual angle into a converted angle located in a first sector; identifying a region location based on the magnitude of the reference voltage vector and the converted angle in the first sector; selecting a switching sequence and a plurality of turn-on time values based on the corresponding region location in actual sector of reference voltage vector; transmitting the turn-on time values to second inputs of the plurality of comparators to generate switching signals, which are transmitted to gate drivers for driving power transistors of the multi-level inverter; comparing each of the plurality of turn-on signals to a digital up/down counter signal to obtain a plurality of comparison signals including a first comparison signal and a second comparison signal; inverting the plurality of comparison signals to obtain a plurality of inverted signals including a first inverted signal; and performing a logical AND operation on the first inverted signal and the second comparison signal to obtain a switching signal, which is transmitted to a gate driver for driving a power transistor of the multi-level inverter.

13. The method of claim 12, further comprising: converting the reference voltage vector and the converted angle into X and Y coordinate point values; and identifying a region location based on the X and Y coordinate point values.

14. The method of claim 13, wherein the identifying a region location includes comparing the X and Y coordinate point values to segments of triangles, which represent regions, in a vector space.

15. The method of claim 13, wherein the turn-on time values and switching sequences are predetermined for each sector and region, and stored in a look-up table stored in memory.

16. The method of claim 12, wherein the first comparison signal is a first switching signal, wherein the logical AND operation is performed on the first inverted signal and the second comparison signal to obtain a second switching signal, wherein the plurality of comparison signals further include a third comparison signal and a fourth comparison signal, wherein the plurality of inverted signals further include a second inverted signal, a third inverted signal, and a fourth inverted signal, wherein the method further comprises: performing a second logical AND operation on the second inverted signal and the third comparison signal to obtain a third switching signal; and performing a second logical AND operation on the second inverted signal and the third comparison signal to obtain a fourth switching signal, and wherein the fourth inverted signal is a fifth switching signal.

17. The method of claim 16, wherein the first switching signal corresponds to either a P.sub.2 or N.sub.2 switching state, wherein the second switching signal corresponds to either a P.sub.1 or N.sub.1 switching state, wherein the third switching signal corresponds to an O switching state, wherein the fourth switching signal corresponds to either an N.sub.1 or P.sub.1 switching state, and wherein the fifth switching signal corresponds to either an N.sub.2 or P.sub.2 switching state.

18. An energy storage system comprising: an energy storage device; a DC-DC converter coupled to the energy storage device; a multi-level inverter coupled to the DC-DC converter; and a controller for the multi-level inverter, the controller comprising: a digital logic circuit comprising: a plurality of comparators including a first comparator and a second comparator; a plurality of inverters coupled to respective outputs of a respective plurality of comparators, the plurality of inverters including a first inverter; and a plurality of AND gates including a first AND gate, the first AND gate having a first input and a second input, the first input coupled to the output of the first inverter and the second input coupled to the output of the second comparator; a counter coupled to first inputs of the plurality of comparators; and a processor and memory configured to: identify a sector location based on an actual angle of a reference voltage vector; convert the actual angle into a converted angle located in a first sector; identify a region location based on the magnitude of the reference voltage vector and the converted angle in the first sector; select a switching sequence and turn-on signal values based on the corresponding region and actual reference voltage vector location; transmit turn-on signal values to second inputs of the plurality of comparators; and provide the output of the first comparator, the outputs of the plurality of AND gates, and the output of a last inverter of the plurality of inverters as switching signals, which are transmitted to gate drivers for driving power transistors of the multi-level inverter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG. 1 is a system block diagram of a data center power supply system according to embodiments of the present disclosure;

[0021] FIG. 2 is a circuit diagram of a three-phase five-level diode-clamped inverter according to embodiments of the present disclosure;

[0022] FIGS. 3A and 3B show a space vector diagram illustrating space voltage vectors of a three-phase five-level inverter according to embodiments of the present disclosure;

[0023] FIG. 4 is a space vector diagram illustrating space vectors indicating regions and switching times according to embodiments of the present disclosure;

[0024] FIG. 5 is a space vector diagram illustrating switching states and switching times of region 1 and sectors A-F for an example mode according to embodiments of the present disclosure;

[0025] FIG. 6 is a waveform diagram illustrating switching states for one phase of sectors A-F and region 1;

[0026] FIG. 7 is a waveform diagram illustrating a sequence of switching states of the three phases in regions 1-4 of sector A according to embodiments of the present disclosure;

[0027] FIGS. 8-12 are waveform diagrams illustrating generation of turn-on time signals and switching logic signals according to embodiments of the present disclosure;

[0028] FIG. 13 is a graphical diagram illustrating turn-on time values for one phase according to embodiments of the present disclosure;

[0029] FIG. 14 is a digital logic circuit for generating switching logic signals to drive power transistors of a multi-level diode-clamped inverter according to embodiments of the present disclosure;

[0030] FIG. 15 is a flow diagram of a method of identifying region and sector locations of a voltage vector according to embodiments of the present disclosure;

[0031] FIG. 16 is a SVPWM controller for a five-level diode-clamped inverter according to embodiments of the present disclosure; and

[0032] FIG. 17 is a flow diagram of a method of controlling a multi-level inverter according to embodiments of the present disclosure.

DETAILED DESCRIPTION

[0033] The present disclosure relates to a processor and digital logic circuit-based hybrid controller and its implementation of SVPWM control strategies for multi-level diode-clamped inverters, e.g., multi-level diode-clamped inverters for Multi-level Medium Voltage Data Center Static Synchronous Compensator (DCSTATCOM) or Multi-level Medium Voltage Uninterruptable Power Supply (MVUPS) with battery energy storage for a data center (DC) load connected at a medium voltage (MV) level. MV operation reduces overall losses of DC components and hence improves overall efficiency of the system.

[0034] A control system of the present disclosure includes a digital logic circuit, such as a Field Programmable Gate Array (FPGA), and a processor, such as a digital signal processor (DSP) or a microprocessor. The processor samples a reference voltage vector V* and an angle θ.sub.e*, and identifies a sector and region based on the sampled reference voltage vector V* and angle θ.sub.e*. The processor then selects predefined switching sequences and pre-calculated turn-on time values based on the identified sector and region location of the reference voltage vector V*. The digital logic circuit generates PWM switching signals for driving power transistors of a multi-level diode-clamped inverter based on the turn-on time values and the selected switching sequences.

[0035] For multi-level inverters, the SVPWM control strategy is more suitable in comparison to sinusoidal PWM as the SVPWM control strategy offers significant flexibility to synthesize switching sequences of waveforms and is suitable for digital implementation by a processor, e.g., a DSP, and a digital logic circuit, e.g., an FPGA, forming a hybrid controller.

[0036] In SVPWM, the inverter voltage vectors, which correspond to the apexes of the triangle, which includes the reference voltage vector, are generally selected to minimize harmonics at the output in comparison to sinusoidal PWM. SVPWM also provides larger under modulation range that extends the modulation factor to 90.7% from the traditional value of 78.5% in sinusoidal PWM.

[0037] In the control systems of the present disclosure, a hybrid controller, which includes a processor and a digital logic circuit, is utilized to implement various control blocks to carry out the SVPWM control strategy. The PWM signal generation task for providing PWM switching signals to the gate driver for driving a power transistor is carried out by a digital logic circuit, e.g., an FPGA. The remaining tasks are performed by a processor, e.g., a DSP. Therefore, a less expensive hybrid processor and digital logic controller is used to implement an overall complex control strategy. Also, the control tasks are divided between a processor and a digital logic circuit to achieve a faster transient response at lower cost.

[0038] The systems and methods of the present disclosure may be applied to a Multi-level Medium Voltage Data Center Static Synchronous Compensator (DCSTATCOM) or Multi-level Medium Voltage Uninterruptable Power Supply (MVUPS), as described in U.S. application Ser. No. 14/481,904, entitled “Multi-level Medium Voltage Data Center Static Synchronous Compensator (DCSTATCOM) for Active and Reactive Power Control of Data Centers connected with Grid Energy Storage and Smart Green Distributed Energy Sources”, filed on Sep. 9, 2014, and U.S. application Ser. No. 14/594,073, entitled “Transformerless Multi-level Medium Voltage Uninterruptable Power Supply (UPS) System”, filed on Jan. 9, 2015, each of which are incorporated herein by reference in their entireties.

[0039] FIG. 1 is a system block diagram of a DCSTATCOM or MVUPS topology with a transfer switch 112 connected between a utility and a generator 110, a static transfer switch 114, a transformer 116, and a DC IT load 118. The DCSTATCOM or MVUPS systems include a battery energy storage block 120, a battery management system (BMS) controller 130, a bi-directional multi-level (ML) DC-DC converter 122, a DC-DC converter controller 124, a ML inverter 124 outputting medium voltage AC (V.sub.INV) at the inverter output, and an SVPWM inverter controller 134 for controlling the ML inverter 124. As described in more detail below, the SVPWM inverter controller 134 includes a processor and a digital logic circuit for generating PWM switching signals, which are applied to driver circuits (not shown) for driving power transistors (not shown) of the ML inverter 124.

[0040] FIG. 2 is a circuit block diagram of a five-level diode-clamped inverter, which may be used as the ML inverter 124, which converts DC voltage V.sub.DC output from the converter 122 to three-phase AC voltage V.sub.AC. The five-level inverter includes power transistors or switches S.sub.1U-S.sub.8U, S.sub.1V-S.sub.8V, and S.sub.1W-S.sub.8W, and diodes connected together in a diode-clamped configuration to generate three phases U, V, and W of an AC voltage V.sub.AC. State O represents neutral point balancing so that the average current injected at O should be zero. States P1 and P2 represent positive bus voltages. States N1 and N2 represent negative bus voltages.

[0041] Switches S.sub.1U-S.sub.8U, S.sub.1V-S.sub.8V, and S.sub.1W-S.sub.8W may be power transistors, such as IGBTs. IGBTs allow for higher voltages or currents and higher switching frequencies. The five-level inverter illustrated in FIG. 2 allows for sharing of the high voltage among the switches S.sub.1U-S.sub.8U, S.sub.1V-S.sub.8V, and S.sub.1W-S.sub.8W, and reduces harmonic distortion.

[0042] The complexity of an inverter control system increases as the inverter level increases from three to five or above. A three-phase five-level diode-clamped inverter illustrated in FIG. 2 is complex due to a high number of switching states, i.e., 5.sup.3=125 switching states, in comparison to a three-phase three-level inverter with a lower number of switching states, i.e., 3.sup.3=27 switching states. The inverter must have a very fast response time (in micro-seconds) to have appropriate control operation and safety aspects for IGBT devices. Also, the SVPWM strategy needs to perform many on-line calculations due to its large number of switching states (e.g., 125 for a five-level inverter) and large number of operating regions/triangles (e.g., 96 for a five-level inverter). Therefore, in embodiments, the control systems of the present disclosure incorporate a digital logic circuit, such as an FPGA, to perform partial logic functions. The digital logic circuit may form part of a hybrid controller, which includes a processor and the digital logic circuit. This hybrid controller is well suited to implement SVPWM control because it allows for much larger bandwidth control and provides faster response times.

[0043] The switching states of the five-level inverter are summarized in Table 1, where X is one of the phases U, V, and W; and P.sub.2 (+V.sub.DC/2), P.sub.1 (+V.sub.DC/4), O (0 V.sub.AC), N.sub.1 (−V.sub.DC/4), and N.sub.2 (−V.sub.DC/2) are DC-bus points as shown in FIG. 2.

TABLE-US-00001 TABLE 1 Switching States S.sub.1X S.sub.2X S.sub.3X S.sub.4X S.sub.5X S.sub.6X S.sub.7X S.sub.8X V.sub.XO P.sub.2 ON ON ON ON OFF OFF OFF OFF +V.sub.DC/2 P.sub.1 OFF ON ON ON ON OFF OFF OFF +V.sub.DC/4 O OFF OFF ON ON ON ON OFF OFF 0 N.sub.1 OFF OFF OFF ON ON ON ON OFF −V.sub.DC/4 N.sub.2 OFF OFF OFF OFF ON ON ON ON −V.sub.DC/2

[0044] Referring to Table 1, in conjunction with FIG. 2, phase U, for example, is in state P2 (positive bus voltage) when the switches S.sub.1U-S.sub.4U are closed or “ON”, and switches S.sub.5U-S.sub.8U are open or “OFF”. The phase V is in state P1 (positive bus voltage that is less than P2) when switches S.sub.1U and S.sub.6U-S.sub.8U are open or OFF, and switches S.sub.2U-S.sub.5U are closed or ON. The phase U is in state O when switches S.sub.1U, S.sub.2U, S.sub.7U, and S.sub.8U are open or OFF and switches S.sub.3U-S.sub.6U are closed or ON.

[0045] The phase U is in state N1, which corresponds to a negative bus voltage that is greater than a negative bus voltage that corresponds to state N2, when switches S.sub.1U-S.sub.3U and S.sub.8U are turned off (i.e., open) and switches S.sub.4U-S.sub.7U are turned on (i.e., closed). The phase U is in state N2, which corresponds to a negative bus voltage that is less than the negative bus voltage that corresponds to state N1, when switches S.sub.1U-S.sub.4U are turned off (i.e., open) and switches S.sub.5U-S.sub.8U are turned on (i.e., closed).

[0046] FIGS. 3A and 3B show a space vector diagram illustrating space voltage vectors of a five-level diode-clamped inverter with 125 switching states and 96 operational triangles. There are 120 active switching states and the remaining 5 are zero states (P.sub.2P.sub.2P.sub.2, P.sub.1P.sub.1P.sub.1, OOO, N.sub.1N.sub.1N.sub.1, N.sub.2N.sub.2N.sub.2) that lie at the origin. FIGS. 3A and 3B also show a hexagon having six sectors—sectors A-F, and each sector has sixteen regions—regions 1-16, giving altogether 96 regions of operation.

[0047] In embodiments, the operation of a multi-level inverter, such as the multi-level inverter of FIG. 2, may be divided into multiple modes. As shown in FIGS. 3A and 3B, the operation is divided into four modes—modes 1-4. In Mode 1 (301), the command voltage vector V* trajectory covers region 1 of all six sectors, e.g., sectors A-F. In Mode 2 (302), the command voltage vector V* trajectory covers regions 2, 3, and 4 of all sectors. In Mode 3 (303), the command voltage vector V* trajectory covers regions 5, 6, 7, 8, and 9 of all sectors. In Mode 4 (304), the command voltage vector V* trajectory covers regions 10, 11, 12, 13, 14, 15, and 16 of all sectors.

Operational Modes

[0048] FIG. 4 is a space vector diagram illustrating a sector A triangle formed by voltage vectors V.sub.0, V.sub.10, and V.sub.14. In Space Vector Pulse Width Modulation (SVPWM), the inverter voltage vectors V.sub.3, V.sub.6, and V.sub.7, which correspond to the apexes of the region 7 of the sector A triangle, which includes the reference or command voltage vector (V*) 412, are generally selected to minimize harmonics at the output of the multi-level inverter. If the command voltage vector V* lies in region 7 (422), as shown in FIG. 4, the following two equations are satisfied for SVPWM:

V.sub.6T.sub.a+V.sub.3T.sub.b+T.sub.c=V*T.sub.S  (1)

T.sub.a+T.sub.b+T.sub.c=T.sub.S  (2)

where T.sub.a, T.sub.b, and T.sub.c are respective time intervals of the nearest three voltage vectors in a particular triangle, and T.sub.S is the sampling time.

[0049] FIG. 5 is a space vector diagram illustrating switching states and switching times of the three phases of region 1 and sectors A-F in Mode 1.

[0050] In embodiments, the switching sequence is pre-defined (and may be stored in a look-up table in memory) and depends on the location of reference voltage vector (V*) in any particular region or triangle. The sequence in opposite sectors, e.g., A-D, B-E, and C-F, is selected to be of a complimentary nature to achieve capacitor neutral voltage balancing.

[0051] FIG. 6 is a waveform diagram showing the construction of AC voltage waveform patterns based on the sequences of switching states (P.sub.2, P.sub.1, O, N.sub.1, N.sub.2) of the U phase in region 1 of sectors A-F (U.sub.A1-U.sub.F1) for Mode 1 operation. The sequences of switching states are obtained from the space vector diagram of FIG. 5 where the switching states for the three phases are defined at each of the voltage vectors. The first row 501 of switching states for voltage vector V.sub.0 are switching states for the U phase, the second row 502 of switching states for voltage vector V.sub.0 are switching states for the V phase, and the third row 503 of switching states for voltage vector V.sub.0 are switching states for the W phase. Likewise, the first row 511 of switching states for voltage vector V.sub.1 are switching states for the U phase, the second row 512 of switching states for voltage vector V.sub.1 are switching states for the V phase, and the third row 513 of switching states for voltage vector V.sub.1 are switching states for the W phase. Further, the first row 521 of switching states for voltage vector V.sub.4 are switching states for the U phase, the second row 522 of switching states for voltage vector V.sub.4 are switching states for the V phase, and the third row 523 of switching states for voltage vector V.sub.4 are switching states for the W phase.

[0052] To construct the first half of the sequence of switching states for phase U, sector A, region 1 (U.sub.A1) (611a) over sampling period Ts/2 (601), switching states are obtained from each of the voltage vectors in a counter-clockwise direction. The switching states are obtained from right to left in the first row of switching states assigned to each of the voltage vectors.

[0053] For example, the first switching state of the sequence U.sub.A1 is the right-most switching state in the first row 501 for voltage vector V.sub.0, which is N.sub.2. The second switching state of the sequence U.sub.A1 is the right-most switching state in the first row 511 for voltage vector V.sub.1, which is N.sub.1. The third switching state of the sequence U.sub.A1 is the right-most switching state in the first row 521 for voltage vector V.sub.4, which is N.sub.1. The fourth switching state of the sequence U.sub.A1 is the second switching state from the right in the first row 501 for voltage vector V.sub.0, which is N.sub.1. The fifth switching state of the sequence U.sub.A1 is the second switching state from the right in the first row 511 for voltage vector V.sub.1, which is 0. The sixth switching state of the sequence U.sub.A1 is the second switching state from the right in the first row 521 for voltage vector V.sub.4, which is 0. The seventh switching state of the sequence U.sub.A1 is the third switching state from the right in the first row 501 for voltage vector V.sub.0, which is O.

[0054] The eighth switching state of the sequence U.sub.A1 is the third switching state from the right in the first row 511 for voltage vector V.sub.1, which is P.sub.1. The ninth switching state of the sequence U.sub.A1 is the third switching state from the right in the first row 511 for voltage vector V.sub.1, which is P.sub.1. The tenth switching state of the sequence U.sub.A1 is the third switching state from the right in the first row 521 for voltage vector V.sub.4, which is P.sub.1. The eleventh switching state of the sequence U.sub.A1 is the fourth switching state from the right in the first row 501 for voltage vector V.sub.0, which is P.sub.1.

[0055] The twelfth switching state of the sequence U.sub.A1 is the fourth switching state from the right in the first row 511 for voltage vector V.sub.1, which is P.sub.2. The thirteenth switching state of the sequence U.sub.A1 is the fourth switching state from the right in the first row 521 for voltage vector V.sub.4, which is P.sub.2. The fourteenth switching state of the sequence U.sub.A1 is the fifth switching state from the right in the first row 501 for voltage vector V.sub.0, which is P.sub.2.

[0056] To construct the second half of the sequence of switching states for phase U, sector A, region 1 (U.sub.A1) (611b) over sampling period Ts/2 (602), switching states are obtained from each of the voltage vectors in a clockwise direction. The switching states are obtained from left to right in the first row of switching states assigned to the voltage vectors.

[0057] FIG. 7 is a waveform diagram illustrating the construction of AC voltage waveform patterns based on the vector space diagram of FIGS. 3A and 3B in a manner similar to that described above with respect to FIG. 6. FIG. 7 shows AC voltage waveform patterns for a sequence of switching states, e.g., P.sub.2, P.sub.1, O, N.sub.1, N.sub.2, of the three phases U, V, and W in regions 1-4 of sector A for operational modes 1 and 2. The AC voltage waveform patterns include waveform patterns U.sub.A1 (611), V.sub.A1 (712), and W.sub.A1 (713), which were constructed based on the switching states obtained from region 1 in sector A.

Determination of Turn-on Times

[0058] PWM waveforms are established once switching turn-on time information is determined based on the following equations.

[0059] The turn-on time (T) is the sum function of weighted duty cycles T.sub.a, T.sub.b, and T.sub.c. Turn-on time T can be represented by the following equation:

T=f(K.sub.T-ON of (T.sub.a,T.sub.b, and T.sub.a)),  (3)

where K.sub.T-ON is a coefficient of time-weighted duty cycles of switching times T.sub.a, T.sub.b, and T.sub.c. Switching times T.sub.a, T.sub.b, and T.sub.c may be determined based on the ‘average value’ principle, which simplifies the implementation.

[0060] FIG. 8 is a waveform diagram illustrating generation of turn-on time signals (U.sub.A1P2, U.sub.A1P1, U.sub.A1O, U.sub.A1N1) and switching logic signals (S.sub.UA1P2, S.sub.UA1P1, S.sub.UA1O, S.sub.UA1N1, S.sub.UA1N2) of respective P.sub.2, P.sub.1, O, N.sub.1, N.sub.2 voltage levels for waveform U.sub.A1 of sector A and region 1. As shown in FIG. 8, the switching pattern during the first T.sub.S/2 interval is repeated inversely in the next T.sub.S/2 interval with appropriate segmentation of T.sub.a, T.sub.b, and T.sub.c.

[0061] Capacitor voltage balancing of multi-level diode-clamped voltage source inverters (VSI) of STATCOM and MVUPS is an issue as it supplies or absorbs both active and reactive power. Capacitor voltage balancing becomes more difficult as the numbers of capacitor to be balanced is increased, e.g., from two (for three-level) to four (for five-level). Thus, switching sequences in opposite sectors (viz., A-D, B-E, and C-F) are selected to be of a complimentary nature to achieve capacitor neutral voltage balancing. The time interval duty cycles T.sub.a, T.sub.b, T.sub.c are distributed appropriately so as to generate symmetrical PWM waves with capacitor neutral point voltage balancing.

[0062] The turn-on time T.sub.1 to establish the turn-on time signal (U.sub.A1P2) of the P.sub.2 voltage level is calculated as follows:

T.sub.1=K.sub.T-ON1-a-A1(T.sub.a)K.sub.T-ON1-b-A1(T.sub.b)K.sub.T-ON1-c-A1(T.sub.a),  (3a)

where K.sub.T-ON1-a-A1 is a coefficient of time-weighted duty cycle T.sub.a, K.sub.T-ON1-b-A1 is a coefficient of time-weighted duty cycle T.sub.b, and K.sub.T-ON1-c-A1 is a coefficient of time-weighted duty cycle T.sub.c of Sector A and Region 1.

[0063] The K.sub.T-ON1-a-A1 value may be calculated as ⅜ (=⅛+⅛+⅛), the K.sub.T-ON1-b-A1 value may be calculated as ⅖ (= 1/10+ 1/10+ 1/10+ 1/10), and the K.sub.T-ON1-c-A1 value may be calculated as ⅜ (=⅛+⅛+⅛), as shown in FIG. 8.

[0064] Switching times (T.sub.a, T.sub.b, and T.sub.c) are determined based on the ‘average value’ principle. Therefore,

T.sub.1=⅜*T.sub.S/3+⅖*T.sub.S/3+⅜*T.sub.S/3=0.76*T.sub.S/2  (3a1)

[0065] The turn-on time T.sub.2 to establish the turn-on time signal (U.sub.A1P1) of the P.sub.1 voltage level is calculated as follows:

T.sub.2=K.sub.T-ON2-a-A1(T.sub.a)+K.sub.T-ON2-b-A1(T.sub.b)+K.sub.T-ON2-c-A1(T.sub.c),  (3b)

where K.sub.T-ON2-a-A1 is a coefficient of time-weighted duty cycle T.sub.a, K.sub.T-ON2-b-A1 is a coefficient of time-weighted duty cycle T.sub.b, and K.sub.T-ON2-c-A1 is a coefficient of time-weighted duty cycle T.sub.c of Sector A and Region 1.

[0066] The K.sub.T-ON2-a-A1 value may be calculated as ¼ (=⅛+⅛), the K.sub.T-ON2-b-A1 value may be calculated as 3/10 (= 1/10+ 1/10+ 1/10), and the K.sub.T-ON2-c-A1 value may be calculated as ¼ (=⅛+⅛), as shown in FIG. 8.

[0067] Switching times (T.sub.a, T.sub.b, and T.sub.c) are determined based on the ‘average value’ principle. Therefore,

T.sub.2=¼*T.sub.S/3+ 3/10*T.sub.S/3+¼*T.sub.S/3=0.53*T.sub.S/2.  (3b1)

Similarly, T.sub.3 for U.sub.A1O of the 0 voltage level and T.sub.4 for U.sub.A1N1 of the N.sub.1 voltage level are determined for waveform U.sub.A1 of Sector A and Region 1.

[0068] After the turn-on time values are calculated, they may be stored in memory and used to generate the switching logic signals. As shown in FIG. 8, an up/down counter signal 805 starts below switching time T.sub.4 (e.g., time equal to zero), increases through switching times T.sub.4-T.sub.1 before reaching T.sub.S/2, then, after reaching T.sub.S/2, decreases through switching times T.sub.1-T.sub.4. Switching times T.sub.1-T.sub.4 are compared to the up/down counter signal 805, e.g., using comparators 1402-1408, respectively of FIG. 14, to obtain the U.sub.A1P2 signal 810, the U.sub.A1P1 signal 814, the U.sub.A1O signal 820, and the U.sub.A1N1 signal 826. The U.sub.A1P2 signal 810 is used as the switching signal S.sub.UA1P2. The U.sub.A1P2 signal 810, the U.sub.A1P1 signal 814, the U.sub.A1O signal 820, and the U.sub.A1N1 signal 826, are then inverted, e.g., by the inverters 1412-1418, respectively of FIG. 14, to obtain the IU.sub.A1P2 signal 812, the IU.sub.A1P1 signal 818, the IU.sub.A1O signal 824, and the IU.sub.A1N1 signal 830. The IU.sub.A1N1 signal 830 is used as the switching signal S.sub.UA1N1. Then, the Boolean AND operation is performed on the IU.sub.A1P2 signal 812 and the U.sub.A1P1 signal 814, e.g., using the AND gate 1422 of FIG. 14, to obtain the S.sub.UA1P1 switching signal 816. The Boolean AND operation is also performed on the IU.sub.A1P1 signal 818 and the U.sub.A1O signal 820, e.g., using the AND gate 1424 of FIG. 14, to obtain the S.sub.UA1O switching signal 822. The Boolean AND operation is further performed on the IU.sub.A1O signal 824 and the U.sub.A1N1 signal 826, e.g., using the AND gate 1426 of FIG. 14, to obtain the S.sub.UA1N1 switching signal 828.

[0069] FIG. 9 is a waveform diagram illustrating the generation of turn-on time signals (U.sub.B1N2, U.sub.B1N1, U.sub.B1O, U.sub.B1P1) and switching logic signals (S.sub.UB1N2, S.sub.UB1N1, S.sub.UB1O, S.sub.UB1P1, S.sub.UB1P2) of respective N.sub.2, N.sub.1, O, P.sub.1, P.sub.2 voltage levels for waveform U.sub.B1 of sector B and Region 1. As shown in FIG. 9, the switching pattern during the first T.sub.S/2 interval 601 is repeated inversely in the next T.sub.S/2 interval 602 with appropriate segmentation of T.sub.a, T.sub.b, and T.sub.c.

[0070] The turn-on time value T.sub.1 to establish the turn-on time signal (U.sub.B1N2) of N.sub.2 voltage level may be calculated as follows:

T.sub.1=K.sub.T-ON1-a-B1(T.sub.a)+K.sub.T-ON1-b-B1(T.sub.b)+K.sub.T-ON1-c-B1(T.sub.a),  (4a)

where K.sub.T-ON1-a-B1 is a coefficient of the time-weighted duty cycle T.sub.a, K.sub.T-ON1-b-B1 is a coefficient of the time-weighted duty cycle T.sub.b, and K.sub.T-ON1-c-B1 is a coefficient of time-weighted duty cycle T.sub.c of Sector B and Region 1.

[0071] The K.sub.T-ON1-a-B1 value may be calculated as ⅜ (=⅛+⅛+⅛), the K.sub.T-ON1-b-B1 value may be calculated as ⅖ (= 1/10+ 1/10+ 1/10+ 1/10), and the K.sub.T-ON1-c-B1 value may be calculated as (⅛+⅛+⅛+⅛=) ½ as shown in FIG. 9.

[0072] Switching times T.sub.a, T.sub.b, and T.sub.c are determined based on the average value principle. Therefore,

T.sub.1=⅜*T.sub.S/3+⅖*T.sub.S/3+½*T.sub.S/3=0.85*T.sub.S/2  (4a1)

[0073] The turn-on time value T.sub.2 to establish turn-on time signal U.sub.B1N1 of N.sub.1 voltage level is calculated as follows:

T.sub.2=K.sub.T-ON2-a-B1(T.sub.a)+K.sub.T-ON2-b-B1(T.sub.b)K.sub.T-ON2-c-B1(T.sub.a),  (4b)

where K.sub.T-ON2-a-B1 is a coefficient of time-weighted duty cycle T.sub.a, K.sub.T-ON2-b-B1 is a coefficient of time-weighted duty cycle T.sub.b, and K.sub.T-ON2-c-B1 is a coefficient of time-weighted duty cycle T.sub.c of Sector B and Region 1.

[0074] The K.sub.T-ON2-a-B1 value may be calculated as ¼ (=⅛+⅛), the K.sub.T-ON2-b-B1 value may be calculated as 3/10 (= 1/10+ 1/10+ 1/10) and the K.sub.T-ON2-c-B1 value may be calculated as ⅜ (=⅛+⅛+⅛) as shown in FIG. 9.

[0075] Switching times T.sub.a, T.sub.b, and T.sub.c are determined based on the average value principle. Therefore,

T.sub.2=¼*T.sub.S/3+ 3/10*T.sub.S/3+⅜*T.sub.S/3=0.61*T.sub.S/2.  (4b1)

[0076] Similarly, T.sub.3 for U.sub.B1O of the 0 voltage level and T.sub.4 for U.sub.B1P1 of the P.sub.1 voltage are determined for waveform U.sub.B1 of Sector B and Region 1.

[0077] After the turn-on time values are calculated, they may be stored in memory and used to generate the switching logic signals. As shown in FIG. 9, the up/down counter signal 805 starts below switching time T.sub.4 (e.g., a time equal to zero), increases through switching times T.sub.4-T.sub.1 before reaching T.sub.S/2, then, after reaching T.sub.S/2, decreases through switching times T.sub.1-T.sub.4. Switching times T.sub.1-T.sub.4 are compared to the up/down counter signal 805, e.g., using comparators 1402-1408, respectively of FIG. 14, to obtain the U.sub.B1N2 signal 910, the U.sub.B1N1 signal 914, the U.sub.B1O signal 920, and the U.sub.B1P1 signal 926. The U.sub.B1N2 signal 910 is used as the switching signal S.sub.UB1N2.

[0078] The U.sub.B1N2 signal 910, the U.sub.B1N1 signal 914, the U.sub.B1O signal 920, and the U.sub.B1P1 signal 926, are then inverted, e.g., by the inverters 1412-1418, respectively of FIG. 14, to obtain the IU.sub.B1N2 signal 912, the IU.sub.B1N1 signal 918, the IU.sub.B1O signal 924, and the IU.sub.B1P1 signal 930. The IU.sub.B1P1 signal 930 is used as the switching signal S.sub.UB1P1. Then, the Boolean AND operation is performed on the IU.sub.B1N2 signal 912 and the U.sub.B1N1 signal 914, e.g., using the AND gate 1422 of FIG. 14, to obtain the S.sub.UB1N1 switching signal 916. The Boolean AND operation is also performed on the IU.sub.B1N1 signal 918 and the U.sub.B10 signal 920, e.g., using the AND gate 1424 of FIG. 14, to obtain the S.sub.UB1O switching signal 922. The Boolean AND operation is further performed on the IU.sub.B1O signal 924 and the U.sub.B1P1 signal 926, e.g., using the AND gate 1426 of FIG. 14, to obtain the S.sub.UB1P1 switching signal 928.

[0079] FIG. 10 is a waveform diagram illustrating the generation of turn-on time signals U.sub.A2P2, U.sub.A2P1, U.sub.A2O and switching logic signals S.sub.UA2P2, S.sub.UA2P1, S.sub.UA2O, S.sub.UA2N1 of the respective P.sub.2, P.sub.1, O, N.sub.1 voltage level for waveform U of Sector A and Region 2.

[0080] As shown in FIG. 10, the up/down counter signal 805 starts below switching time T.sub.3, increases through switching times T.sub.3-T.sub.1 before reaching T.sub.S/2, then, after reaching T.sub.S/2, decreases through switching times T.sub.1-T.sub.3. Switching times T.sub.1-T.sub.3 are compared to the up/down counter signal 805, e.g., using comparators 1402-1406, respectively of FIG. 14, to obtain the U.sub.A2P2 signal 1010, the U.sub.A2P1 signal 1014, and the U.sub.A2O signal 1020. The U.sub.A2P2 signal 1010 is used as the switching signal S.sub.UA2P2.

[0081] The U.sub.A2P2 signal 1010, the U.sub.A2P1 signal 1014, and the U.sub.A2O signal 1020, are then inverted, e.g., by the inverters 1412-1416, respectively of FIG. 14, to obtain the IU.sub.A2P2 signal 1012, the IU.sub.A2P1 signal 1018, and the IU.sub.A2O signal 1024. The IU.sub.A2O signal 1024 is used as the switching signal S.sub.UA2N1. Then, the Boolean AND operation is performed on the IU.sub.A2P2 signal 1012 and the U.sub.A2P1 signal 1014, e.g., using the AND gate 1422 of FIG. 14, to obtain the S.sub.UA2P1 switching signal 1016. The Boolean AND operation is also performed on the IU.sub.A2P1 signal 1018 and the U.sub.A2O signal 1020, e.g., using the AND gate 1424 of FIG. 14, to obtain the S.sub.UA2O switching signal 1022.

[0082] FIG. 11 is a waveform diagram illustrating the generation of turn-on time signals U.sub.A7P2, U.sub.A7P1 and switching logic signals S.sub.UA7P2, S.sub.UA7P1, S.sub.UA7O of the respective P.sub.2, P.sub.1, 0 voltage level for waveform U.sub.A7 of Sector A and Region 7.

[0083] As shown in FIG. 11, the up/down counter signal 805 starts below switching time T.sub.2, increases through switching times T.sub.2 and T.sub.1 before reaching T.sub.S/2, then, after reaching T.sub.S/2, decreases through switching times T.sub.1 and T.sub.2. Switching times T.sub.1 and T.sub.2 are compared to the up/down counter signal 805, e.g., using comparators 1402 and 1404, respectively of FIG. 14, to obtain the U.sub.A7P2 signal 1110 and the U.sub.A7P1 signal 1114. The U.sub.A7P2 signal 1110 is used as the switching signal S.sub.UA7P2.

[0084] The U.sub.A7P2 signal 1110 and the U.sub.A7P1 signal 1114 are then inverted, e.g., by the inverters 1412 and 1414, respectively of FIG. 14, to obtain the IU.sub.A7P2 signal 1112 and the IU.sub.A7P1 signal 1118. The IU.sub.A7P1 signal 1118 is used as the switching signal S.sub.UA7O. Then, the Boolean AND operation is performed on the IU.sub.A7P2 signal 1112 and the U.sub.A7P1 signal 1114, e.g., using the AND gate 1422 of FIG. 14, to obtain the S.sub.UA7P1 switching signal 1116.

[0085] FIG. 12 is a waveform diagram illustrating the generation of turn-on time signal U.sub.A13P2 and switching logic signals (S.sub.UA13P2, S.sub.UA13P1) of the respective P.sub.2, P.sub.1 voltage level for waveform U.sub.AB of Sector A and Region 13.

[0086] As shown in FIG. 12, the up/down counter signal 805 starts below switching time T.sub.1 (e.g., time equal to zero), increases through switching time T.sub.1 before reaching T.sub.S/2, then, after reaching T.sub.S/2, decreases through switching time T.sub.1. Switching time T.sub.1 is compared to the up/down counter signal 805, e.g., using comparator 1402, to obtain the U.sub.A13P2 signal 1210, which is used as the switching signal S.sub.UA13P2. The U.sub.A13P2 signal 1210 is then inverted, e.g., by the inverter 1412 of FIG. 14, to obtain the IU.sub.A13P2 signal 1212, which is used as the switching signal S.sub.UA13P1.

[0087] FIG. 13 is a graphical diagram illustrating example turn-on time values T.sub.1, T.sub.2, T.sub.3, T.sub.4 for phase U of all six sectors (Sectors A-F) and Region 1 based on the equations set forth above. As shown, the turn-on time values T.sub.1, T.sub.2, T.sub.3, T.sub.4 are given for the switching states of each of the sectors. For phases V and W, the waveforms are similar to the waveforms in FIGS. 8-12, but are mutually phase shifted by the angle 2π/3.

PWM Signal Generation

[0088] FIG. 14 is a digital logic circuit for generating PWM switching signals for a five-level inverter. The digital logic circuit includes a first comparator 1402, a second comparator 1404, a third comparator 1406, a fourth comparator 1408, a first inverter 1412, a second inverter 1414, a third inverter 1416, a fourth inverter 1418, a first AND gate 1422, a second AND gate 1424, and a third AND gate 1426. The inverters 1412-1418 are digital logic inverters and are connected to outputs of the comparators 1402-1408, respectively. The AND gate 1422 has a first input connected to the output of the first inverter 1412 and a second input connected to the output of the second comparator 1404, the AND gate 1424 has a first input connected to the output of the second inverter 1414 and a second input connected to the output of the third comparator 1406; and the AND gate 1426 has a first input connected to the output of the third inverter 1416 and a second input connected to the output of the fourth comparator 1408.

[0089] The first inputs of the comparators 1402-1408 receive turn-on time values T.sub.1, T.sub.2, T.sub.3, and T.sub.4, respectively, and the second inputs of the comparators 1402-1408 receive the output from an up/down counter 1401. The up/down counter 1401 counts over a sampling period T.sub.S from 0 to T.sub.S/2 and from T.sub.S/2 to 0. The turn-on time values T.sub.1, T.sub.2, T.sub.3, and T.sub.4 are compared with the output of the up/down counter 1401 using digital logic comparators 1402-1408 to generate turn-on pulse signals U.sub.A/C/EP2, U.sub.A/C/EP1, U.sub.A/C/EO, U.sub.A/C/EN1 for A/C/E sectors or U.sub.B/D/FN2, U.sub.B/D/FN1, U.sub.B/D/FO, U.sub.B/D/FP1 for B/D/F sectors. These turn-on pulse signals are then logically inverted with multiple inverters 1412-1418 and logically ANDed by AND gates 1422-1426 to generate switching logic signals S.sub.UA/C/EP2, S.sub.UA/C/EP1, S.sub.UA/C/EO, S.sub.UA/C/EN1, S.sub.UA/C/EN2 for A/C/E sectors or S.sub.UB/D/FN2, S.sub.UB/D/FN1, S.sub.UB/D/FO, S.sub.UB/D/FP1, S.sub.UB/D/FP2 for B/D/F sectors for all sectors and regions. The comparators 1402-1408, the inverters 1412-1418, and the AND gates 1422-1426 may be implemented by a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC) for high-bandwidth fast operation.

[0090] In embodiments, the number of comparators, inverters, and AND gates may be increased or decreased depending on the number of levels of the multi-level inverter.

[0091] As shown in FIG. 8, turn-on time values T.sub.1, T.sub.z, T.sub.3, T.sub.4 are used to generate switching logic signals S.sub.UA1P2, S.sub.UA1P1, S.sub.UA1O, S.sub.UA1N1, S.sub.UA1N2. These switching logic signals are applied to gate drivers that drive respective power transistors, such as IGBT devices, to generate the U.sub.A1 waveform of Phase U. Turn-on time values T.sub.1, T.sub.z, T.sub.3, T.sub.4 are used to generate switching logic signals for P.sub.2, P.sub.1, O, N.sub.1, N.sub.2 in that respective order for all A, C, and E odd sectors.

[0092] As shown in FIG. 9, turn-on time values T.sub.1, T.sub.z, T.sub.3, T.sub.4 are used to generate switching logic signals S.sub.UB1N2, S.sub.UB1N1, S.sub.UB1O, S.sub.UB1P1, S.sub.UB1P2. These switching logic signals are applied to gate drivers to drive respective power transistors to generate the U.sub.B1 waveform of Phase U in sector B of region 1. Turn-on time values T.sub.1, T.sub.2, T.sub.3, T.sub.4 are used to generate the switching logic signal for N.sub.2, N.sub.1, O, P.sub.1, P.sub.2 in that respective order for all B, D, and F even sectors.

[0093] Similar signal processing is done for all other regions and V and W phases using the digital logic circuit. The turn-on time values T.sub.1, T.sub.2, T.sub.3, and T.sub.4 are different for Phases V and W. Some portion of the same control circuit is used to generate switching logic signals based on the location of the voltage vector V* as shown in FIGS. 10, 11, and 12.

[0094] In embodiments, a single timer, counting from 0 to T.sub.S/2 and then back to 0, and one digital logic circuit is used for all Sectors and Regions. Therefore, the complexity of SVPWM is simplified using the control system according to the present disclosure.

Region and Sector Identification of Five-Level Inverter

[0095] FIG. 15 is a flow diagram of a method for determining region and sector locations of command voltage V*. In the beginning, the command or reference voltage V* and angle θ.sub.e* are sampled. In step 1502, the current sector location is identified based on the angle θ.sub.e*. For easy implementation and calculation, all angles θ.sub.e* located in sectors B-F are remapped to sector A (θ.sub.eA) according to Table 2 below. Then, the command voltage V* and remapped angle θ.sub.eA are converted into X and Y voltage vector coordinate point values. The X and Y voltage vector coordinate points are compared with a respective XY-line equation in a sector to determine the region.

TABLE-US-00002 TABLE 2 Θ.sub.e* Location Sector Θ.sub.eA 0 ≧ Θ.sub.e* < π/3 A = Θ.sub.e* π/3 ≧ Θ.sub.e* < 2*π/3 B = (Θ.sub.e* − π/3) 2* π/3 ≧ Θ.sub.e* < π C = (Θ.sub.e* − 2*π/3) π ≧ Θ.sub.e* < 4*π/3 D = (Θ.sub.e* − π) 4*π/3 ≧ Θ.sub.e* < E = (Θ.sub.e* − 4*π/3) 5*π/3 5*π/3 ≧ Θ.sub.e* < 2* π F = (Θ.sub.e* − 5*π/3)

[0096] For example, as shown in FIG. 15, in step 1504, it is determined whether the X-Y coordinate points are less than or equal to Y=−1.732X+0.866. If the result of the determination in step 1504 is false, it is determined whether the X-Y coordinate points are greater than or equal to Y=−1.732X−0.866 and the X coordinate point is greater than or equal to 0.5, in step 1505. If the result of the determination in step 1505 is true, it is determined in step 1506 that the voltage vector V* is located in regions 5, 10, 11, or 12.

[0097] In step 1508, it is determined whether the X-Y coordinate points are less than or equal to Y=−1.732X+1.299. If the result of the determination in step 1508 is true, the voltage vector is determined to be in region 5, in step 1510. If the result of the determination in step 1508 is false, it is determined whether the X-Y coordinate points are greater than or equal to Y=−1.732X−1.299 and X is greater than or equal to 0.75, in step 1512. If the result of the determination in step 1512 is true, the voltage vector is determined to be in region 10, in step 1514. If the result of the determination in step 1512 is false, it is determined whether the Y coordinate point is greater than or equal to Y=0.2165, in step 1516. If the result of the determination in step 1516 is true, the voltage vector is determined to be in region 12, in step 1518. If the result of the determination in step 1516 is false, the voltage vector is determined to be in region 11, in step 1520.

[0098] If the result of the determination in step 1505 is false, it is determined whether the Y coordinate point is greater than or equal to Y=0.433 in step 1522. If the result of the determination in step 1522 is true, it is determined in step 1524 that the voltage vector V* is located in regions 9, 14, 15, or 16. In step 1526, it is determined whether the X-Y coordinate points are greater than or equal to Y=1.732X−0.433. If the result of the determination in step 1526 is true, the voltage vector is determined to be in region 14, in step 1528. If the result of the determination in step 1526 is false, it is determined whether the X-Y coordinate points are less than or equal to Y=−1.732X+1.299, in step 1530. If the result of the determination in step 1530 is true, the voltage vector is determined to be in region 9, in step 1532. If the result of the determination in step 1530 is false, it is determined whether the Y coordinate point is greater than or equal to Y=0.6495, in step 1534. If the result of the determination in step 1534 is true, the voltage vector is determined to be in region 16, in step 1536. If the result of the determination in step 1534 is false, the voltage vector is determined to be in region 15, in step 1538.

[0099] If the result of the determination in step 1522 is false, it is determined in step 1540 that the voltage vector V* is located in regions 6, 7, 8, or 13. In step 1542, it is determined whether the X-Y coordinate points are less than or equal to Y=1.732X−0.433. If the result of the determination in step 1542 is true, the voltage vector is determined to be in region 8, in step 1544. If the result of the determination in step 1542 is false, it is determined whether the X-Y coordinate points are greater than or equal to Y=−1.732X+1.299, in step 1546. If the result of the determination in step 1546 is true, the voltage vector is determined to be in region 13, in step 1548. If the result of the determination in step 1546 is false, it is determined whether the Y coordinate point is less than or equal to Y=0.2165, in step 1550. If the result of the determination in step 1550 is true, the voltage vector is determined to be in region 6, in step 1552. If the result of the determination in step 1550 is false, the voltage vector is determined to be in region 7, in step 1554.

[0100] If the result of the determination in step 1504 is true, it is determined in step 1556 that the voltage vector V* is located in regions 1, 2, 3, or 4. In step 1558, it is determined whether the X-Y coordinate points are less than or equal to Y=−1.732X+0.433. If the result of the determination in step 1558 is true, the voltage vector is determined to be in region 1, in step 1560. If the result of the determination in step 1558 is false, it is determined whether the X-Y coordinate points are greater than or equal to Y=−1.732X−0.433 and the X coordinate point is greater than or equal to 0.25, in step 1562. If the result of the determination in step 1562 is true, the voltage vector is determined to be in region 2, in step 1564. If the result of the determination in step 1562 is false, it is determined whether the Y coordinate point is greater than or equal to Y=0.2165, in step 1566. If the result of the determination in step 1566 is true, the voltage vector is determined to be in region 4, in step 1568. If the result of the determination in step 1566 is false, the voltage vector is determined to be in region 3, in step 1570.

SVPWM Controller

[0101] Once turn-on time values T.sub.1, T.sub.2, T.sub.3, T.sub.4 have been calculated for all P.sub.2, P.sub.1, O, N.sub.1, N.sub.2 states of all phases, it is possible to evaluate them in real time with the help of a DSP and establish the Space Vector PWM waves with the help of FPGA-based single timer and single digital logic circuit as shown in FIG. 14.

[0102] FIG. 16 is a block diagram illustrating a control system for a five-level diode clamped inverter. The control system includes a processor, such as a digital signal processor (DSP), which is used to implement blocks 1602 and 1604. Blocks 1602 and 1604 are easily implemented to carry out the SVPWM control strategy.

[0103] In block 1602, the processor samples a reference voltage vector V* and an angle θ.sub.e*, and identifies a sector and region based on the sampled reference voltage vector V* and angle θ.sub.e*. In block 1604, the processor selects predefined switching sequences and pre-calculated turn-on signal values T.sub.1, T.sub.2, T.sub.3, T.sub.4 based on the identified sector and region location of the reference voltage vector V*.

[0104] The control system also includes a digital logic circuit 1606, such as an FPGA, and an up/down counter for generating PWM switching signals. The digital logic circuit 1606, such as the digital logic circuit of FIG. 14, generates PWM switching signals for the power transistor drivers based on the turn-on signal values T.sub.1, T.sub.2, T.sub.3, T.sub.4 and the selected switching sequence. In embodiments, less expensive DSPs and FPGAs may be used because the overall control implementation is divided between a DSP and an FPGA circuit.

[0105] As described above, the overall control operation is divided into multiple modes (e.g., Modes 1-4) in terms of sector and region locations. A single digital logic circuit 1606 is used to generate switching logic signals for all the regions and sectors. This simplifies the control system and, in turn, reduces time to implement at minimum cost. Also, to simplify the control system, one up/down counter 1608 (counting from 0 to T.sub.S/2 and then from T.sub.S/2 to 0) with sampling period T.sub.S may be utilized.

[0106] FIG. 17 is a flow diagram of a method of controlling a multi-level inverter according to embodiments of the present disclosure. After starting in step 1701, a sector location is identified based on an actual angle of a reference voltage vector, in step 1702. In step 1704, the actual angle is converted into a converted angle located in a first sector and, in step 1706, a region location is identified based on the magnitude of the reference voltage vector and the converted angle in the first sector. In step 1708, a switching sequence and a plurality of turn-on signal values are selected based on the corresponding region location in the actual sector of the reference voltage vector. In step 1710, turn-on signal values are transmitted to second inputs of the plurality of comparators to generate switching signals for a power transistor driver of a multi-level inverter. In step 1712, each of the plurality of turn-on signals are compared to a digital up/down counter signal to obtain a plurality of comparison signals including a first comparison signal and a second comparison signal. In step 1714, the plurality of comparison signals are inverted to obtain a plurality of inverted signals including a first inverted signal. Then, before ending in step 1717, a logical AND operation is performed on the first inverted signal and the second comparison signal to obtain a switching signal for a corresponding driver that drives a power transistor of a multi-level inverter.

[0107] While several embodiments of the disclosure have been shown in the drawings and/or discussed herein, it is not intended that the disclosure be limited thereto, as it is intended that the disclosure be as broad in scope as the art will allow and that the specification be read likewise. Therefore, the above description should not be construed as limiting, but merely as exemplifications of particular embodiments. Those skilled in the art will envision other modifications within the scope and spirit of the claims appended hereto.