ELECTRON GAS CONFINEMENT HETEROJUNCTION TRANSISTOR

Abstract

A high electron mobility heterojunction transistor, including a first GaN layer; a second, p-doped GaN layer on top of the first layer, including magnesium as a p-type dopant, the concentration of which is at least equal to 5*10.sup.16 cm.sup.−3 and at most equal to 2*10.sup.18 cm.sup.−3, the thickness of the second GaN layer being between 20 and 50 nm; a third, n-doped GaN layer on top of the second GaN layer in order to form a depleted p-n junction; a fourth GaN layer, which is not intentionally doped, on top of the third GaN layer; a semiconductor layer plumb with the fourth GaN layer, which is not intentionally doped, in order to form an electron gas layer.

Claims

1. A high electron mobility heterojunction transistor, comprising: a first GaN layer; a second, p-doped GaN layer formed on top of the first GaN layer, this second GaN layer including magnesium forming a p-type dopant, the concentration of magnesium in the second GaN layer being at least equal to 5*10.sup.16 cm.sup.−3 and at most equal to 2*10.sup.18 cm.sup.−3, the thickness of said second GaN layer being between 20 and 50 nm; a third, n-doped GaN layer formed on top of the second GaN layer so as to form a depleted p-n junction; a fourth GaN layer, which is not intentionally doped, formed on top of the third GaN layer; a semiconductor layer formed plumb with the fourth GaN layer, which is not intentionally doped, in order to form an electron gas layer.

2. The heterojunction transistor according to claim 1, in which the third GaN layer includes silicon forming an n-type dopant.

3. The heterojunction transistor according to claim 2, in which the concentration of silicon in the third GaN layer is at least equal to 1.5*10.sup.16 cm.sup.−3.

4. The heterojunction transistor according to claim 2, in which the concentration of silicon in the third GaN layer is at most equal to 2*10.sup.18 cm.sup.−3.

5. The heterojunction transistor according to claim 1, in which the thickness of said third GaN layer is between 10 and 100 nm.

6. The heterojunction transistor according to claim 1, in which the dopant concentration of said fourth layer is less than 1*10.sup.16 cm.sup.−3.

7. The heterojunction transistor according to claim 1, in which the thickness of said fourth layer is between 50 and 100 nm.

8. The heterojunction transistor according to claim 1, in which the carbon concentration of said first GaN layer is greater than that of the second and third GaN layers.

9. The heterojunction transistor according to claim 1, in which said semiconductor layer includes AlGaN.

Description

[0019] Other features and advantages of the invention will become clearly apparent from the description that is given thereof below by way of completely non-limiting indication and with reference to the appended drawings, in which:

[0020] FIG. 1 is a cross-sectional view of an exemplary high electron mobility heterojunction transistor according to the invention;

[0021] FIGS. 2 and 3 are diagrams of conduction bands of a transistor according to the invention and of a transistor according to the prior art;

[0022] FIG. 4 is a cross-sectional view of another exemplary variant of a high electron mobility heterojunction transistor according to the invention.

[0023] FIG. 1 is a schematic cross-sectional view of an exemplary high electron mobility heterojunction transistor according to one embodiment of the invention. The transistor 1 comprises a substrate 11, an intermediate layer 12 positioned on the substrate 11, a GaN buffer layer 13 positioned on the intermediate layer 12, a p-doped GaN layer 14 positioned on the GaN buffer layer 13, an n-doped GaN layer 15 positioned on the GaN layer 14 and a GaN layer 16, which is not intentionally doped, positioned on the layer 15. The transistor 1 additionally comprises an AlGaN layer 17 positioned on the layer 16. An electron gas is intrinsically formed by heterojunction at the interface between the layer 17 and the layer 16. For the sake of legibility, the electron gas is illustrated in the form of layer 18 at the interface between the layer 16 and the layer 17. An intermediate layer (not illustrated) may be interposed between the layers 16 and 17, for example in order to increase the electron density and mobility in the electron gas. Such an intermediate layer is typically extremely thin (for example 1 nm) and may be made of AlN (particularly suited to the interface between a GaN layer 16 and an AlGaN layer 17).

[0024] In a manner known per se, the transistor 1 comprises a source 21, a drain 22 and a control gate 23 which are formed on the AlGaN layer 17. The source 21, the drain 22 and the control gate 23 are only schematically illustrated, their dimensions and their structures potentially differing substantially from the illustration of FIG. 1.

[0025] The substrate 11 may be an insulator, an intrinsic or doped silicon semiconductor, SiC or sapphire. The thickness of the substrate 11 may typically be of the order of 650 μm to 1 mm.

[0026] The intermediate layer 12 (which may be formed from a superposition of transition layers) is deposited on the substrate 11. The transition layer 12 allows the crystal lattice parameters between the GaN layers 11 and 13 to be adjusted. This makes it possible to manage the mechanical stresses between the substrate 11 and an active portion of layers formed by epitaxy. The layer 12 may include the superposition of a nucleation layer (typically of AlN with a thickness of about 100 nm) and multiple adaptation layers (for example multiple layers of AlGaN with a decreasing molar fraction of AlN, or else a superlattice comprising multiple AlxGa(1−x)N/GaN) bilayers.

[0027] Such an intermediate layer 12 has been shown to be particularly advantageous in the case of a substantial mismatch of lattice parameters between the layer 13 and the substrate 11, which could result in mechanical dislocations within these layers.

[0028] The thickness of the buffer layer 13 may be dependent on the target voltage for the transistor 1, for example it may have a thickness of a few microns. A relatively substantial thickness of the buffer layer 13 makes it possible to limit the lateral and vertical leakage currents in the transistor 1 and also to better confine the electron gas layer 18. The buffer layer 13 may, for example, be made of carbon-doped (semi-insulator) GaN—Si or of the superposition of a layer of GaN—Si/AlxGa(1−x)N, where x is small, for example between 4 and 8%.

[0029] The thickness of the p-doped GaN layer 14 is, for example, 50 nm and its acceptor concentration N.sub.A is, for example, 1*10.sup.17 cm.sup.−3. The thickness of the n-doped GaN layer 15 is, for example, 80 nm and its donor concentration N.sub.D is, for example, 2*10.sup.16 cm.sup.−3. The carbon concentration of the layers 14 and 15 is lower than that of the layer 13. This carbon concentration is, for example, lower than 1*10.sup.16 cm.sup.−3.

[0030] The thickness of the GaN layer 16, which is not intentionally doped, is, for example, 50 nm. In order to favour maximum electron mobility in the electron gas layer 18, the doping of the GaN layer 16 is as low as possible. A layer 16 will, for example, be considered to be not intentionally doped if the concentration of n and p dopants is lower than 1*10.sup.16 cm.sup.−3. The thickness of the AlGaN layer 17 is, for example, 25 nm.

[0031] Advantageously, the p-doped layer 14 is doped with magnesium, which chemical element may easily be integrated into the layer 14 during a potential formation by means of epitaxy. Additionally, magnesium may easily be activated. Advantageously, the n-doped layer 15 is doped with silicon, which chemical element may easily be integrated into the layer 15 during a potential formation by means of epitaxy.

[0032] The superposition of the p-doped GaN layer 14 on the n-doped GaN layer 15 allows a depleted p-n junction to be formed, so as to form a particularly high potential barrier below the electron gas layer. The p-n junction formed may be completely depleted, with appropriate thicknesses and dopant concentrations in the layers 14 and 15. Additionally, such a junction is formed using materials compatible with the GaN layer 16, which is not intentionally doped, intended to form the electron gas layer. Additionally, such a potential barrier allows the formation of an AlGaN layer below this GaN layer 16, which is not intentionally doped, to be avoided, thereby making it possible to limit the mechanical stresses at the interface with this GaN layer 16.

[0033] This technical solution of the invention may be applied both to a normally-off transistor and to a normally-on transistor.

[0034] FIG. 2 is a conduction band diagram of the transistor 1 described above as a function of depth. By way of comparison, FIG. 3 provides a conduction band diagram of a transistor of the prior art as a function of depth. The transistor of the prior art under consideration comprises a 25 nm AlGaN layer formed on top of a GaN layer, which is not intentionally doped, and the thickness of which is 1.40 μm.

[0035] It has been observed that the potential barrier for the transistor 1 according to the invention is about 1.3 eV. In contrast, the potential barrier of the transistor according to the prior art is about 0.15 eV. The transistor 1 according to the invention thus makes it possible to obtain a particularly high potential barrier in order to avoid electrons of the electron gas layer 18 being trapped in the layer 13 for example. Simulations have made it possible to determine that the electron densities in the respective electron gas layers of these transistors are substantially equivalent, i.e. about 8.5*10.sup.12 cm.sup.−2 for the transistor of the example of FIG. 3, compared to about 8.2*10.sup.12 cm.sup.−2 for the transistor of the example of FIG. 2. The electron density of the electron gas layer 18 according to the invention therefore remains particularly high.

[0036] The influence of various parameters of the layers 14, 15 and 16 on the formation of a potential barrier for the electron gas layer 18 and the GaN layer 16 will be described in more detail below.

[0037] According to one variant illustrated in FIG. 4, a GaN layer 19 is formed in a manner known per se on top of the AlGaN layer 17, in order to avoid oxidation of the AlGaN layer 17. The layer 19 is etched below the contacts in order to make contact with the layer 17. The thickness of the layer 19 is, for example, between 1 and 3 nm.

[0038] In order to make it possible to predict the influence of various parameters on the performance of the transistor 1 according to the invention, the following notation will be used hereinafter:

[0039] Ns: the electron density in the electron gas layer (in cm.sup.−2);

[0040] μ.sub.2 DEG: the electron mobility in the electron gas layer (en cm.sup.2/Vs);

[0041] N.sub.D: the volumetric density of donors in the n-doped GaN layer 15 (in cm.sup.−3);

[0042] N.sub.A: the volumetric density of acceptors in the p-doped GaN layer 14 (in cm.sup.−3);

[0043] N.sub.A−: the volumetric density of acceptors in a p-doped GaN layer that is sufficiently thick not to be depleted (en cm.sup.−3);

[0044] N.sub.D+: the volumetric density of donors in an n-doped GaN layer that is sufficiently thick not to be depleted (en cm.sup.−3);

[0045] ni: the intrinsic carrier density in a GaN layer at room temperature (in cm.sup.−3);

[0046] RT: room temperature, taken to be 300 K;

[0047] T: the temperature of the substrate in K;

[0048] Nsc: the electron density in the layer 16 of the transistor 1 (in cm.sup.−2);

[0049] Wn: the thickness of the n-doped GaN layer 15;

[0050] Wnid: the thickness of the GaN layer 16, which is not intentionally doped;

[0051] Wp: the thickness of the p-doped GaN layer 14;

[0052] Vbi: the built-in potential of the p-n junction formed at the interface between the layers 14 and 15;

[0053] Vbbpn: the potential barrier across the terminals of the depleted p-n junction;

[0054] Vbbnid: the potential barrier across the terminals of the GaN layer 16, which is not intentionally doped;

[0055] Vbb: the total potential barrier;

[0056] α.sub.0: the permittivity of vacuum;

[0057] ε.sub.sc: the permittivity of GaN;

[0058] k: the Boltzmann constant=1.3806488 E.sup.−23 J/K;

[0059] q: the charge of an electron≈1.6 E.sup.−19 C.

[0060] The accesses of the transistor 1 include the zones between the control gate 23 and the drain 22, and between the control gate 23 and the source 21, including the electron gas layer 18.

[0061] The built-in potential of the iunction between the lavers 14 and 15 may be defined as follows:

[00001] $V_{bi (T)} = \frac{k .Math. T}{q} .Math. \ln (\frac{N_{A (T)}^{-} .Math. .Math. N_{D (T)}^{+}}{n_{i (T)}^{2}})$

[0062] With p-doping using magnesium, the ionization energy of the Mg acceptor in the GaN is about 180 meV. Ionization is therefore partial at temperature RT. This must therefore be taken into account for the calculation of Vbi by means of the inequality N.sub.A−<N.sub.A at temperature RT.

[0063] When ni=1.9e.sup.−10 cm.sup.−3 at temperature RT, ND≈N.sub.D+=1e.sup.16 cm.sup.−3 (with silicon doping) and N.sub.A−=1e.sup.17 cm.sup.−3, Vbi≈3.1 V is obtained. Vbi remains largely insensitive to variations in N.sub.A− and N.sub.D+ owing to the logarithm in the relationship and to the low value of ni.

[0064] The potential barrier formed between the electron gas layer 18 and the buffer layer 13 (preventing electrons being injected into and trapped in the deep layers of the buffer layer 13) appears by virtue of the built-in potential Vbi, and includes: [0065] in part a potential barrier across the terminals of the p-n junction formed between the layers 14 and 15:

[00002] $V_{bbnid} = \frac{q}{.Math. {.Math.}_{s}} .Math. (N_{A} .Math. W_{p} - N_{D} .Math. W_{n}) .Math. W_{nid}$ [0066] in part a potential barrier across the terminals of the GaN layer 16:

[00003] $V_{bbpn} = \frac{q}{2 .Math. .Math. {.Math.}_{s}} .Math. (N_{A} .Math. W_{p}^{2} + 2 .Math. N_{A} .Math. W_{p} .Math. W_{n} - N_{D} .Math. W_{n}^{2})$

[0067] In the space charge zone of the p-n junction, all of the acceptors and donors are ionized and it is therefore their total concentration that appears in the calculations (Na−=Na and Nd+=Nd).

[0068] The potential barrier obtained by combining the layers 14 and 15 attains a higher level than that of a potential layer of AlGaN placed below the layer 16 forming the electron gas (as in the example described in “Characteristics of AlGaN/GaN/AlGaN double heterojunction HEMTs with an improved breakdown voltage” cited in the introduction).

[0069] The design rules of such a transistor 1 may be cited.

[0070] When the dopant of the layer 14 is magnesium, the end limits for N.sub.A are fixed by: [0071] the capability of the epitaxy technology to incorporate magnesium into the GaN layer 14 and to activate it there (accounting for a solubility limit and passivation by complexes, in particular Mg—H complexes). The maximum usable value for N.sub.A is currently a priori 1e.sup.19 cm.sup.−3; [0072] the value required to have a Vbi>3V, namely N.sub.A>3e.sup.16 cm.sup.−3.

[0073] A transistor 1 according to the invention within this range of values could theoretically be designed. In practice, a concentration of 1e.sup.17 cm.sup.−3<N.sub.A<1e.sup.18 cm.sup.−3 will advantageously be used. N.sub.A>1e.sup.17 cm.sup.−3 allows a substantial back barrier (>1.3 V) to be obtained and N.sub.A<1e.sup.18 cm.sup.−3 allows the p-layer 14 to be robust in terms of thickness (Wp>15 nm).

[0074] For the layer 15, an N.sub.D value between 1e.sup.17 cm.sup.−3 and N.sub.A may be selected, for example, in particular with Si as the dopant.

[0075] The built-in potential Vbimay subsequently be calculated according to the relationship described above.

[0076] A corresponding total depletion thickness Wn0 in a GaN n-layer and a corresponding total depletion thickness Wp0 in a GaN p-layer may then be calculated, in the case that the thicknesses of the n- and p-layers are greater than Wn0 and Wp0, respectively.

[0077] It is then possible to determine the thicknesses of the GaN layers 15 and 14 to be produced so that they are completely depleted, observing only the following inequalities:

Wn0≧Wn; and

Wp0≧Wp.

[0078] The layer 14 is advantageously completely depleted, in order to avoid the retention of a conductive layer of holes which would prevent the penetration of the electric field through the thickness of the GaN layer 13, thereby leading to a substantial decrease in the voltage withstand of the transistor.

[00004] $W_{p} < W_{p .Math. .Math. 0} = \sqrt{\frac{2 .Math. .Math. {.Math.}_{s} .Math. V_{bi} .Math. N_{D}}{q .Math. N_{A} .Math. (N_{A} + N_{D})}}$

[0079] When Vbi=3.1 V, N.sub.A=1*10.sup.18 cm.sup.−3 and N.sub.D=1*10.sup.18 cm.sup.−3, a W.sub.p0 value of 41 nm is obtained. A W.sub.p value that is sufficiently high to enable robust epitaxial production thereof is used (for example W.sub.p>10 nm). A W.sub.p value of 28 nm may be chosen, for example. A decrease in the W.sub.p value lowers the level of the potential barrier. However, a decrease in the W.sub.p value guarantees the depletion of the GaN layer 14. Advantageously, W.sub.p is between 30 and 50 nm, and it is preferably equal to 50 nm.

[0080] In order to obtain complete depletion of the GaN layer 15, the following relationship is verified:

[00005] $W_{n} < W_{n .Math. .Math. 0} = \sqrt{\frac{2 .Math. .Math. {.Math.}_{s} .Math. V_{bi} .Math. N_{A}}{q .Math. N_{D} .Math. (N_{A} + N_{D})}}$

[0081] When N.sub.A=N.sub.D=1.sup.e18 cm.sup.−3, W.sub.no=41 nm, a W.sub.n value of 28 nm may be chosen, for example.

[0082] Advantageously, Wn≧0.2*Wn0 or Wn≧10 nm, in order to avoid the depletion having an effect on the electron gas layer 18. Specifically, the layer 15 must absorb a non-negligible proportion of the built-in potential. A sufficiently substantial thickness Wn is additionally used so that the potential barrier generated by the junction is sufficient to prevent the injection of electrons with a sufficient developed space charge into the layer 15. A Wn value of 28 nm is sufficient, for example.

[0083] Advantageously, Wn0 is greater than Wn (for example Wn0>Wn), such that the GaN layer 15 is completely depleted below the electrodes of the transistor 1. For example, for a Wn0 value of 41 nm, a Wn value of less than 41 nm may be chosen.

[0084] When Wn=28 nm, Wp=28 nm and N.sub.A=N.sub.D=1e.sup.18 cm.sup.−3, a potential barrier of about 1.7 eV is obtained, 0.9 eV of which is across the terminals of the junction and 0.3 eV of which is across the terminals of the layer 16.

[0085] The layer 16 is advantageously sufficiently thick to prevent any disruption of the electron gas layer 18 at the electrodes of the transistor through the influence of the dopants of the layers 14 and 15. Thus, advantageously, 100 nm≧Wnid≧50 nm (for example obtained when Wn=28 nm and Wn+Wnid≧78 nm in order to limit the effect of the magnesium on the electron gas layer 18). Advantageously, Wnid=50 nm.

[0086] The layers 12 to 18 may be formed successively in one and the same vapour phase epitaxy machine, while of course changing the epitaxy conditions for each of the layers. The epitaxy parameters for the formation of each of the layers are known per se to those skilled in the art.

[0087] In the example illustrated, the barrier layer 17 is formed from AlGaN. According to the invention, any other semiconductor layer may be positioned on top of the GaN layer 16, which is not intentionally doped, if it is capable of generating an electron gas at their interface. The layer 17 may, for example, be another ternary group-III nitride alloy. The layer 17 may also be a binary group-III nitride alloy, for example AlN.

[0088] In the example, the AlGaN of the layer 17 may comprise an aluminium concentration of between 6 and 9%, but other aluminium proportions may of course be used.

[0089] In the various variants, it is possible to envisage interposing an AlN layer between an AlGaN layer 17 and a GaN layer 16, in order to enhance the confinement of the electron gas and the mobility thereof. The thickness of this AlN layer is advantageously between 5 ångströms and 2 nm.

[0090] The layer 17 may advantageously be covered by a passivation layer, in particular in order to improve the insulation between the electrodes of the transistor 1. The passivation layer may, for example, be made of SiN. A layer of SiNmay be deposited by means of epitaxy, without removing the wafer from the epitaxy installation after the formation of the layers 16 and 17.

ELECTRON GAS CONFINEMENT HETEROJUNCTION TRANSISTOR

Assignee

Inventors

Cpc classification

Classification Explorer

H01L29/7786

ELECTRICITY

Classification Explorer

H01L29/0607

ELECTRICITY

Classification Explorer

H01L29/2003

ELECTRICITY

Classification Explorer

H01L29/205

ELECTRICITY

Classification Explorer

H01L29/1075

ELECTRICITY

Classification Explorer

H01L29/207

ELECTRICITY

International classification

Classification Explorer

H01L29/207

ELECTRICITY

Classification Explorer

H01L29/06

ELECTRICITY

Classification Explorer

H01L29/20

ELECTRICITY

Classification Explorer

H01L29/205

ELECTRICITY

Classification Explorer

H01L29/778

ELECTRICITY

Abstract

Claims

Description