PIXEL CIRCUIT, DRIVING METHOD AND DISPLAY PANEL

Abstract

A pixel circuit, a driving method and a display panel are provided by the disclosure. The pixel circuit includes: a sharing unit and N light-emitting control units. An input terminal of each of the light-emitting control units is electrically connected to an output terminal of the sharing unit; an output terminal of each of the light-emitting control units is electrically connected to a light-emitting element, a control terminal of each of the light-emitting control units is electrically connected a control signal line. The sharing unit is configured to drive, through each of the light-emitting control units. The light-emitting element electrically connected to the light-emitting control unit. N is positive integer greater than or equal to 2. The pixel circuit, the driving method and the display panel of the disclosure may solve the problem of the non-uniform display due to the drift of the threshold voltage of the driving transistor.

Claims

1. A pixel circuit, comprising: a sharing unit and N light-emitting control units; and, wherein the N light-emitting control units are configured such that: an input terminal of each of the N light-emitting control units is electrically connected to an output terminal of the sharing unit; an output terminal of each of the N light-emitting control units is electrically connected to a light-emitting element; and a control terminal of each of the N light-emitting control units is configured to be electrically connected to a respective one of N control signal lines; and the sharing unit is configured to drive, through each of the light-emitting control units, the light-emitting element electrically connected to the light-emitting control unit, wherein N is positive integer greater than or equal to 2.

2. The pixel circuit of claim 1, wherein, the sharing unit is configured to be electrically connected to a power signal line, a data line and at least one scan line, to receive a power supply voltage signal, a data signal and at least one scan signal, respectively.

3. The pixel circuit of claim 2, wherein, each of the N light-emitting control units comprises a first transistor, and the light-emitting element is a light-emitting diode; wherein an output terminal of the first transistor is configured to be electrically connected to an anode of the light-emitting diode, and a control terminal of the first transistors is configured to be electrically connected to a corresponding control signal line; a cathode of the light-emitting diode is electrically connected to the ground.

4. The pixel circuit of claim 3, wherein, the sharing unit comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor; and, wherein an input terminal of the second transistor is configured to be electrically connected to a reference signal line, and an output terminal of the second transistor is electrically connected to a first terminal of the first capacitor, and a control terminal of the second transistor is configured to be electrically connected to a first scan line; an input terminal of the third transistor is configured to be electrically connected to the power signal line, an output terminal of the third transistor is electrically connected to an input terminal of the fourth transistor, a control terminal of the third transistor is configured to be electrically connected to a strobe signal line; an input terminal of the fifth transistor is configured to be electrically connected to the data line, an output terminal of the fifth transistor is electrically connected to the input terminal of the fourth transistor, a control terminal of the fifth transistor is configured to be electrically connected to a second scan line; a control terminal of the fourth transistor is electrically connected to the first terminal of the first capacitor; an input terminal of the sixth transistor is electrically connected to an output terminal of the fourth transistor, an output terminal of the sixth transistor is electrically connected to the terminal of the first capacitor, a control terminal of the sixth transistor is configured to be electrically connected to the second scan line; and a second terminal of the first capacitor is configured to be electrically connected to the power signal line.

5. The pixel circuit of claim 3, wherein, the sharing unit comprises a seventh transistor, an eighth transistor, a ninth transistor, a second capacitor and a third capacitor; and the pixel circuit further comprises N tenth transistors; and, wherein, an input terminal of each of the N tenth transistors is configured to be electrically connected to a reference signal line, an output terminal of each of the N tenth transistors is electrically connected to a second terminal of the second capacitor, a control terminal of each of the N tenth transistors is configured to be electrically connected to a respective one of the N control signal lines; an input terminal of the ninth transistor is configured to be electrically connected to the data line, an output terminal of the ninth transistor is electrically connected to the second terminal of the second capacitor, a control terminal of the ninth transistor is configured to be electrically connected to the scan line; an input terminal of the seventh transistor is configured to be electrically connected to the power signal line, a control terminal of the seventh transistor is electrically connected to the first terminal of the second capacitor; and an input terminal of the eighth transistor is electrically connected to an output terminal of the seventh transistor, an output terminal of the eighth transistor is electrically connected to the first terminal of the second capacitor and a first terminal of the third capacitor, and a control terminal of the eighth transistor is configured to be electrically connected to the scan line and a second terminal of the third capacitor.

6. The pixel circuit of claim 4, wherein, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor have an identical channel type.

7. The pixel circuit of claim 5, wherein, the first transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistors have an identical channel type.

8. A display panel, comprising: a plurality of the pixel circuits and a plurality of light-emitting elements; and, wherein the plurality of light-emitting elements are arranged in an array, and N light-emitting elements in a row of the array share one of the plurality of the pixel circuits, wherein, each of the plurality of the pixel circuits comprises a sharing unit and N light-emitting control units, and wherein an input terminal of each of the N light-emitting control units is electrically connected to an output terminal of the sharing unit; an output terminal of each of the N light-emitting control units is electrically connected to a light-emitting element; and a control terminal of each of the N light-emitting control units is configured to be electrically connected to a respective one of N control signal lines; and the sharing unit is configured to drive, through each of the N light-emitting control units, the light-emitting element electrically connected to the light-emitting control unit; wherein N is positive integer greater than or equal to 2.

9. The display panel of claim 8, wherein the sharing unit is configured to be electrically connected to a power signal line, a data line and at least one scan line, to receive a power supply voltage signal, a data signal and at least one scan signal, respectively.

10. The display panel of claim 9, wherein each of the N light-emitting control units comprises a first transistor, and the light-emitting element is a light-emitting diode; and, wherein an output terminal of the first transistor is electrically connected to an anode of the light-emitting diode, and a control terminal of the first transistors is configured to be electrically connected to a corresponding control signal line; a cathode of the light-emitting diode is electrically connected to the ground.

11. The display panel of claim 10, wherein the sharing unit comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor; and, wherein an input terminal of the second transistor is configured to be electrically connected to a reference signal line, and an output terminal of the second transistor is electrically connected to a first terminal of the first capacitor, and a control terminal of the second transistor is configured to be electrically connected to a first scan line; an input terminal of the third transistor is configured to be electrically connected to the power signal line, an output terminal of the third transistor is electrically connected to an input terminal of the fourth transistor, a control terminal of the third transistor is configured to be electrically connected to a strobe signal line; an input terminal of the fifth transistor is configured to be electrically connected to the data line, an output terminal of the fifth transistor is electrically connected to the input terminal of the fourth transistor, a control terminal of the fifth transistor is configured to be electrically connected to a second scan line; a control terminal of the fourth transistor is electrically connected to the first terminal of the first capacitor; an input terminal of the sixth transistor is electrically connected to an output terminal of the fourth transistor, an output terminal of the sixth transistor is electrically connected to the terminal of the first capacitor, a control terminal of the sixth transistor is configured to be electrically connected to the second scan line; and a second terminal of the first capacitor is configured to be electrically connected to the power signal line.

12. The display panel of claim 10, wherein the sharing unit comprises a seventh transistor, an eighth transistor, a ninth transistor, a second capacitor and a third capacitor; and the pixel circuit further comprises N tenth transistors; and, wherein, an input terminal of each of the N tenth transistors is configured to be electrically connected to a reference signal line, an output terminal of each of the N tenth transistors is electrically connected to a second terminal of the second capacitor, a control terminal of each of the N tenth transistors is configured to be electrically connected to a respective one of the N control signal lines; an input terminal of the ninth transistor is configured to be electrically connected to the data line, an output terminal of the ninth transistor is electrically connected to the second terminal of the second capacitor, a control terminal of the ninth transistor is configured to be electrically connected to the scan line; an input terminal of the seventh transistor is configured to be electrically connected to the power signal line, a control terminal of the seventh transistor is electrically connected to the first terminal of the second capacitor; and an input terminal of the eighth transistor is electrically connected to an output terminal of the seventh transistor, an output terminal of the eighth transistor is electrically connected to the first terminal of the second capacitor and a first terminal of the third capacitor, and a control terminal of the eighth transistor is configured to be electrically connected to the scan line and a second terminal of the third capacitor.

13. The display panel of claim 11, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor have an identical channel type.

14. The display panel of claim 12, wherein the first transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistors have an identical channel type.

15. A method, for driving the pixel circuit according to claim 4, comprising repeatedly performing a reset step, a writing and compensating step, and a light-emitting step until the N light-emitting diodes emit light one by one, wherein in the reset step, under the control of a scan signal of the first scan line, the second transistor is turned on, so that a reference voltage is written into the first terminal of the first capacitor through the reference signal line, and the potential of the control terminal of the fourth transistor is reset; in the writing and compensating step, under the control of a scan signal of the second scan line, the fifth transistor, the fourth transistor and the sixth transistor are turned on, so that the data line inputs the data signal, and the potential of the first terminal of the first capacitor increases until the fourth transistor is turned off; and in the light-emitting step, under the control of the input voltage of the strobe signal line and the input voltage of the control signal line, the third transistor and the first transistor electrically connected to the control signal line are turned on, so that the light-emitting diode electrically connected to the first transistor emits light.

16. A method, for driving the pixel circuit according to claim 5, comprising repeatedly performing a writing and compensate step and a light-emitting step in sequence until the N light-emitting diodes emit light one by one; and, wherein in the writing and compensate step, under the control of a scan signal of the scan line, the ninth transistor and the eighth transistor are turned on, so that the data line inputs the data signal to the second terminal of the second capacitor, the third capacitor pulls down the potential of the first terminal of the second capacitor, the seventh transistor is turned on, and the power signal line inputs the power supply, and the potential of the first terminal of the second capacitor increases until the seventh transistor is turn off; and in the light-emitting step, under the control of an input voltage of the control signal line, the tenth transistor and the first transistor electrically connected to the control signal line are turned on, so that the reference signal line inputs the reference voltage to the second terminal of the second capacitor, and the seventh transistor is turned on, the light-emitting diode electrically connected to the first transistor emits light.

Description

DESCRIPTION OF DRAWINGS

[0023] FIG. 1 is a schematic diagram showing the structure of a pixel circuit provided by an embodiment of the disclosure;

[0024] FIG. 2 is a schematic diagram showing the structure of another pixel circuit provided by an embodiment of the disclosure;

[0025] FIG. 3 is the timing diagram of a pixel circuit driving method provided by the an embodiment of the disclosure;

[0026] FIG. 4 is a schematic diagram showing the structure of another pixel circuit provided by an embodiments of the disclosure;

[0027] FIG. 5 is the timing diagram of a pixel circuit driving method provided by an embodiment of the disclosure; and

[0028] FIG. 6 is a schematic diagram showing the structure of a display panel provided by an embodiment of the disclosure.

DETAILED DESCRIPTION

[0029] For better understanding of the disclosure, the disclosure will be further described below with reference to the accompanying drawings and embodiments. It may be understood that specific embodiments described herein are merely for explaining the present disclosure rather than limiting the present disclosure. Moreover, it is noted that only parts related to the disclosure, rather than the entire structure are shown in the accompanying drawings.

[0030] FIG. 1 is a schematic diagram showing the structure of a pixel circuit provided by an embodiment of the disclosure. As shown in FIG. 1, a pixel circuit includes: a sharing unit and N light-emitting control units T.sub.EmitN, where N is positive integer greater than or equal to two.

[0031] An input terminal of each of the light-emitting control units T.sub.EmitN is electrically connected to an output terminal of the sharing unit. An output terminal of each of the light-emitting units T.sub.EmitN is electrically connected to a corresponding light-emitting element O.sub.N, an control terminal of each of light-emitting control units T.sub.EmitN is electrically connected to a corresponding control signal line Emit.sub.N. An input terminal of the sharing unit is electrically connected to a data lines V.sub.N, to receive corresponding data signals. The sharing unit is configured to drive, through each of the light-emitting control units T.sub.EmitN, the light-emitting element O.sub.N electrically connected to the output terminal of the light-emitting control unit T.sub.EmitN to emit light. Referring to the pixel circuit shown in FIG. 1, it is noted that the pixel circuit in FIG. 1 can control the N light-emitting elements O.sub.N to emit light one by one, so that the N light-emitting elements O.sub.N may be disposed above the region of the pixel circuit in manufacturing the display panel, thus significantly improving the resolution of the display panel as compared with the configuration in the related art that one light-emitting element is disposed above one pixel circuit.

[0032] A core idea of the disclosure is described above. The sharing unit can be implemented in many ways, and the connection between the sharing unit and other devices of the pixel circuit can be implemented in many ways. The technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to accompanying drawings. Obviously, the described embodiments are just a part of the embodiments of the disclosure, rather than all the embodiments. Based on the embodiments in the disclosure, other embodiments obtained by those skilled in the art without creative work also belong to the scope of protection of the present disclosure.

[0033] On the basis of the pixel circuit provided in FIG. 1, in some embodiments, the sharing unit provided by an embodiment of the disclosure is electrically connected to a power signal line VDD, a data line VDATA and at least one scan line SCAN, to receive a power supply voltage signal, data signals and at least one scan signal respectively.

[0034] FIG. 2 is a schematic diagram showing the structure of another pixel circuit provided by an embodiment. As shown in FIG. 2, illustratively, the pixel circuit in the embodiment includes two light-emitting control units. That is, N is equal to 2. Each light-emitting control unit includes a first transistor. For easy description, the first transistors of the two light-emitting control units are referred to as the first transistor T.sub.11 and the first transistor T.sub.12 respectively. The light-emitting element O.sub.N is a light-emitting diode (which is also indicated by O.sub.N for easy description). An output terminal of the first transistor T.sub.11 is electrically connected to an anode of the light-emitting diode O.sub.1, and an output terminal of the first transistor T.sub.12 is electrically connected to an anode of the light-emitting diode O.sub.2. A control terminal of the first transistor T.sub.11 is electrically connected to a control signal line Emit.sub.1, and a control terminal of the first transistor T.sub.12 is electrically connected to a control signal line Emit.sub.2. Each of cathodes of the light-emitting diode O.sub.1 and the light-emitting diode O.sub.2 is connected to the ground (i.e., a ground line VSS).

[0035] The sharing unit (that is, the region in the dash line box) includes: a second transistor T.sub.2, a third transistor T.sub.3, a fourth transistor T.sub.4, a fifth transistor T.sub.5, a sixth transistor T.sub.6 and a first capacitor C.sub.1. An input terminal of the second transistor T.sub.2 is electrically connected to a reference signal line V.sub.ref, an output terminal of the second transistor T.sub.2 is electrically connected to a first terminal of the first capacitor C.sub.1, and a control terminal of the second transistor T.sub.2 is electrically connected to a first scan line SCAN.sub.1. An input terminal of the third transistor T.sub.3 is electrically connected to the power signal line VDD, an output terminal of the third transistor T.sub.3 is electrically connected to an input terminal of the fourth transistor T.sub.4, and a control terminal of the third transistor T.sub.3 is electrically connected to a strobe signal line V.sub.Emit. An input terminal of the fifth transistor T.sub.5 is electrically connected to the corresponding data lines (including V.sub.1 and V.sub.2), an output terminal of the fifth transistor T.sub.5 is electrically connected to an input terminal of the fourth transistor T.sub.4, and a control terminal of the fifth transistor T.sub.5 is electrically connected to a second scan line SCAN.sub.2. A control terminal of the fourth transistor T.sub.4 is electrically connected to the first terminal of the first capacitor C.sub.1. An input terminal of the sixth transistor T.sub.6 is electrically connected to the output terminal of the fourth transistor T.sub.4, an output terminal of the sixth transistor T.sub.6 is electrically connected to the first terminal of the first capacitor C.sub.1, and a control terminal of the sixth transistor T.sub.6 is electrically connected to the second scan line SCAN.sub.2. A second terminal of the first capacitor C.sub.1 is electrically connected to the power signal line VDD. It is noted that the pixel circuit illustratively shown in FIG. 2 includes two light-emitting control units (that is, two first transistors), which is not a limited thereto, and in other embodiments, the number of the light-emitting control units may be specifically arranged based on the requirements of real products.

[0036] It is noted that in the embodiments of the disclosure, the first transistors, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor may be N-channel transistors, and may also be P-channel transistors. In driving the light-emitting diode by the pixel circuit, the input signals (such as high level signal and low level signal) may be changed based on the channel types of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor. In the present embodiment, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor have same channel type, thus simplifying the structure of the pixel circuit and reducing the area occupied by the pixel circuit.

[0037] For easy description, hereinafter, the data signal voltages of the data line are represented by V.sub.N, the voltage of the power signal line is represented by VDD, the voltage of the corresponding scan line is represented by SCAN. The voltage of the reference signal line is represented by V.sub.ref.

[0038] An embodiment also provides a pixel circuit driving method used for the pixel circuit shown in FIG. 2. Illustratively, the driving method provided by the present embodiment is described using the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor, of P-channel. FIG. 3 is the timing diagram of the pixel circuit driving method provided by the present embodiment. In combination of the pixel circuit shown in FIG. 2 with the timing diagram of the pixel circuit driving method shown in FIG. 3, the pixel circuit driving method includes: a first reset step S.sub.1, a first writing and compensating step S.sub.2, a first light-emitting step S.sub.3, a second reset step S.sub.4, a second writing and compensating step S.sub.5, and a second light-emitting step S.sub.6.

[0039] In the first reset step S.sub.1, the scan signal of the first scan line SCAN.sub.1 is at a low level. Under the control of the scan signal of the first scan line SCAN.sub.1, the second transistor is turned on, so that the reference voltage V.sub.ref is written into the first terminal (that is, node A.sub.1 in FIG. 2) of the first capacitor C.sub.1 through the reference signal line, and hence the potential value of node A.sub.1 is V.sub.ref, and thereby the potential of the control terminal of the fourth transistor T.sub.4 is reset.

[0040] In the first writing and compensating step S.sub.2, the scan signal of the second scan line SCAN.sub.2 is at a low level. Under the control of the scan signal of the second scan line SCAN.sub.2, the fifth transistor T.sub.5, the fourth transistor T.sub.4 and the sixth transistor T.sub.6 are turned on, so that the data line inputs a data signal V.sub.1. When the potential of the first terminal of the first capacitor C.sub.1 is pulled up to V.sub.1−|V.sub.th| (where V.sub.th is the threshold voltage of the fourth transistor T.sub.4), the fourth transistor T.sub.4 is turned off, and hence the potential difference between the second terminal and the first terminal of the first capacitor C.sub.1 is VDD−V.sub.1+|V.sub.th|, thus achieving the data inputting and threshold voltage compensation.

[0041] In the first light-emitting step S.sub.3, the input voltages of the strobe signal line V.sub.Emit and the control signal line Emit.sub.1 are both at a low level. Under the control of the input voltages of the strobe signal line V.sub.Emit and the control signal line Emit.sub.1, the third transistor T.sub.3 and the first transistor T.sub.11 electrically connected to the control signal line Emit.sub.1 are turned on, so that the light-emitting diode O.sub.1 electrically connected to the first transistor T.sub.11 emits light. The current formula of the light-emitting diode is: I=K(V.sub.SG−|V.sub.th|).sup.2, where I represents the current of the light-emitting diode, K is a parameter related to the process parameters and critical dimension of the driving transistor, V.sub.SG represents the potential difference between the input terminal of the driving transistor and the control terminal of the driving transistor (that is, the potential difference between the potential of the source electrode and the potential of the gate electrode), and V.sub.th is the threshold voltage of the driving transistor. Thus, the current flowing through the light-emitting diode O1 is I.sub.1=K[|VDD−(V.sub.1−|V.sub.th|)|−|V.sub.th|].sup.2=K(VDD−V.sub.1).sup.2, and is independent of the threshold voltage V.sub.th of the fourth transistor T.sub.4 (that is, the driving transistor), where K is a parameter related to the process parameters and critical dimension of the driving transistor.

[0042] In the second reset step S.sub.4, the scan signal of the first scan line SCAN.sub.1 is at a low level. Under the control of the scan signal of the first scan line SCAN.sub.1, the second transistor T.sub.2 is turned on, so that the reference voltage V.sub.ref is written into the first terminal of the first capacitor C.sub.1 through the reference signal line, and hence the potential value of node A.sub.1 is V.sub.ref, and thereby the potential of the control terminal of the fourth transistor T.sub.4 is reset.

[0043] In the second writing and compensating step S.sub.5, the scan signal of the second scan line SCAN.sub.2 is at a low level. Under the control of the scan signal of the second scan line SCAN.sub.2, the fifth transistor T.sub.5, the fourth transistor T.sub.4 and the sixth transistor T.sub.6 are turned on, the data line inputs a data signal V.sub.2, when the potential of the first terminal of the first capacitor C.sub.1 is pulled up to V.sub.2−|V.sub.th| (where V.sub.th is the threshold voltage of the fourth transistor T.sub.4), the fourth transistor T.sub.4 is turned off, and hence the potential difference between the second terminal and the first terminal of the first capacitor C.sub.1 is VDD−V.sub.2+V.sub.th|, thus achieving the data inputting and threshold voltage compensation.

[0044] In the second light-emitting step S.sub.6, the input voltages of the strobe signal line V.sub.Emit and the control signal line Emit.sub.2 are both at a low level. Under the control of the input voltages of the strobe signal line V.sub.Emit and the control signal line Emit.sub.2, the third transistor T.sub.3 and the first transistor T.sub.12 electrically connected to the control signal line Emit.sub.2 are turned on, so that the light-emitting diode O.sub.2 electrically connected to the first transistor T.sub.12 emits light. According to the current calculating formula of the light-emitting diode I=K(V.sub.SG−|V.sub.th).sup.2, the current of the light-emitting diode O.sub.2 is I.sub.2=K[|VDD−(V.sub.2−|V.sub.th|)|−|V.sub.th|].sup.2=K(VDD−V.sub.2).sup.2

[0045] So far, scan displaying of a frame of image has finished, and the scan display of the next frame of image will start when next SCAN1 with a low level arrives. The display process is repeated in such a way.

[0046] In this embodiment, the driving method for the pixel circuit enables the current of the light-emitting diode to be independent of the threshold voltage of the fourth transistor (i.e., the driving transistor), thus effectively solving the problem of the non-uniform display due to the drift of the threshold voltage of the driving transistor. In addition, unlike the configuration in the related art that a pixel circuit is provided for each of the light-emitting diodes and a complicated circuit is arranged in the region of the pixel unit including the light-emitting diode in order to solve the problem of the non-uniform display due to the drift of the threshold voltage of the driving transistor. In the present embodiment, more than one light-emitting diodes is configured to share a pixel circuit, so that the light-emitting diodes can be disposed in the region of the pixel circuit, that is, more than one pixel units may be disposed in the region of the pixel circuit, thus sufficiently decreasing the size of the pixel unit and significantly improving the resolution of the display panel.

[0047] When the pixel circuit comprises N light-emitting control unit, and each of the light-emitting control units includes a first transistor, the driving method for the pixel circuit includes: a reset step, a writing and compensating step and a light-emitting step.

[0048] In the reset step, under the control of a scan signal of the first scan line, the second transistor is turned on, so that a reference voltage is written into the first terminal of the first capacitor through the reference signal line, and the voltage of the control terminal of the fourth transistor is reset.

[0049] In the writing and compensating step, under the control of a scan signal of the second scan line, the fifth transistor, the fourth transistor and the sixth transistor are turned on, so that the data signal is inputted through the data line, and the potential of the first terminal of the first capacitor is pulled up to turn off the fourth transistor.

[0050] In the light-emitting step, under the control of the input voltage of the strobe signal line and the input voltage of the control signal line, the third transistor and the first transistor electrically connected to the control signal line are turned on, so that the light-emitting diode electrically connected to the first transistor emits light.

[0051] By this method, the reset step, the writing and compensating step and the light-emitting step described above are performed repeatedly in sequence until the N light-emitting diodes emit light one by one.

[0052] It is noted that the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are illustratively defined as P-channel transistors to describe the above embodiment. When the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor all are N-channel, the scan signal of each of the scan lines, the input voltage of the strobe signal line and the input voltage of each control signal line in FIG. 3 are changed from a low level to a high level.

[0053] FIG. 4 is a schematic diagram showing the structure of another pixel circuit provided by an embodiment of the disclosure. The sharing unit (that is, the region of the dash line rectangle) comprises a seventh transistor T.sub.7, an eighth transistor T.sub.8, a ninth transistor T.sub.9, a second capacitor C.sub.2 and a third capacitor C.sub.3. The pixel circuit further comprises N tenth transistors T.sub.10. FIGS. 4 illustratively show two tenth transistors, namely the tenth transistor T.sub.101 and the tenth transistor T.sub.102 respectively. An input terminal of the tenth transistor T.sub.101 and an input terminal of the tenth transistor T.sub.102 both are electrically connected to a reference signal line V.sub.ref. An output terminal of the tenth transistor T.sub.101 and an output terminal of the tenth transistor T.sub.102 both are electrically connected to a second terminal of the second capacitor C.sub.2. A control terminal of the tenth transistor T.sub.101 is electrically connected to a control signal line Emit.sub.1, and a control terminal of the tenth transistor T.sub.102 is electrically connected to a control signal line Emit.sub.2. An input terminal of the ninth transistor T.sub.9 is electrically connected to a corresponding data line VDATA (including V.sub.1 and V.sub.2), an output terminal of the ninth transistor T.sub.9 is electrically connected to the second terminal of the second capacitor C.sub.2, and a control terminal of the ninth transistor T.sub.9 is electrically connected to a corresponding scan line SCAN. An input terminal of the seventh transistor T.sub.7 is electrically connected to a power supply signal line VDD, and a control terminal of the seventh transistor T.sub.7 is electrically connected to a first terminal of the second capacitor C.sub.2. An input terminal of the eighth transistor T.sub.8 is electrically connected to the input terminal of the seventh transistor T.sub.7. An output terminal of the eighth transistor T.sub.8 is electrically connected to the first terminal of the second capacitor C.sub.2 and a first terminal of the third capacitor C.sub.3, and a control terminal of the eighth transistor T.sub.8 is electrically connected to a scan line SCAN and a second terminal of the second capacitor C.sub.3.

[0054] It is noted that, according to various embodiments, the first transistor T.sub.1, the seventh transistor T.sub.7, the eighth transistor T.sub.8, the ninth transistor T.sub.9 and the tenth transistors may be N-channel transistors, or may be with P-channel transistors. When driving light-emitting diodes through the pixel circuit, each of the input signals (such as the values of the high level voltage and low level voltage) of the pixel circuit may be changed according to the channel types of the first transistor T.sub.1, the seventh transistor T.sub.7, the eighth transistor T.sub.8, the ninth transistor T.sub.9 and the tenth transistors. Similar to the above embodiments, the first transistor T.sub.1, the seventh transistor T.sub.7, the eighth transistor T.sub.8, the ninth transistor T.sub.9 and the tenth transistors have same channel type, thus simplifying the structure of the pixel circuit and reducing the area occupied by the pixel circuit.

[0055] An embodiment also provides another pixel circuit driving method used for the pixel circuit shown in FIG. 4. Illustratively, the driving method provided by the present embodiment is described using the first transistor T.sub.1, the seventh transistor T.sub.7, the eighth transistor T.sub.8, the ninth transistor T.sub.9 and the tenth transistors, of P-channel. FIG. 5 is the timing diagram of the pixel circuit driving method provided by the present embodiment. In combination of the pixel circuit shown in FIG. 4 and the timing diagram of the pixel circuit driving method shown in FIG. 5, the pixel circuit driving method includes the following steps: a first writing and compensating step X.sub.1, a first light-emitting step X.sub.2, a second writing and compensating step X.sub.3 and a second light-emitting step X.sub.4.

[0056] In the first writing and compensating step X.sub.1, the scan signal of the scan line SCAN is at low level. Under the control of the scan signal of the scan line SCAN, the ninth transistor T.sub.9 and the eighth transistor T.sub.8 are turn on, so that the data signal V.sub.1 is written into the second terminal (node B.sub.2 in FIG. 4) of the second capacitor C.sub.2 through the data line V.sub.1. Also, due to the coupling effect of the third capacitor C.sub.3, the value of the potential of the first terminal (node B.sub.1 in FIG. 4) of the second capacitor C.sub.2 is pulled down, so that the seventh transistor T.sub.7 is turned on and the the power supply voltage VDD is inputted through power supply signal line, and the current flows through the seventh transistor T.sub.7 and the eighth transistor T.sub.8, and hence the potential of the node B.sub.1 is being continuously pulled up until the potential of the node B.sub.1 is VDD−|Vth|(where Vth is the threshold voltage of the seventh transistor T.sub.7), and then the seventh transistor T.sub.7 is turned off

[0057] In the light-emitting step X.sub.2, the input voltage of the control signal line Emit.sub.1 is at low level. Under the control of the input voltage of the control signal line Emit.sub.1, the tenth transistor T.sub.101 and the first transistor T.sub.11 electrically connected to the control signal line Emit.sub.1 are turned on, so that the reference voltage V.sub.ref is written into the second terminal (node B.sub.2) of the second capacitor C.sub.2 by the reference signal line V.sub.ref. Due to the coupling effect of the capacitor, the potential of node B.sub.1 is changed to

[00001] $\frac{C_{2}}{(C_{2} + C_{3})} .Math. (V_{ref} - V_{1}) + VDD - .Math. V_{th} .Math. .$

Then, the seventh transistor T.sub.7 is turned on, so that the light-emitting diode O.sub.1 electrically connected to the first transistor T.sub.11 emits light. According to the current calculating formula for the light-emitting diode I=K(V.sub.SG−|V.sub.th|).sup.2, the current of the light-emitting diode O.sub.1 is

[00002] $I_{1} = K .Math. {.Math. VDD - [\frac{C_{2}}{(C_{2} + C_{3})} .Math. (V_{ref} - V_{1}) + VDD - .Math. V_{th} .Math.] .Math. - .Math. V_{th} .Math.}^{2} = {K [\frac{C_{2}}{(C_{2} + C_{3})} .Math. (V_{ref} - V_{1})]}^{2} \circ +^{'} .$

[0058] In the second writing and compensating step X.sub.3, the scan signal of the scan line SCAN is at low level. Under the control of the scan signal of the scan line SCAN, the ninth transistor T.sub.9 and the eighth transistor T.sub.8 are turn on, so that the data signal V.sub.2 is written into the second terminal (node B.sub.2 in FIG. 4) of the second capacitor C.sub.2 through the data line. Also, due to the coupling effect of the third capacitor C.sub.3, the value of the potential of the first terminal (node B.sub.1 in FIG. 4) of the second capacitor C.sub.2 is pulled down, so that the seventh transistor T.sub.7 is turned on and the power supply voltage VDD is inputted through the power supply signal line, the current flows through the seventh transistor T.sub.7 and the eighth transistor T.sub.8 and hence the potential of the node B.sub.1 is being continuously pulled up until the potential of the node B.sub.1 is VDD−|Vth|(Vth is the threshold voltage of the seventh transistor T.sub.7), when the seventh transistor T.sub.7 is turned off.

[0059] In the second light-emitting step X.sub.4, the input voltage of the control signal line Emit.sub.1 is at low level. Under the control of the input voltage of the control signal line Emit.sub.1, the tenth transistor T.sub.101 and the first transistor T.sub.11 electrically connected to the control signal line Emit.sub.1 are turned on, and the reference voltage V.sub.ref is written into the second terminal (node B.sub.2) of the second capacitor C.sub.2 by the reference signal line V.sub.ref. The potential of node B.sub.1 is changed to

[00003] $\frac{C_{2}}{(C_{2} + C_{3})} .Math. (V_{ref} - V_{2}) + VDD - .Math. V_{th} .Math.$

due to the capacitor coupling effect. At this moment, the seventh transistor T.sub.7 is turned on and the light-emitting diode O.sub.1 electrically connected to the first transistor T.sub.11 emits light. According to the current calculating formula of the light-emitting diode I=K(V.sub.SG−|V.sub.th|).sup.2, the current of the light-emitting diode O.sub.1 is

[00004] $I_{2} = K .Math. {.Math. VDD - [\frac{C_{2}}{(C_{2} + C_{3})} .Math. (V_{ref} - V_{2}) + VDD - .Math. V_{th} .Math.] .Math. - .Math. V_{th} .Math.}^{2} = {K [\frac{C_{2}}{(C_{2} + C_{3})} .Math. (V_{ref} - V_{2})]}^{2} \circ +^{'} .Math. .Math. I_{1} = K .Math. {.Math. VDD - [\frac{C_{2}}{(C_{2} + C_{3})} .Math. (V_{ref} - V_{1}) + VDD - .Math. V_{th} .Math.] .Math. - .Math. V_{th} .Math.}^{2} = {K [\frac{C_{2}}{(C_{2} + C_{3})} .Math. (V_{ref} - V_{1})]}^{2} .$

[0060] So far, scan displaying of a frame of image has finished, and the scan display of the next frame of image will start when next SCAN1 with a low level arrives. The display process is repeated in such a way.

[0061] In the present embodiment, the driving method for the pixel circuit enables the current of the light-emitting diode to be independent of the threshold voltage of the seventh transistor (i.e., the driving transistor), thus effectively solving the problem of the non-uniform display due to the drift of the threshold voltage of the driving transistor. In addition, unlike the configuration in the related art that a pixel circuit is provided for each of the light-emitting diodes and a complicated circuit is arranged in the region of the pixel unit including the light-emitting diode in order to solve the problem of the non-uniform display due to the drift of the threshold voltage of the driving transistor. In the present embodiment, more than one light-emitting diodes is configured to share a pixel circuit, so that the light-emitting diodes can be disposed in the region of the pixel circuit. That is, more than one pixel units may be disposed in the region of the pixel circuit, thus sufficiently decreasing the size of the pixel unit and significantly improving the resolution of the display panel.

[0062] In the case that the pixel circuit comprises N light-emitting control unit, each of the light-emitting control units comprises a first transistor, the driving method for the pixel circuit is performed as the following steps: a writing and compensate step and a light-emitting step.

[0063] In the writing and compensate step, under the control of a scan signal of the scan line, the ninth transistor and the eighth transistor are turned on, so that the data line inputs the data signal to the second terminal of the second capacitor, the third capacitor pulls down the potential of the first terminal of the second capacitor, the seventh transistor is turned on, and the power signal line inputs the power supply, and the potential of the first terminal of the second capacitor increases until the seventh transistor is turn off.

[0064] In the light-emitting step, under the control of an input voltage of the control signal line, the tenth transistor and the first transistor electrically connected to the control signal line are turned on, so that the reference signal line inputs the reference voltage to the second terminal of the second capacitor, and the seventh transistor is turned on, the light-emitting diode electrically connected to the first transistor emits light.

[0065] By this method, the writing and compensating step and the light-emitting step described above in sequence until the N light-emitting diodes emit light one by one.

[0066] It is noted that, the embodiment above described is explained in case of that the first transistors, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistors all have P type channel. In the case that the first transistors, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistors all have N type channel, the scan signal of each of the scan lines, the input voltage of the strobe signal line and the input voltage of each control signal line are changed from a low level to a high level.

[0067] The embodiment also provides a display panel. FIG. 6 is a schematic diagram showing the structure of a display panel provided by an embodiment of the disclosure. As shown in FIG. 6, the display panel includes a plurality of the pixel circuits 20 according to in the above embodiments and a plurality of light-emitting elements O.sub.N. The plurality of light-emitting elements O.sub.N are arranged in an array, and N light-emitting elements in a row of the array share a sharing unit of one of the pixel circuits 20 (not shown). Each of the plurality of the pixel circuits 20 is configured to drive N light-emitting elements O.sub.N to emit light one by one. As the exemplary arrangement in FIG. 6, each of the pixel circuits 20 is configured to drive three light-emitting diodes in a row of the array to emit light one by one and the three light-emitting diodes are indicated by O.sub.1, O.sub.2 and O.sub.3 respectively.

[0068] In the display panel provided by the embodiments of the present disclosure, N light-emitting elements share one pixel circuit, and each of the light-emitting elements defines a a region of one pixel unit, so that more than one light-emitting elements can be disposed in the region of the pixel circuit while being compatible with the function of the pixel circuit in the related art. Compared with the configuration in the related art that each light-emitting element requires a pixel circuit (that is, a complicated circuit is disposed in the pixel unit defined by a light-emitting element), the pixel circuit of the disclosure may significantly reduce the size of the pixel unit, and hence the resolution of the display panel is significant improved. For example, the resolution of the display panel shown in FIG. 6 is three times than the resolution of the display panel in the related art that one pixel circuit is disposed for one pixel unit.

[0069] It is noted that, throughout FIGS. 1 to 6, the same elements are indicated by identical drawing reference numbers. The same elements are not discussed repeatedly in detail, and those skilled in the art may understand the content of the drawings according to the related specific description.

[0070] The preferred embodiments of the present invention are described as above, but are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., that are made without departing from the spirit and principle of the present invention should fall into the scope of protection of the present invention.

PIXEL CIRCUIT, DRIVING METHOD AND DISPLAY PANEL

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Cpc classification

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G09G2310/0251

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G09G2300/0443

PHYSICS

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G09G2330/02

PHYSICS

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G09G2310/021

PHYSICS

Classification Explorer

G09G3/3233

PHYSICS

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G09G2320/045

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G09G3/2092

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G09G2300/0804

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G09G2300/0876

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G09G2300/0426

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International classification

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G09G3/20

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Abstract

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