FULLY INTEGRATED LOW-NOISE AMPLIFIER

Abstract

A low-noise amplifier device includes an inductive input element, an amplifier circuit, an inductive output element and an inductive degeneration element. The amplifier device is formed in and on a semiconductor substrate. The semiconductor substrate supports metallization levels of a back end of line structure. The metal lines of the inductive input element, inductive output element and inductive degeneration element are formed within one or more of the metallization levels. The inductive input element has a spiral shape and the an amplifier circuit, an inductive output element and an inductive degeneration element are located within the spiral shape.

Claims

1. An integrated amplifier device, comprising: an inductive input element, an amplifier circuit, an inductive output element, and an inductive degeneration element, wherein the amplifier circuit, said inductive output element and said inductive degeneration element are located on an inside of said inductive input element.

2. The device according to claim 1, wherein the inductive input element is configured to permit an input current to flow between an input terminal and the amplifier circuit in a first direction, and the inductive output element is configured to permit an output current to flow between the amplifier circuit and a supply terminal in a second direction that is opposite to the first direction.

3. The device according to claim 1, wherein the amplifier circuit comprises at least one first transistor configured to operate in an amplification mode.

4. The device according to claim 3, wherein the amplifier circuit comprises a cascode assembly comprising the at least one first transistor and a second transistor.

5. The device according to claim 3, wherein the inductive input element is coupled between a gate of the at least one first transistor and an input terminal of said device, the gate of the at least one first transistor being placed adjacent an end of the inductive input element.

6. The device according to claim 3, wherein said inductive degeneration element is coupled between a source of the at least one first transistor and a ground terminal, the source of the at least one first transistor being placed adjacent to one end of said inductive degeneration element and the ground terminal being placed adjacent another end of said inductive degeneration element.

7. The device according to claim 1, wherein said inductive input element comprises a metal track in the form of a non-intersecting spiral, with the amplifier circuit, said inductive output element and said inductive degeneration element located inside of said non-intersecting spiral.

8. The device according to claim 1, wherein the amplifier circuit, said inductive output element and said inductive degeneration element are supported by an integrated circuit substrate.

9. An integrated amplifier device, comprising: a semiconductor substrate; a back end of line structure supported by said semiconductor substrate; an amplifier circuit formed in and on said semiconductor substrate; an inductive input element, inductive output element and inductive degeneration element provided within said back end of line structure; wherein said inductive input element comprises a spiral shape; and wherein the amplifier circuit, inductive output element and inductive degeneration element are located within the spiral shape of the inductive input element.

10. The device of claim 9, wherein said back end of line structure includes metallization levels and the inductive input element, inductive output element and inductive degeneration element are formed in one or more of the metallization levels.

11. The device of claim 9, wherein inductive output element also has a spiral shape, and where current flowing in the spiral shape of the inductive input element flows in an opposite direction of flowing in the spiral shape of the inductive output element.

12. The device of claim 11, wherein the spiral shape of said inductive input element is in the form of a non-intersecting spiral and wherein the spiral shape of said inductive output element is in the form of an intersecting spiral.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Other advantages and features of the invention will become apparent upon examining the detailed description of completely non-limiting embodiments, and the appended drawings in which:

[0029] FIG. 1 shows an exemplary receiving stage of a telecommunication system;

[0030] FIG. 2 shows an exemplary circuit diagram of an amplifier device; and

[0031] FIG. 3 shows an exemplary architecture of an amplifier device structure.

DETAILED DESCRIPTION

[0032] FIG. 1 shows an exemplary conventional receiving stage, for example of a telecommunication system, comprising an antenna 1, directly coupled to a low-noise amplifier (LNA) 2.

[0033] The amplified signal output from the LNA is mixed by two mixers 3 with a local oscillator signal 4 and this local oscillator signal phase-shifted by 90° by a phase shifter 5, respectively.

[0034] At the output of the mixers 3, analog signals transposed onto the channel I and onto the channel in phase quadrature Q are obtained, which will subsequently be filtered by filters 6 and converted into digital signals by an analog-digital converter (CAN) 7, then processed, in particular demodulated, by a processing stage (MPU) 8.

[0035] FIG. 2 shows a circuit diagram of an, advantageously low noise, amplifier device, comprising an amplifier circuit CA and an inductive input element Lin, an inductive degeneration element Ldeg and an inductive output element Lout.

[0036] The amplifier circuit CA comprises active elements, such as transistors for example.

[0037] The amplifier device 2 conventionally comprises supply Vdd and ground GND terminals, an input terminal receiving signal RF_IN+VG_GO1, an output terminal generating signal RF_OUT, and a bias voltage terminal receiving bias voltage VG_GO2.

[0038] The amplifier circuit CA here comprises a cascode assembly of two transistors M1, M2 in series, the source of the transistor M2 being connected to the drain of the transistor M1, used in amplification mode. The amplification function could be ensured by a common-source assembly, for example, or any other assembly ensuring this function.

[0039] The source of the transistor M1 is connected to ground via the inductive degeneration element Ldeg.

[0040] The inductive input element Lin is connected between the input receiving signal RF_IN+VG_GO1 and the gate of the transistor M1.

[0041] The gate of the transistor M2 is connected to a node linking a bias resistor Rbias connected to the bias voltage terminal receiving bias voltage VG_GO2 and a decoupling capacitor Cgo2 connected to the ground GND.

[0042] The drain of the transistor M2 is connected to an output node linking the output generating the signal RF_OUT of the amplifier 2 via an output capacitor Cout and an inductive output element Lout connected to the supply terminal Vdd. The supply terminal Vdd is directly connected to a decoupling capacitor Cvdd linked to ground GND.

[0043] Thus, the transistor M1 is controlled via the gate thereof by the input signal RF_IN+VG_GO1, said input signal comprising the signal to be amplified RF_IN transmitted by an antenna for example, and a bias voltage VG_GO1 biasing the transistor M1 to a given on-state corresponding to a desired power consumption.

[0044] The input signal RF_IN+VG_GO1 resistively generates an input current IRFin that flows through the inductive input element Lin.

[0045] The inductive degeneration element Ldeg allows the input impedance matching to be optimized in combination with the inductive input element Lin in particular. More specifically, to the first order, the inductive input element Lin allows the imaginary part of the input impedance of the LNA to be cancelled out and the inductive degeneration element Ldeg allows the real part of the input impedance to be set to 50 ohms, for a reference impedance of 50 ohms.

[0046] The resistance Rbias allows the gate of the transistor M2 to be biased while presenting a high impedance to the input radiofrequency signal. The capacitor Cgo2 allows the radiofrequency signal entering at the drain of the transistor M2 to see ground.

[0047] The transistor M2 is controlled by the bias voltage VG_GO2, which may be, for example, of 1.5 V so as to bias the drain of the transistor M1 to 1.2 V, in the case of a supply voltage Vdd at 2.5 V.

[0048] An output current IRFout, corresponding to the amplified input current IRFin, flows into the inductive output element Lout and into the output capacitor Cout.

[0049] The transistor M1 has been shown in body contact configuration, i.e. the source terminal and the substrate (“body”) terminal of the transistor M1 are linked, ensuring good linearity of amplification. The transistor M2 has been shown in floating body configuration, i.e. the potential of the substrate (“body”) thereof is floating, facilitating the architecture while having a satisfactory output impedance.

[0050] Preferably, the transistors M1 and M2 are produced on and in a semiconductor substrate of a silicon-on-insulator (SOI) technology. SOI technology allows higher quality factors to be obtained in comparison with other technologies.

[0051] However, the transistors M1 and M2 may, depending on the need, be in a configuration other than the body contact and floating body configuration respectively, or be of another nature, for example bipolar or CMOS transistors, or produced in BiCMOS (bipolar and CMOS) technology supported on and in a semiconductor substrate.

[0052] The decoupling capacitor Cvdd allows potential variations on the supply Vdd to be removed and filtered to ground.

[0053] The inductive output element Lout in particular allows the output impedance to be matched to a required value. The assembly of the inductive output element Lout and of the output capacitor Cout allows the output matching desired at the working frequency to be obtained.

[0054] FIG. 3 shows an architecture of an, advantageously low noise, integrated amplifier device structure 2 corresponding to the circuit described above in relation to FIG. 2, in which the amplifier circuit CA and the inductive degeneration Ldeg and output Lout elements are positioned on the inside of the inductive input element Lin.

[0055] The integrated amplifier device 2 is produced, according to this architecture, on a single semiconductor substrate surmounted by a back end of line (BEOL) portion and conventionally comprises pads for connecting to the supply Vdd, ground GND, input RF_IN+VG_GOL output RF_OUT and bias voltage VG_GO2 terminals.

[0056] The various pads for connecting to the ground terminals GND shown in FIG. 3 are all linked to a ground plane that is not shown in this representation, corresponding to a uniform common ground.

[0057] Usually, the amplifier circuit CA is produced in and on the semiconductor substrate and the inductive elements in the metallization levels of the back end of line portion.

[0058] These connection pads are intended, for example, to receive metallization bumps in order to enable flip chip interconnection. These connection pads may also, for example, allow probes to be applied in order to characterize the circuit in terms of small signal performance, noise and linearity.

[0059] The inductive input element Lin is here formed by a metal track in the form of a non-intersecting flat spiral, i.e. the metal track winds around without unwinding, one end of the inductive input element consequently being located on the outside of the spiral and the other end on the inside of the spiral.

[0060] Consequently, in this configuration that advantageously avoids the superposition of metal tracks of the inductive input element Lin, this being a source of parasitic components, the pad for connecting to the input terminal to receive the signal RF_IN+VG_GO2 is located on the outside of the spiral.

[0061] The pad for connecting to the bias voltage terminal for receiving the bias voltage VG_GO2 is, in this non-limiting representation, also located on the outside of the inductive input element Lin, but according to the general features, nothing prevents an embodiment comprising this pad located on the inside of the inductive input element Lin.

[0062] The transistor M1 is positioned very close to the inner end of the inductive input element Lin in order to minimize the length of a connecting track Pg linking said inductive input element Lin to the gate of the transistor M1. In particular, this allows losses at the input of the amplifier circuit CA to be reduced.

[0063] The inductive degeneration element Ldeg is configured so as to be as compact as possible. Connecting tracks Ps and Pgnd at the ends of the inductive element Ldeg and the inductive element Ldeg are optimized together, so as to obtain the desired inductance “L” and a quality factor “Q” that is optimal at the working frequency.

[0064] In particular, this allows the surface area occupied on the inside of the inductive input element Lin to be decreased.

[0065] In this representation, in contrast to the inductive input element Lin, the inductive degeneration element Ldeg is formed by a flat spiral that intersects itself, i.e. in the form of a metal track that winds and unwinds, and the two ends of which are on the outside of the spiral.

[0066] The decoupling capacitors Cgo2 and Cvdd of FIG. 2 are shown here in a non-limiting manner in the respective combinations of capacitor pairs Cgo2_1 and Cgo2_2, Cvdd_1 and Cvdd_2. Each pair of capacitors comprises a capacitor (Cgo2_1, Cvdd_1) produced, for example, in MOM (metal-oxide-metal) technology comprising intersecting metal “fingers” separated by oxide spaces, and a capacitor (Cgo2_2, Cvdd_2) produced, for example, in PIPCAP (poly-insulator-poly capacitor) technology by superposing layers of polysilicon, insulator and polysilicon.

[0067] These two capacitor technologies are well known to those skilled in the art and are used in combination in order to benefit from the advantages of each thereof. These advantages are based on linearity and density criteria, i.e. capacitance per μm.sup.2.

[0068] The inductive output element Lout is positioned in a configuration such that, during normal operation of the amplifier device 2, the output current portion IRFout flowing through the inductive output element Lout flows in a direction of rotation that is opposite to the direction of rotation of the input current IRFin flowing through the inductive input element Lin.

[0069] Specifically, in the configuration shown in FIG. 3, the input current IRFin flows through the inductive input element Lin in an anticlockwise direction, from the input terminal RF_IN+VG_GO1 to the gate of the transistor M1. In this same configuration, the output current portion IRFout flows through the inductive output element Lout in a clockwise direction, from the drain of the transistor M2 to the supply terminal Vdd.

[0070] The magnetic fields generated by the two inductive input Lin and output Lout elements are consequently in opposite directions and the coupling of one to the other is very much reduced.

[0071] This configuration allows an improved isolation factor S.sub.12 to be obtained, for example a reduction of substantially 6 dB with respect to a configuration in which the current flows in the same direction in said two inductive elements.

[0072] The other components of the amplifier circuit CA, described above in relation to FIG. 2, are advantageously positioned on the surface area available on the inside of the inductive input element Lin and the configuration shown in FIG. 3 is, geometrically speaking, in no way limiting.