Semiconductor device for power electronics applications

Abstract

The present invention suggests a semiconductor device for integration into a power module. The semiconductor device comprises (a) a semiconductor layer (10), a first side of the semiconductor layer (10) having a plurality of depressions (11); (b) an insulating layer (12; 12a, 12b), the insulating layer being deposited on the first side of the semiconductor layer (10) and engaging in the depressions (11); (c) a first electrically conductive layer (14; 14a, 14b) for contacting the semiconductor device (1, 2), the first electrically conductive layer (14; 14a, 14b) being deposited on the insulating layer (12a, 12b); and (d) a second electrically conductive layer (16) for contacting the semiconductor device (1, 2), the second electrically conductive layer (16) being deposited on a second side of the semiconductor layer (10) opposite to the first side. The first electrically conductive layer (14; 14a, 14b) has a plurality of recesses (20, 20) and a plurality of subregions (24), and each subregion (24) is enclosed by at least one recess (20), leaving at least one region (22, 22) having a narrowed cross-section.

Claims

1. A semiconductor device for integration into a power module, the semiconductor device comprising (a) a semiconductor layer (10), a first side of the semiconductor layer (10) having a plurality of depressions (11); (b) an insulating layer (12; 12a, 12b), the insulating layer being deposited on the first side of the semiconductor layer (10) and engaging in the depressions (11); (c) a first electrically conductive layer (14; 14a, 14b) for contacting the semiconductor device (1, 2), the first electrically conductive layer (14; 14a, 14b) being deposited on the insulating layer (12a, 12b); and (d) a second electrically conductive layer (16) for contacting the semiconductor device (1, 2), the second electrically conductive layer (16) being deposited on a second side of the semiconductor layer (10) opposite to the first side; wherein the first electrically conductive layer (14; 14a, 14b) has a plurality of recesses (20, 20) and a plurality of subregions (24), and each subregion (24) is enclosed by at least one recess (20), leaving at least one region (22, 22) having a narrowed cross-section.

2. The semiconductor device according to claim 1, wherein at least some of the subregions (24) of the first electrically conductive layer (14; 14a, 14b) are enclosed by a plurality of recesses (20, 20), leaving a plurality of regions (22, 22) having a narrowed cross-section.

3. The semiconductor device according to claim 1, wherein the regions (22) having a narrowed cross-section in the first electrically conductive layer (14; 14a, 14b) each have a height (h.sub.A) between 100.0 nm and 1.0 μm and a width (b.sub.A) between 50.0 nm and 5.0 μm.

4. The semiconductor device according to claim 1, wherein the respective regions (22) having a narrowed cross-section are identical in height (h.sub.A) and identical in width (b.sub.A).

5. The semiconductor device according to claim 1, wherein the respective one subregion (24) of the first electrically conductive layer (14; 14a, 14b) at least partially covers, or completely covers, an opening of a depression (11), or extends radially beyond an edge of the respective opening of the depression (11).

6. The semiconductor device according to claim 1, wherein the respective one subregion (24) of the first electrically conductive layer (14; 14a, 14b) at least partially covers, or completely covers, a plurality of openings of associated depressions (11), or extends radially beyond edges of the respective openings.

7. The semiconductor device according to claim 1, wherein the recesses (20) have a partially circular, circular, rectangular or polygonal basic shape.

8. A semiconductor device for integration into a power module, the semiconductor device comprising (a) a semiconductor layer (10), a first side of the semiconductor layer (10) being provided with a plurality of depressions (11) as pits; (b) an insulating layer (12; 12a, 12b), the insulating layer being deposited on the first side of the semiconductor layer (10) and extending into the pits (11); (c) a first electrically conductive layer (14; 14a, 14b) for contacting the semiconductor device (3), the first electrically conductive layer (14; 14a, 14b) being deposited on the insulating layer (12; 12a, 12b) and extending into, but not filling (34), the pits (11); and (d) a second electrically conductive layer (16), the second electrically conductive layer (16) being deposited on a second side of the semiconductor layer (10) located opposite to the first side; wherein the insulating layer (12) has thickenings (30) in opening areas of the pits (11), a respective thickening (30) defining a conductive region (32) having a narrowed cross-section in the first electrically conductive layer (14; 14a, 14b).

9. The semiconductor device according to claim 8, wherein the regions (32) having a narrowed cross-section in the first electrically conductive layer (14) each have a first diameter (d.sub.1) between 100.0 nm and 2.0 μm.

10. The semiconductor device according to claim 8, wherein each pit (11) has, at least sectionwise, a second diameter (d.sub.2) in the opening area of the respective pit (11), wherein a ratio (d.sub.1:d.sub.2) of a first diameter (d.sub.1) to the second diameter (d.sub.2) of the conductive region (32) having the narrowed cross-section is between 1:2 and 1:20.

11. The semiconductor device according to claim 8, wherein the insulating layer (12; 12a, 12b) has, sectionwise, a first a layer thickness (t.sub.1), and the thickenings (30) of the insulating layer have a second layer thickness (t.sub.2), wherein a ratio (t.sub.1:t.sub.2) of the first layer thickness (t.sub.1) to the second layer thickness (t.sub.2) is between 100:105 and 100:150.

12. A semiconductor device for integration into a power module with at least one deactivatable power semiconductor, the semiconductor device comprising (a) a semiconductor layer (10), a first side of the semiconductor layer (10) having a plurality of depressions (11) as pits; (b) an electrically conductive layer (16), the electrically conductive layer (16) being deposited on a second side of the semiconductor layer (10) that is located opposite to the first side; (c) an insulating layer (12; 12a, 12b), the insulating layer being deposited on the first side of the semiconductor layer (10) and extending into the pits (11); (d) a further electrically conductive layer (14; 14a, 14b) for contacting the semiconductor device (3), the further electrically conductive layer (14; 14a, 14b) being deposited on the insulating layer (12) and the further electrically conductive layer (14; 14a, 14b) having a plurality of narrow sections (22, 32).

13. The semiconductor device according to claim 12, wherein each of the narrow sections (22, 32) connects an areally small portion (24) to an areally large or larger portion in an electrically conductive manner, but is also capable of disconnecting the small portion in an electrically separating manner.

14. The semiconductor device according to claim 12, wherein at least some of the narrow sections (32) are located in the depressions (11).

15. The semiconductor device according to claim 14, wherein the insulating layer (12) has thickenings (30) in opening areas of the depressions (11).

16. The semiconductor device according to claim 15, wherein the thickenings (30) in opening areas of the depressions (11) correspond to the narrow sections (32) of the further electrically conductive layer (14; 14a, 14b).

17. The semiconductor device according to claim 12, wherein the narrow sections (22) are located on the first side of the semiconductor layer (10), outside or above the depressions (11).

18. The semiconductor device according to claim 12, wherein one narrow section (22) is associated with a plurality of depressions (11).

19. The semiconductor device according to claim 12, wherein a plurality of narrow sections (22) are associated with a depression (11).

20. The semiconductor device according to claim 12, wherein the narrow sections (22, 32) are configured to be cut or split by a flow of current.

21. The semiconductor device according to claim 13, wherein each of the areally smaller portions (24) occupies a conductive area that is less than 1/10 or less than 1/100 of the area of the areally larger portion (14b).

22. The semiconductor device according to claim 14, wherein below each of the narrow sections (32) a cavity (34) is formed in the depression (11).

23. The semiconductor device according to claims 14 and 20, wherein melting of one of the narrow sections (32) will melt material that enters the cavity (34) located therebelow in the depression (11) in question.

24. A method of operating a power module including a multi-layer semiconductor device, (a) wherein narrow sections (22, 32) acting as electrical connection conductive paths in an electrically conductive layer (14; 14a, 14b) of the multi-layer semiconductor device melt at electrical currents higher than a predefined threshold value, and no longer conduct electrically, (b) whereby defective elements acting as capacitors are isolated, in a singulated form, from a plurality of elements of the multi-layer semiconductor device that are connected in parallel and act as capacitors.

25. The method according to claim 24, wherein the threshold value is between 20.0 mA and 500.0 mA.

26. The method according to claim 24, wherein melting of one of the narrow sections (32) will melt material that enters a cavity (34) located below the narrow section (32).

Description

INTRODUCTION TO THE DRAWINGS

[0083] The embodiments of the present invention are shown on the basis of examples and are not shown in a manner in which limitations from the figures or more concrete forms are read into the claims as long as these limitations or concretizations have not been incorporated in the latter. Like reference numerals in the figures designate like elements.

[0084] FIG. 1A shows, in a top view, a schematic partial view of a semiconductor device 1 having a plurality of annular, non-closed recesses 20 in a contacting layer 14 of the semiconductor device 1;

[0085] FIG. 1B shows a first schematic sectional view A-A of the semiconductor device 1;

[0086] FIG. 1C shows a second schematic sectional view B-B of the semiconductor device 1 in the region 22 between the two free ends of the recess 20, also referred to as narrow section 22;

[0087] FIG. 2 shows, in a top view, schematic representations of possible basic shapes of at least one—preferably of all—recesses 20 in the contacting layer 14 of the semiconductor device 1, which have at least one narrow section 22;

[0088] FIG. 3A shows, in a top view, a schematic partial view of a further semiconductor device 2 having a plurality of oval ring-shaped recesses 20 in a contacting layer 14 of the semiconductor device 2;

[0089] FIG. 3B shows a schematic sectional view C-C of the semiconductor device 2;

[0090] FIG. 4A shows a schematic sectional view of a further semiconductor device 3 in an embodiment without recesses in a first contacting layer 14 of the semiconductor device 3;

[0091] FIG. 4B shows a schematic sectional view D-D of the semiconductor device 3 for illustrating the region 32 with the narrowed cross-section; also this region will be referred to as narrow section 22.

DETAILED DESCRIPTION

[0092] FIG. 1A shows, in a top view, a schematic partial (sectionwise) view of a semiconductor device 1 having a plurality of annular recesses 20 in a contacting layer 14 of the semiconductor device 1. The recesses 20 are not closed. A portion 22 of the contacting layer 14 remains.

[0093] For the purpose of orientation, an x-y-z coordinate system is drawn in. The axis z is the height direction. The x-y axes circumscribe the plane in which the pit capacitors are arranged in a distributed manner.

[0094] In FIG. 1A, a total of nine recesses 20 are shown in the contacting layer 14 of the semiconductor device 1. However, the semiconductor device may have more than nine recesses 20, preferably several hundred recesses 20, each of them having the portion 22.

[0095] Through the recesses 20 in the contacting layer 14 as a first electrically conductive layer of the semiconductor device 1, regions 22 with narrowed cross-sections are defined in the first electrically conductive layer 14. What is shown here are (connection) webs 22. In addition, smaller subregions 24 are exempted in (or from) the first electrically conductive layer 14. In this context, “exempted” means that, parallel to the z-axis, a respective (side) surface is “separated” or delimited by a respective recess in the first electrically conductive layer, and that a subregion 24 will thus remain electrically conductively connected to the rest of the first electrically conductive layer only by the narrow sections 22 (also referred to as “webs”). The respective recesses 20 additionally delimit the subregions 24, with ends 20a and 20b of the respective recess 20 approaching each other closely and thus defining a lateral extension of the narrow section 22 (as a web).

[0096] A respective subregion 24 means a planar region of the first electrically conductive layer 14, which is exempted through the recess 20 and is connected to the planar region 14a of the first electrically conductive layer 14 only via the narrowed conductive cross-section. The conductive connection is intended to become non-conductive, when the exemption defined as a narrow section 22 becomes an exposure, i.e. is physically separated, as will be explained in more detail hereinafter.

[0097] The first electrically conductive layer 14 is to be understood functionally, with the planar region 14a and the regions 14b having a finger-shaped form, as will be explained hereinafter.

[0098] A view of section A-A is shown in FIG. 1B, and a view of section B-B is shown in FIG. 1C.

[0099] In FIG. 1B, it can be seen that the semiconductor device 1 is composed of a plurality of layers. A layer 16 constituting the lowermost layer when seen in the z-direction and representing a second electrically conductive layer of the semiconductor device 1 is used for electrically contacting the semiconductor device 1.

[0100] A semiconductor layer 10 is arranged on and above the second electrically conductive layer 16, respectively. The semiconductor layer 10 has a plurality of depressions 11, the number of depressions shown here being three. However, the semiconductor layer 10 may have significantly more than three depressions 11, preferably the semiconductor layer may have several hundred depressions 11.

[0101] An insulating layer 12 is deposited on the semiconductor layer 10. Corresponding to the surface of the semiconductor layer 10, the insulating layer 12 has a region 12a, which is flat and parallel to the x,y plane, and regions 12b whose outer contours correspond to the shape of the depressions 11 and engage in the depressions 11.

[0102] The number of depressions 11 may correspond to the number of recesses 20. The number of depressions 11 may be higher than the number of recesses 20. In a sectional view, the depressions 11 in FIG. 1B are U-shaped (2D, x,z-plane).

[0103] The depressions 11 may have a finger-shaped form (3D view). Finger-shaped means that each depression 11, which is recessed into the semiconductor layer 10 as a pit, may have a cylindrical portion and a hemispherical portion. Accordingly, an upper edge contour of an opening of a depression 11, as viewed in the z-direction, is defined by the cylindrical portion (circular edge contour).

[0104] The depressions 11 may also have other geometries. For example, the depressions 11 may be configured as trenches.

[0105] The depressions 11 may be arranged uniformly, i.e. at uniform distances (x,y plane) from one another, in the semiconductor layer 10.

[0106] The semiconductor layer 10 has a largest layer thickness in the semiconductor device. The depressions 11 may extend into the semiconductor layer 10 up to and beyond half of the layer thickness of the semiconductor layer 10.

[0107] The semiconductor layer is parallel to an x,y plane (it is planar).

[0108] The semiconductor layer 10 has deposited thereon an insulating layer 12. Corresponding to a surface contour of the semiconductor layer 10, the insulating layer 12 comprises a planar region 12a (parallel to the x,y plane) and regions 12b having a finger-shaped configuration, which engage in the depressions 11 and cover the side walls of the latter.

[0109] The insulating layer 12 may have a uniform layer thickness.

[0110] The insulating layer 12 has the first electrically conductive layer 14 deposited thereon. In FIG. 1B it can be seen that, corresponding to a surface contour of the insulating layer 12, the first electrically conductive layer 14 is divided into a planar region 14a (parallel to the x,y plane) and regions 14b having a finger-shaped form, which engage in the depressions 11 and fill them (as a filling material).

[0111] The partially dashed outlined and grayed area here indicates a position of a region 22 having a narrowed cross-section, viewed in the x,y plane.

[0112] A subregion 24 means a planar region of the first electrically conductive layer 14, which is exempted through the recess 20 and is connected to the planar region 14a of the first electrically conductive layer 14 only via a respective portion 22 having a narrowed cross-section, without taking into account the filling material 14b in a depression 11 that corresponds to the recess 20.

[0113] In this example, each recess 20 and each subregion 24, respectively, is associated with a respective depression 11. Each subregion 24 in the first electrically conductive layer 14 extends radially in the x,y plane up to and beyond an opening of a coated depression 11.

[0114] The recesses 20 are arranged in the first electrically conductive layer such that they each define, sectionwise, a planar region 12a and a finger-shaped recessed region 12b of the insulating layer 12.

[0115] Hence, the insulating layer 12 is to be understood functionally.

[0116] In FIG. 1C it can be seen that a region 22 having a narrowed cross-section, representative for all regions 22 having a respective narrowed cross-section in the first electrically conductive layer, has a width b.sub.A and a height h.sub.A, i.e. it has a cross-section h.sub.A.Math.b.sub.A.

[0117] The width b.sub.A and the height h.sub.A are configured such that the narrowed cross-section—compared to the recess 20—can conduct a current of a defined current level. Up to this current, the region 22 having a narrowed cross-section can conduct the electric current without damage being caused. A current above the defined current level is intended to cause melting or sublimation of the region 22 having a narrowed cross-section, so that current can no longer be conducted across this region.

[0118] Also a length of the region 22 having a narrowed cross-section may have an influence on the timing of the interruption of current conduction and may be adjusted accordingly.

[0119] The height h.sub.A of the region 22 having a narrowed cross-section may substantially be determined by a layer thickness of the planar region 14a of the first electrically conductive layer 14, and may preferably correspond to the layer thickness of the planar region 14a.

[0120] By melting or sublimating the region 22 having a narrowed cross-section, a region of the semiconductor device 1 forming an element that acts as a (pit) capacitor within the semiconductor device 1 can thus be electrically isolated from the rest of the semiconductor device 1 to the greatest possible extent. The exemption of the small subregion leads to a separation or exposure of the pit capacitor in question. It can here be said that the current destroying the narrow section could be the cause of a fault, in particular a short circuit of the one relief network (consisting of the RC element). The other pit capacitors connected in parallel continue to operate without any damage being caused.

[0121] FIG. 2 shows, in a top view, schematic representations of possible basic shapes of recesses 20 in a contacting layer 14 of a semiconductor device. One basic shape is here intended to be representative for all recesses 20 in the first electrically conductive layer 14 of a semiconductor device, e.g. semiconductor device 1.

[0122] The annular recess 20 (first row, first shape) corresponds to the shape as already shown and explained in FIG. 1A.

[0123] The recesses 20 may also have other basic shapes. The basic shape of the recesses 20 may be triangular (first row, second shape), square or rectangular (first row, third shape) or pentagonal or polygonal (first row, fourth shape). The depressions 11 may also be non-circular in shape, e.g. as trenches.

[0124] So far, an example has been considered in which one recess 20 is associated with one depression 11. However, a depression 11 may also have associated therewith a plurality of recesses 20, or a plurality of depressions may define an exempted subregion 24.

[0125] This is shown exemplarily in the second row of FIG. 2. The first shape in the second row of FIG. 2 still has a circular basic shape, but is formed by two semi-annular recesses 20 defining two regions 22 with a narrowed cross-section in the first electrically conductive layer. The current carrying capacity is doubled.

[0126] The same applies to the other design forms of the recesses 20. The various basic shapes (triangle, rectangle, polygon, etc.) remain essentially unchanged, but are formed by two or more than two recesses 20. The number of recesses 20, by means of which a subregion 24 is formed or exempted, correspondingly also determines the number of regions 22 having a narrowed cross-section, i.e. the number of narrow sections.

[0127] FIG. 3A shows, in a top view, a schematic partial view of a semiconductor device 2 having six oval ring-shaped recesses 20 in a contacting layer 14 of the semiconductor device 2. The contacting layer 14 is a first electrically conductive layer of the semiconductor device 2.

[0128] The recesses 20 in the first electrically conductive layer 14 of the semiconductor device 2 each enclose a subregion 24 in the first electrically conductive layer 14, leaving a region 22 having a narrowed cross section. Through the recesses 20, the subregions 24 are exempted on one side thereof.

[0129] A sectional view of the semiconductor device 2 (section C-C) is shown in FIG. 3B.

[0130] From the sectional view of FIG. 3B it can be seen that the semiconductor device 2 has a layer structure corresponding to that of the semiconductor device 1 according to FIG. 1A, 1B and 1C, with the difference that a respective recess 20 encloses two depressions 11, and one recess 20 is associated with two depressions 11, respectively.

[0131] A respective recess 20 may also be associated with more than two depressions 11. The function is the same as that in the case of FIG. 1. Disconnecting one pit capacitor then corresponds to electrically disconnecting a group of pit capacitors, in the example in question two.

[0132] FIG. 4A shows a schematic sectional view of a semiconductor device 3 in an alternative embodiment without recesses in a first contacting layer 14 of the semiconductor device 3.

[0133] The semiconductor device 3 has a layered structure or layered design. The lowermost layer 16, when seen in the z-direction, is a second electrically conductive layer for contacting the semiconductor component 3. The second electrically conductive layer 16 has deposited thereon a semiconductor layer 10.

[0134] The semiconductor layer 10 has deposited thereon an insulating layer 12. Corresponding to the surface of the semiconductor layer 10, the insulating layer 12 has a region 12a that is flat and parallel to the x,y plane, and regions 12b whose outer contours correspond to the shape of the depressions 11 and engage in the depressions 11, respectively.

[0135] The semiconductor layer 10 has a plurality of depressions 11, the total number of depressions 11 shown here being three.

[0136] The semiconductor device 3 may have more than three depressions 11, preferably the semiconductor device 3 may have several hundred depressions 11.

[0137] The depressions 11 may be arranged at uniform distances (x,y plane) from one another in the semiconductor layer 10.

[0138] The depressions 11 may extend on one side down to more than half of a layer thickness of the semiconductor layer 10, i.e. extend into the semiconductor layer 10 (in a negative z-direction).

[0139] The depressions 11 preferably have a finger-shaped form. This means that each depression 11 has, sectionwise, a cylindrical portion and a portion that is hemispherical in shape. Accordingly, an opening of the depression 11 has a circular edge contour.

[0140] The depressions may have a different shape, e.g. the shape of a parallelepiped or that of a trench. The depressions 11 enlarge a surface area of the semiconductor layer 10.

[0141] The semiconductor layer 10 has deposited thereon an insulating layer 12. Corresponding to the surface of the semiconductor layer 10, the insulating layer 12 has a region 12a that is flat and parallel to the x,y plane, and regions 12b whose outer contours correspond to the shape of the depressions 11 and engage in the depressions 11, respectively. In addition, the insulating layer 12 has, in each opening area of each depression 11, a thickening 30 that extends radially inwards (in the direction of an axis of the depression 11) from the respective cylindrical portion of the depression 11.

[0142] With the exception of the thickenings 30, the insulating layer 12 has a uniform layer thickness t.sub.1. The thickenings have a maximum layer thickness t.sub.2. The layer thickness t.sub.1 is smaller than the layer thickness t.sub.2 of the thickenings.

[0143] Corresponding to a surface geometry of the insulating layer 12, the first contacting layer 14, which represents the first electrically conductive layer, has regions 14b that engage in the coated depressions 11, and a region 14a that is parallel to the x,y plane.

[0144] Due to the thickenings 30 in the insulating layer 12, the first electrically conductive layer 14, and the regions 14b that engage in the coated depressions 11, respectively, each have a region 32 having a narrowed cross-section for each depression 11.

[0145] The first electrically conductive layer 14 may, for example, be grown or deposited on the insulating layer 12 (thermal oxidation, oxides or nitrides deposited from the gas phase, gas phase deposition, sputtering, etc.).

[0146] As a result of the process, electrically conductive material of the first electrically conductive layer 14 may pass through and deposit in the region 32 having a narrowed cross-section, but only until the region 32 having a narrowed cross-section will be closed by deposited material, so that a cavity 34, which is not filled with electrically conductive material (gas inclusion), will be formed below the region 32 having a narrowed cross-section. Accordingly, the depressions 11 coated with the insulating layer 12 may be filled only partially with material of the electrically conductive layer 14.

[0147] Each region 32 having a narrowed cross-section may in particular be configured such that it can conduct exclusively a current of a prespecified strength or magnitude without damage being caused. If a current above this current threshold flows through one of the regions 32 having a narrowed cross-section, this will have the effect that the region 32 having a narrowed cross-section melts. As a result, current can no longer be conducted through the region 32 having a narrowed cross-section.

[0148] Molten material of the region 32 can deposit in the cavity 34, which is not filled with material of the first semiconductor layer 14. As a result, current can no longer be conducted through the region 32 having a narrowed cross-section.

[0149] A (partial) sectional view of the semiconductor device 3 (section D-D) is shown in FIG. 4B.

[0150] In FIG. 4B, a total of nine depressions 11 are shown in a sectional view. As has already been mentioned above, the semiconductor device 3 may have a significantly higher number of depressions 11 (not shown).

[0151] Each finger-shaped depression 11 has, at least sectionwise, an insulating diameter d.sub.2 (in the sectionwise cylindrical portion of the depression). The region 32 having a narrowed cross-section has a conductive diameter d.sub.1 therein.

[0152] The diameter d.sub.2 of the depression is larger than the diameter d.sub.1 of the region 32 having a narrowed cross-section. The ratio of the two diameters to each other may, in particular, be configured such that the region 32 having a narrowed cross-section (the narrow section) of the first electrically conductive layer 14 can conduct a current of a specific strength without damage being caused. In other words, above this current threshold the narrow section 32 will melt.

[0153] In the event that this limit current is exceeded in one of the regions 32 having a narrowed cross-section, material in the diameter d.sub.1 will be melted, as has already been mentioned above, so that a region of the semiconductor device will electrically be isolated from the rest of the semiconductor device.