MILLIVOLT POWER HARVESTING FET CONTROLLER

Abstract

Circuits and methods for controlling a transistor that has first, second and third terminals, wherein a voltage level at said first terminal controls in part a current flow from said second terminal to said third terminal. A controller receives an voltage existing across the second and third terminals of the transistor, generates an isolated voltage and uses that voltage to power components of the controller. The controller provides a voltage to the first terminal of the transistor, whereby the controller regulates the voltage across the second and third terminals of the transistor by regulating the voltage provided to the first terminal.

Claims

1. A circuit comprising: a transistor comprising first, second and third terminals, wherein a voltage level at said first terminal controls create a current flow from said second terminal to said third terminal; and a voltage converter configured to receive a voltage existing across the second and third terminals of the transistor and generating an isolated voltage to power components of the controller, the controller being further configured to provide a voltage to the first terminal of the transistor, whereby the controller is operable to regulate the voltage across the second and third terminals of the transistor by regulating the voltage provided to the first terminal.

2. The circuit of claim 1 wherein the received voltage existing across the second and third terminals of the transistor is the controller's sole source of power.

3. The circuit of claim 1 wherein the controller is operable to maintain the voltage across the second and third terminals of the transistor at a predetermined target voltage by regulating the voltage provided to the first terminal of the transistor.

4. The circuit of claim 3 wherein said predetermined target voltage corresponds to a minimum voltage required to power the components of the controller.

5. The circuit of claim 1 wherein the transistor comprises a field-effect transistor (FET) and wherein said first terminal comprises the gate of the FET.

6. The circuit of claim 5 wherein the transistor comprises an n-channel FET (NFET) and wherein said second terminal comprises the source of the NFET, and said third terminal comprises the drain of the NFET.

7. A circuit comprising: a transistor comprising first, second and third terminals, wherein a voltage level at said first terminal controls create a current flow from said second terminal to said third terminal; and a controller comprising: a voltage converter configured to receive a voltage existing across the second and third terminals of the transistor and convert said voltage to a power supply voltage that is a higher voltage than said received voltage and isolated from a common ground; and a control circuit powered by said power supply voltage and configured to receive the voltage existing across the second and third terminals of the transistor and to provide a control voltage to the first terminal of the transistor, whereby the control circuit is operable to regulate the voltage across the second and third terminals of the transistor by regulating the control voltage provided to the first terminal.

8. The circuit of claim 7 wherein said voltage converter comprises a charge pump circuit configured to receive a voltage existing across the second and third terminals of the transistor and convert said voltage to a power supply voltage that is a higher voltage than said received voltage.

9. The circuit of claim 8 wherein the controller further comprises an oscillator configured to receive a voltage existing across the second and third terminals of the transistor and to generate an oscillating signal, and to provide the oscillating signal to the charge pump to drive the charge pump circuit.

10. The circuit of claim 8 wherein the controller further comprises a reservoir capacitor coupled to receive and store the power supply voltage generated by the charge pump circuit.

11. The circuit of claim 7 wherein the control circuit is operable to maintain the voltage across the second and third terminals of the transistor at a predetermined target voltage by regulating the voltage provided to the first terminal of the transistor.

12. The circuit of claim 11 wherein the control circuit comprises: a differential amplifier powered by the power supply voltage and having an inverting input coupled to the third terminal of the transistor and having an output coupled to the first terminal of the transistor; and an offset voltage source coupled between the second terminal of the transistor and a non-inverting input of the differential amplifier, the voltage of the offset voltage source corresponding to the target voltage across the second and third terminals of the transistor.

13. The circuit of claim 11 wherein said predetermined target voltage corresponds to a minimum voltage required to power the control circuit.

14. The circuit of claim 7 wherein the received voltage existing across the second and third terminals of the transistor is the control circuit's sole source of power.

15. The circuit of claim 7 wherein the transistor comprises a field-effect transistor (FET) and wherein said first terminal comprises the gate of the FET.

16. The circuit of claim 15 wherein the transistor comprises an n-channel FET (NFET) and wherein said second terminal comprises the source of the NFET, and said third terminal comprises the drain of the NFET.

17. A method of controlling a transistor comprising first, second and third terminals, wherein a voltage level at said first terminal controls create a current flow from said second terminal to said third terminal, the method comprising: receiving a voltage existing across the second and third terminals of the transistor; using said voltage existing across the second and third terminals of the transistor to power a control circuit using voltage isolated from a common ground; generating, with the control circuit, a control voltage based on the voltage existing across the second and third terminals of the transistor; and providing, with the control circuit, the control voltage to the first terminal of the transistor.

18. The method of claim 17 wherein said generating a control voltage comprises generating a control voltage such that the voltage across the second and third terminals of the transistor is substantially maintained at a predetermined target voltage.

19. The circuit of claim 18 wherein said predetermined target voltage corresponds to a minimum voltage required to power the control circuit.

20. The method of claim 17 wherein the received voltage existing across the second and third terminals of the transistor is the control circuit's sole source of power.

21. The circuit of claim 1 further comprising a battery powering a load, the battery and the load being isolated from ground.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 is a schematic circuit diagram of a circuit that includes a battery powering a load and that employs a transistor serving as reverse-current protection.

[0007] FIG. 2 is a schematic circuit diagram of an NFET transistor and an associated controller.

[0008] FIG. 3 is a flow chart representing a method of controlling a transistor.

[0009] FIG. 4 is the same circuit shown in FIG. 1, except that the battery and load are isolated from ground.

DETAILED DESCRIPTION

[0010] Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.

[0011] Illustrative aspects of the present disclosure are directed generally toward powering a transistor controller using the voltage existing across the terminals of the transistor being controlled. This general concept of the present disclosure is described herein with respect to controlling a series protection FET. It is to be appreciated, though, that aspects of the present disclosure can be applied to and implemented in a wide variety of applications.

[0012] FIG. 1 is a schematic circuit diagram of a circuit 100 that includes a battery 110 powering a load 120 and that employs a transistor 130 serving as reverse-current protection. FIG. 1 shows an n-channel FET (NFET) 130 in the power path of the circuit 100, but it is to be appreciated that a p-channel FET could be employed instead of the NFET, with corresponding changes in circuit operation as will be appreciated by those of skill in the art. The reverse-current protection transistor 130 can also be implemented with other transistor types besides field-effect transistors. In circuit 100, the body diode 135 of NFET 130 is oriented in the direction of normal current flow. The NFET 130 allows current flow in the forward direction, i.e., from the source 140 to the drain 145 of NFET 130 (i.e., from the battery 110 to the load 120), and blocks current in the reverse direction, i.e., from the drain 145 to the source 140 of NFET 130. A controller 160 receives inputs from the source 140 and the drain 145 of the NFET 130. The controller 160 generates a control signal, or gate driver signal, based on the drain-to-source voltage V.sub.ds. The controller 160 provides the gate driver signal to the gate 150 of the NFET 130. In this way, the controller 160 regulates the drain-to-source voltage V.sub.ds in a control loop.

[0013] FIG. 4 is a schematic circuit diagram of a circuit 400 that includes a battery for 10 powering a load 420 and that employs a transistor 430 serving as reverse-current protection. FIG. 4 shows an n-channel FET (NFET) 430 in the power path of the circuit 400, but it is to be appreciated that a p-channel FET could be employed instead of the NFET, with corresponding changes in circuit operation as will be appreciated by those of skill in the art. The reverse-current protection transistor 430 can also be implemented with other transistor types besides field-effect transistors. In circuit 400, the body diode 435 of NFET 430 is oriented in the direction of normal current flow. The NFET 430 allows current flow in the forward direction, i.e., from the source 440 to the drain 445 of NFET 430 (i.e., from the battery 410 to the load 420), and blocks current in the reverse direction, i.e., from the drain 445 to the source 440 of NFET 430. A controller 460 receives inputs from the source 440 and the drain 445 of the NFET 430. The controller 460 generates a control signal, or gate driver signal, based on the drain-to-source voltage Vds. The controller 460 provides the gate driver signal to the gate 450 of the NFET 430. In this way, the controller 460 regulates the drain-to-source voltage Vds in a control loop.

[0014] The difference between the circuits of FIGS. 1 and 4, is that in FIG. 4, ground is not utilized for the return path of current from the load 420 to the battery 410.

[0015] In an illustrative aspect of the present disclosure, the controller 160 also receives its power from the voltage drop across the NFET 130, i.e., from the drain-to-source voltage V.sub.ds.

[0016] FIG. 2 is a schematic circuit diagram of an NFET transistor 230 and an associated controller 260. In FIG. 2, NFET 230 corresponds to NFET 130 of FIG. 1, and controller 260 corresponds to controller 160 of FIG. 1. The controller 260 includes a voltage conversion circuit 265, an oscillator 270, a reservoir capacitor 275, a differential amplifier 280, and an offset voltage source 285. The controller 260 receives its power from the voltage drop across the NFET 230, i.e., from the drain-to-source voltage V.sub.ds. In an illustrative embodiment, the controller 260 receives all of its power from the drain-to-source voltage V.sub.ds, without receiving any additional power from other power sources. The voltage conversion circuit 265 receives the drain-to-source voltage V.sub.ds of the NFET 230 and converts it to a voltage level appropriate for powering components of the controller, such as differential amplifier 280. In certain illustrative embodiments of the present disclosure, the voltage converter 265 comprises a capacitive charge pump circuit, while in other illustrative embodiments, the voltage conversion circuit 265 comprises an inductive voltage boost circuit. The oscillator 270 receives the drain-to-source voltage V.sub.ds of the NFET 230, generates an oscillating signal, and provides the oscillating signal to the voltage conversion circuit 265 to drive the charge pump circuit. The oscillating signal generated by the oscillator 270 can be a square wave, a pulsed DC signal, or any other type of oscillating signal. The reservoir capacitor 275 stores the supply voltage generated by the voltage conversion circuit 265. The reservoir capacitor 275 can be either internal to the controller 260 or can be external. The controller 260 can be implemented in some cases without the reservoir capacitor. The supply voltage generated by the voltage converter 265 is used to power a control circuit, represented in FIG. 2 by the differential amplifier 280 and the offset voltage source 285, that regulates the drain-to-source voltage V.sub.ds of the NFET 230 by controlling the voltage of a control signal provided to the gate 250 of the NFET 230 in a control loop based on said drain-to-source voltage V.sub.ds.

[0017] The voltage generated by the voltage converter 265 used to power the differential amplifier 280 is isolated from ground, whether or not the reservoir capacitor 275 is utilized. In the illustrative embodiment of FIG. 2, the voltage of the offset voltage source 285 is added to the source voltage of the NFET 230 and the summed voltage signal is provided to the non-inverting input of the differential amplifier 280. The voltage level of the offset voltage source 285 corresponds to a target voltage level of the drain-to-source voltage V.sub.ds. The drain voltage of the NFET 230 is provided to the inverting input of the differential amplifier 280. The output of the differential amplifier 280 is provided to the gate 250 of the NFET 230. In this way, the control circuit represented by the differential amplifier 280 and the offset voltage source 285 works to maintain the drain-to-source voltage V.sub.ds at a voltage level substantially corresponding to the target voltage represented by the offset voltage source 285.

[0018] In operation, at startup, because of the body diode orientation of the N-channel FET 230, there will be initial current flowing through the body diode 235 if the load 120 is on. Therefore, even if the controller 260 is not powered, this will not interrupt the flow of current. However, as the current starts to flow through the body diode 235, a voltage will be generated across the source 240 and drain 245 of the NFET 230, specifically the voltage of a PN junction. This voltage can vary from NFET to NFET, and across temperatures, but nominally may be around 0.5V-0.7V. This voltage is also seen by the controller 260, across the source terminal 240 and the drain terminal 245 of the NFET 230. Using this voltage, the controller 260 will have enough voltage to turn on and startup its own circuitry, namely the voltage conversion circuit 265 and the oscillator 270.

[0019] The voltage conversion circuit 265 uses the body voltage, i.e., the drain-to-source voltage V.sub.ds (0.5V-0.7V) to generate an internal supply voltage. In the illustrative embodiment of FIG. 2, this internal supply voltage is shown to be approximately 5V, but this voltage level is merely illustrative and other internal supply voltage levels can be used. In an illustrative embodiment, the voltage converter 265 generates anywhere from approximately 0.5 mWatts to 10 mWatts. The controller 260 then enters the regulation mode, wherein it varies the gate voltage of the NFET 230 in a controlled loop to keep the drain-to-source voltage V.sub.ds at the desired target level. In the illustrative embodiment of FIG. 2, this target voltage is shown to be 50 mV, but this voltage level is merely illustrative and other target V.sub.ds levels can be used. In an illustrative embodiment, the controller 260 maintains the gate voltage at a level that is just high enough to give sufficient V.sub.ds to keep the voltage conversion circuit 265 running and generating the internal supply voltage (5V). As mentioned, this internal supply voltage is used to power the differential amplifier 280 and/or other control circuitry.

[0020] The regulated source-to-drain voltage V.sub.ds of the NFET 230 is dependent on the threshold voltage (V.sub.threshold) of the NFET device used. Therefore, the regulation self-adjusts when V.sub.threshold fluctuates across temperature by varying the gate voltage to match the V.sub.ds.

[0021] In the illustrative embodiment of FIG. 2, the controller 260 is shown to include a single voltage conversion circuit 265. In an alternative embodiment, the controller 260 may include two separate voltage conversion circuits in order to accommodate the two different V.sub.ds levels that exist at start-up and in the regulation mode. For example, the controller 260 can include a first voltage conversion circuit configured to receive a V.sub.ds of 0.5V-0.7V at start-up and convert said V.sub.ds to the level of the internal supply voltage (e.g., 5V), and a second voltage conversion circuit configured to receive a V.sub.ds of approximately 50 mV in the regulation mode and convert that V.sub.ds to the level of the internal supply voltage. Alternatively a single voltage conversion circuit 265 can be figured to operate at the V.sub.ds levels of both the start-up and regulation modes. Similarly, while FIG. 2 shows a single oscillator 270, in an alternative embodiment the controller 260 can include two separate oscillators in order to accommodate the two different V.sub.ds levels that exist at start-up and in the regulation mode.

[0022] FIG. 3 is a flow chart representing a method of controlling a transistor comprising first, second and third terminals, wherein a voltage level at said first terminal controls in part a current flow from said second terminal to said third terminal. At step 300, a voltage existing across the second and third terminals of the transistor is received. At step 310, the voltage existing across the second and third terminals of the transistor is used to power a control circuit. At step 320, the control circuit generates a control voltage based on the voltage existing across the second and third terminals of the transistor. At step 330, the control circuit provides the control voltage to the first terminal of the transistor.

[0023] It is noted that the embodiments disclosed herein are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure. Furthermore, in some instances, some features may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the broad inventive concepts disclosed herein.