Clamp based ESD protection circuits

Abstract

An electro-static discharge (ESD) protection circuit utilizes a gate-drain breakdown characteristic of high electron mobility transistors (HEMTs) in a dual stacked configuration to provide a discharge path for electro-static discharges, while having a minimal effect on the associated circuit which is being protected.

Claims

1. An ESD (Electro-static Discharge) protection circuit comprising: an input node; a first resistor; a second resistor; a first transistor comprising a first drain contact connected to the input node, a first gate contact, and a first source contact connected to the first gate contact via the first resistor; and a second transistor comprising a second source contact connected to the first source contact, a second gate contact connected to the second source contact via the second resistor, and a second drain contact in electrical communication with a ground, wherein the occurrence of an ESD event at the input node causes a junction in the first transistor between the first drain contact and the first gate contact to break down such that current flows through the first transistor from the first drain contact to the first gate contact.

2. The ESD protection circuit of claim 1, wherein the ESD protection circuit is configured to turn ON when a voltage at the input node is equal to or greater than a positive trigger voltage, and is configured to turn ON when the voltage at the input node is less than or equal to a negative trigger voltage.

3. The ESD protection circuit of claim 2, wherein the first transistor and the second transistor are pHEMTs (pseudomorphic high electron mobility transistors).

4. The ESD protection circuit of claim 3, wherein the first transistor and second transistor are enhanced mode transistors.

5. The ESD protection circuit of claim 4, wherein the first transistor and the second transistor are configured to provide the positive trigger voltage based on the following equation: positive trigger voltage equals a drain-gate breakdown voltage of the first transistor plus a threshold voltage of the first transistor.

6. The ESD protection circuit of claim 5, wherein the second transistor is substantially identical to the first transistor, and the positive trigger voltage is equal and opposite to the negative trigger voltage.

7. The ESD protection circuit of claim 1, further comprising a third transistor and a third resistor, wherein the third transistor includes a third source contact, a third gate contact, and a third drain contact, wherein the third transistor is configured such that the third source contact is connected to the second drain contact, the third gate contact is connected to a third gate end of the third resistor, and the third drain contact is in electrical communication with the ground, and wherein the third resistor is configured such that a second gate end of the third resistor is connected to the second gate contact.

8. The ESD protection circuit of claim 7, wherein the ESD protection circuit is configured to turn ON when a voltage at the input node is equal to or greater than a positive trigger voltage, and is configured to turn ON when the voltage at the input node is less than or equal to a negative trigger voltage, wherein the first and second and third transistors are pHEMTs (pseudomorphic high electron mobility transistors), wherein the first, second, and third transistors are enhanced mode transistors, wherein the first, second, and third transistors are configured to provide the positive trigger voltage based on the following equation: positive trigger voltage equals a drain-gate breakdown voltage of the first transistor plus the threshold voltage of the first transistor, and wherein the first, second, and third transistors are substantially identical.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

(2) FIG. 1A is an illustrative dual clamp schematic.

(3) FIG. 1B illustrates a drain-gate breakdown current.

(4) FIG. 1C illustrates an ESD (Electro-Static Discharge) current flow.

(5) FIG. 1D is an illustrative dual clamp layout.

(6) FIG. 2A is an illustrative dual clamp during a positive ESD event.

(7) FIG. 2B is an illustrative dual clamp during a negative ESD event.

(8) FIG. 3A illustrates positive TLP IV and leakage curves.

(9) FIG. 3B illustrates negative TLP IV and leakage curves.

(10) FIG. 4 illustrates the capacitance of an unbiased dual clamp as a function of frequency.

(11) FIG. 5 illustrates the insertion loss as a function of power.

(12) FIG. 6 illustrates the insertion gain as a function of power.

(13) FIG. 7A illustrates EVM (Error Vector Magnitude) as a function of power.

(14) FIG. 7B illustrates second and third harmonics as a function of power.

(15) FIGS. 8A through 8D illustrate various embodiments of the present disclosure.

DETAILED DESCRIPTION

(16) The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

(17) FIG. 1A is an illustrative dual clamp schematic of one embodiment of the present disclosure. The structure (Dual E-clamp) includes two pHEMT clamps connected in back to back configuration. Each clamp consists of an E-mode Field Effect Transistor (E_FET) with a resistor (R.sub.trig) connected between gate and source.

(18) Specifically, the first transistor E_FET_1 is defined by three nodes: DRAIN_1, GATE_1, and SOURCE. The second transistor E_FET_2 is defined by three nodes: DRAIN_2, GATE_2, and SOURCE. Note that SOURCE is a common node which serves as the source for the first transistor and as the source for the second transistor in a two FET back-to-back configuration.

(19) Regarding the first transistor, DRAIN_1 serves as an input node for an RF port labeled SIGNAL. The DRAIN_1 node is connected to the RF port labeled SIGNAL that needs to be ESD protected. A first trigger resistor Rtrig1 connects GATE_1 to SOURCE. The node SOURCE is a common source connecting the source of the first transistor to the source of the second transistor.

(20) Regarding the second transistor, DRAIN_2 is connected to ground. Additional transistors may be placed in series with the first and second transistor (see FIGS. 8A and 8D). A second trigger resistor Rtrig2 connects GATE_2 to SOURCE. Again, the node SOURCE is a common source connecting the source of the first transistor to the source of the second transistor.

(21) During normal operation (no ESD events), the clamp is OFF, and no current (except a very small leakage current) flows through the clamp. An RF processing circuit associated with the clamp (and connected to the SIGNAL input) operates normally, with only a slight effect from the small leakage current and from the capacitance of the clamp. For example, the associated circuit may be a switch or may be a power amplifier. The working principles during positive and negative ESD events are depicted in the following figures.

(22) FIG. 1B illustrates a drain-gate breakdown current I.sub.DG1. During a positive ESD event, as the SIGNAL voltage approaches (or exceeds) the drain-gate breakdown voltage (BVdgo1) of the first transistor, the leakage through the drain-gate junction of the first transistor increases, and a drain-gate breakdown current I.sub.DG1 flows from DRAIN_1 to GATE_1, and then flows through resistor Rtrig1. As the voltage V.sub.GS1 from GATE_1 to SOURCE increases beyond the threshold voltage Vth1 of the first transistor, the first transistor acts as a clamp.

(23) In addition to triggering the clamp, the value of Rtrig1 needs to be large enough to prevent thermal runaway once the gate-drain junction of the first transistor breaks down.

(24) A small portion of this drain-gate breakdown current I.sub.DG1 flows through resistor Rtrig2 to GATE_2 to turn on the second transistor (which acts as a diode with a turn on voltage of Vth2), and the remainder (the majority) of this (ESD)current I.sub.DG1 flows through the SOURCE and through the second transistor (which acts as a shunt) as I.sub.DIODE.

(25) FIG. 1C illustrates an ESD current flow. The dual clamp device is triggered by a trigger voltage at the RF SIGNAL input of Vtrig=BVdgo1+Vth2. Preferably, the transistors are identical, and would have the same threshold voltage (Vth1=Vth2).

(26) During a negative ESD event, the functionalities of the two transistors reverse.

(27) FIG. 1D is an illustrative dual clamp layout. An 8 finger, 50 μm gate width and 0.5 μm gate length device with A 1000Ω resistor (R.sub.trig) was chosen to meet a 1000V Human Body Model (HBM) ESD requirement. These values are dependent upon the process and could be varied based on the ESD requirement and process parameters.

(28) FIG. 2A is an illustrative dual clamp during a positive ESD event, and is similar to FIG. 1B, but more clearly illustrates that the first transistor acts as a clamp and the second transistor acts as a forward based diode.

(29) FIG. 2B is an illustrative dual clamp during a negative ESD event, and is similar to FIG. 2A except operating in reverse.

(30) FIG. 3A illustrates positive TLP IV and leakage curves. A transmission line pulser (TLP) is a universally accepted ESD characterization tool which can monitor the voltage and current at the device under test (DUT) during an ESD event. A 10 ns rise-time, 100 ns pulse width square pulse was generated using the pulser. The above mentioned pulse width and rise time was chosen to mimic a Human Body Model (HBM) type ESD event.

(31) Specifically, transmission line pulsing (TLP) test results from a stand-alone clamp structure (not connected to any RF processing circuit) are shown in FIG. 3A. The solid line indicates TLP current versus TLP voltage (bottom axis). The dashed line indicates TLP current versus leakage current (ILeakage). The dashed line is a constant current that is measured after every single pulse point to make sure that the structure is not destroyed.

(32) Points A through E on the solid line correspond to points A′ through E′ on the dashed line, respectively.

(33) Regarding the solid line, from A to B the TLP voltage (signal voltage or voltage at DRAIN_1) is increased from 1V to 21V (plotted in bottom X axis) and the corresponding TLP current is measured (plotted in Y-axis). Region A to B of the solid line (TLP curve) shows that as the voltage increases from 1V to 21V, the TLP current is close to 0 Amps (negligible) indicating that the structure is OFF. This denotes that any RF signal which has a voltage level less than 21V will NOT trigger the ESD structure. After every voltage step, a leakage test is performed on the ESD structure to determine if the structure is functional. This is shown by the dashed line A′-B′. The leakage current is plotted in top X-axis vs TLP current in Y-axis. Since TLP current did not change (almost 0 Amp) in region A-B, region A′-B′ corresponds to single point, and the leakage current is 1E−9 Amp. At point B on the solid line, the clamp is triggered at about 21V.

(34) Points B to C in the solid line correspond to “snap-back region” points B′ to C′ in the dashed line. When the TLP voltage exceeds 21V, the structure turns ON, snaps back and clamps the voltage to 14V (point C). After every single test point between B and C, a leakage test is performed and is shown in B′-C′ region of the dotted line. The leakage current doesn't change (remains around 1E−9) indicating the device or structure is still functional.

(35) Points C to D in the solid line correspond to points C′ to D′ in the dashed line. Once the device turns ON, as the test voltage is increased, the TLP current increases and there is a marginal increase in TLP voltage until the device's maximum current handling capability (which depends on the size of the device) is reached.

(36) Points D to E in the solid line correspond to points D′ to E′ in the dashed line. Failure of the clamp occurs at points E and E′. For this particular device size, region D corresponds the maximum current handling of the structure and hence signifies the TLP current handling of this particular structure. This structure was specifically designed to meet 1000V HBM ESD rating. The TLP current rating required to meet 1000V HBM rating is approximately 0.67 A. The size of the FETs can be increased/decreased to change the TLP current handling (and the ESD rating) of the structure.

(37) As expected, the pulsed IV curves are similar for positive and negative ESD events (see FIG. 3B in comparison to FIG. 3A). Leakage measurements were performed at a constant DC voltage after every single TLP pulse voltage. Any shift in the DC leakage current is considered as a device failure. The TLP current level at which the failure occurs determines the TLP current handling of the clamp. The structure has a trigger voltage of ±21V and can handle ±0.7 A of TLP current. The measured HBM rating of this structure is 1400V. As mentioned earlier, the trigger voltage is process dependent and the size of the FETs could be varied to obtain the desired ESD protection level.

(38) FIG. 3B illustrates negative TLP IV and leakage curves. FIG. 3B is similar to FIG. 3A, but for a negative ESD event.

(39) Loading capacitance is a very important parameter defining an ESD structure. Since the proposed structure has two clamps in series, the effective capacitance of the ESD structure is half of the capacitance of each clamp.

(40) The channel is OFF during normal operation and hence the drain-source capacitance (C.sub.ds) for each clamp is low. For each clamp, the gate-source (C.sub.gs) and gate-drain (C.sub.gd) fringing capacitance are in series which reduces the overall capacitance for each clamp. The above capacitances (C.sub.ds, C.sub.gs, and C.sub.gd) are capacitances for a single transistor or clamp.

(41) FIG. 4 illustrates the capacitance of an unbiased dual clamp as a function of frequency. There is generally a reduction in the capacitance at higher frequencies, but for frequencies beyond 2 GHz the capacitance of the dual clamp is fairly constant (around 120 fF). This constancy is an important property because non-linearities in system performance are caused mainly due to the change in capacitance over frequency. Thus, this illustrative dual clamp provides relatively constant capacitance from 2 GHz to 6 GHz. The inventors use the term “dual clamp” to describe this structure, because one of the transistors functions as a clamp for a positive ESD event, and the other transistor functions as a clamp during a negative ESD event.

(42) FIG. 5 illustrates the insertion loss as a function of power. Specifically, FIG. 5 shows the insertion loss as a function of power of the standalone dual clamp measured at matched (50Ω) conditions. FIG. 5 does not show the compression point because the test setup could not (at that time) apply an RF signal >30 dBm. As the power level increases, the voltage swing increases. Once the voltage swing exceeds the trigger voltage of the clamp, the clamp would turn ON and start clipping the RF signal. The structure was added to Pout node of a product (RF5611), and therefore the power was labeled Pout (although it is actualy Pin relative to the structure). FIG. 5 indicates that the standalone clamp does not turn ON up to 30 dBm during a continuous wave (CW) power sweep.

(43) For a Front End Module (Low Noise Amplifier with a SP3T switch), the maximum power rating of the WLAN Transmit (TX) port of the switch is 30 dBm.

(44) FIG. 6 illustrates the insertion gain as a function of power. Specifically, FIG. 6 shows the large signal insertion loss from the TX to Antenna (ANT) port. Power sweep data shows that the clamp does not compress even at 30 dBm. This baseline die was laid out without ESD protection and compared with another die where the ESD clamp structure was added to the TX port. Insertion loss is a positive number. For example, 0.9 dB insertion loss means the signal is degraded by 0.9 dB.

(45) FIG. 7A illustrates a linearity metric EVM (Error Vector Magnitude) as a function of power. The clamp has marginal impact on the EVM linearity metric.

(46) FIG. 7B illustrates second and third harmonics as a function of power, with and without the dual clamp. The dual clamp has marginal impact on the linearity metrics of second and third harmonics.

(47) FIG. 8A though 8D illustrate various embodiments of the present disclosure. In FIG. 8A, multiple clamps are added in series to increase the effective trigger voltage. This increases the maximum power handling of the clamp.

(48) In FIG. 8B, a dual gate FET is used. In FIG. 8C, a triple gate FET is used. Multiple gate FETs may be more area efficient when compared with series connected back to back single clamps. In FIG. 8D, multiple claims are added in series to increase the effective trigger voltage. All such variations are considered within the scope of the present disclosure.

(49) Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.