Layered substrate with a miscut angle comprising a silicon single crystal substrate and a group-III nitride single crystal layer

Abstract

A step-flow growth of a group-III nitride single crystal on a silicon single crystal substrate is promoted. A layer of oxide oriented to a <111> axis of silicon single crystal is formed on a surface of a silicon single crystal substrate, and group-III nitride single crystal is crystallized on a surface of the layer of oxide. Thereupon, a <0001> axis of the group-III nitride single crystal undergoing crystal growth is oriented to a c-axis of the oxide. When the silicon single crystal substrate is provided with a miscut angle, step-flow growth of the group-III nitride single crystal occurs. By deoxidizing a silicon oxide layer formed at an interface of the silicon single crystal and the oxide, orientation of the oxide is improved.

Claims

1. A layered substrate comprising a silicon single crystal substrate and a wurtzite group-III nitride single crystal layer, when: an axis orthogonal to a normal line on a surface of the silicon single crystal substrate and overlapping a <11-2> axis of the silicon single crystal when observed from the direction of the normal line is a y-axis; an axis orthogonal to the normal line and the y-axis and configuring three orthogonal axes is an x-axis; a plane including the normal line and the y-axis is an ny-plane; a plane including the normal line and the x-axis is an nx-plane; an axis wherein a <111> axis of the silicon single crystal is projected onto the ny-plane is a <111>ny axis; an axis wherein the <111> axis is projected onto the nx-plane is a <111>nx axis; an axis wherein a <0001> axis of the group-III nitride single crystal is projected onto the ny-plane is a <0001>ny axis; an axis wherein the <0001> axis is projected onto the nx-plane is a <0001>nx axis; a rotation angle measured in the ny-plane from the normal line to the <111>ny axis is θx0; a rotation angle measured in the nx-plane from the normal line to the <111>nx axis is θy0; a rotation angle measured in the ny plane from the normal line to the <0001>ny axis is θx1; and a rotation angle measured in the nx-plane from the normal line to the <0001>nx axis is θy1; wherein, absolute value of θx0>absolute value of θy0, and absolute value of θx1>absolute value of θy1, and when the ny-plane was viewed in cross-section, the <111> axis of the silicon single crystal and the <0001> axis of the group-III nitride single crystal are inclined in the same direction with respect to the normal line.

2. The layered substrate according to claim 1, wherein the group-III nitride single crystal is GaN.

3. The layered substrate according to claim 1, wherein the relationship θx1/θx0=0.6 to 1.0 is satisfied.

4. The layered substrate according to claim 1, wherein the absolute value of θx0 is 0.1° or more.

5. The layered substrate according to claim 1, wherein the absolute value of θx0 is 1.0° or less.

6. The layered substrate according to claim 1, wherein a surface of the group-III nitride single crystal layer has a step and terrace shape.

7. The layered substrate according to claim 6, when average value of a terrace width is W, and a lattice constant of the <0001> axis of the group-III nitride single crystal is C, wherein, a relationship of absolute value of (W×tan θx1)=0.5×C to 2.0×C is satisfied.

8. The layered substrate according to claim 1, wherein layer thickness of the group-III nitride single crystal layer is 1.5 μm or less.

9. The layered substrate according to claim 1, wherein dislocation density of the group-III nitride single crystal layer is 5×10.sup.8 cm.sup.−2 or less.

10. The layered substrate according to claim 1, wherein a SiOx layer, a layer of oxide other than SiOx, and a group-III nitride single crystal layer are stacked in sequence on the silicon single crystal substrate, and x<2.

11. The layered substrate according to claim 10, wherein the layer of oxide other than SiOx is formed by an oxide having larger enthalpy of formation than silicon oxide.

12. The layered substrate according to claim 11, wherein the layer of oxide other than SiOx is an alumina layer.

13. The layered substrate according to claim 12, wherein the alumina layer is formed by an alpha-phase alumina structure.

14. The layered substrate according to claim 12, wherein layer thickness of the alumina layer is 0.5 to 20 nm.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 shows in three dimensions the direction of a <0001> axis of group-III nitride single crystal grown by step-flow growth on a plane (xy-plane) that is not orthogonal to a <111> axis of silicon single crystal.

(2) FIG. 2 (a) shows the relationship of the <111> axis and the <0001> axis viewed cross-sectionally in a plane including a normal line n and a y-axis, (b) shows the relationship of the <111> axis and the <0001> axis viewed cross-sectionally in a plane including the normal line n and an x-axis, and (c) shows the relationship of the <111> axis and the <0001> axis observed from the normal line direction.

(3) FIG. 3 schematically shows the layered structure of a layered substrate comprising a silicon single crystal substrate having a miscut angle, a silicon oxide layer having an oxidation valence less than 2, an oxide crystal with larger enthalpy of formation than silicon oxide, and group-III nitride single crystal grown by step-flow growth.

(4) FIG. 4 shows an XPS spectrum of a silicon oxide layer before thermal processing and a silicon oxide layer after thermal processing.

(5) FIG. 5 shows the relationship between a miscut angle of the silicon single crystal substrate and a miscut angle of group-III nitride single crystal layer.

(6) FIG. 6 is an AFM image of a surface of group-III nitride single crystal grown by step-flow growth.

(7) FIG. 7 shows the relationship between layer thickness and dislocation density of group-III nitride single crystal grown by step-flow growth.

(8) FIG. 8 shows the layered structure of a layered substrate obtained by growing group-III nitride single crystal on a group-LIT nitride single crystal substrate having a miscut angle.

(9) FIG. 9 shows the layered structure of a layered substrate obtained by growing group-III nitride single crystal on a silicon single crystal substrate having a miscut angle.

(10) FIG. 10 schematically shows an apparatus for growing a group-III nitride single crystal layer with few crystal defects on a silicon single crystal substrate.

DESCRIPTION OF EMBODIMENTS

(11) Substantial features of the below embodiment will be summarized.

(12) (Feature 1) θx0>>θy0, namely θx0 is much larger than θy0. That is, a <111> axis of a silicon single crystal substrate is exclusively inclined to a <11-2> direction, and is hardly inclined to a <1-10> direction.

(13) (Feature 2) A surface of the silicon single crystal substrate is washed, is exposed to 1% hydrofluoric acid, is rinsed with pure water and then dried, thereby preparing a silicon single crystal substrate on which a thin native oxide layer is stacked on a surface.
(Feature 3) An alumina layer is formed by ALD (atomic layer deposition) method.
(Feature 4) Alternatively, an alumina layer is formed by sputtering.
(Feature 5) Thermal processing is performed at a temperature at which the alumina layer is crystallized.
(Feature 6) Thermal processing is performed at a temperature at which the alumina layer is crystallized to alpha-phase.
(Feature 7) Thermal processing is performed at 1000 to 1200° C.
(Feature 8) Thermal processing is performed in a noble gas.
(Feature 9) Epitaxial growth of group-III nitride single crystal is promoted by the metal-organic chemical vapor deposition (MOCVD) method.
(Feature 10) First, crystal growth of AlN and then crystal growth of GaN are promoted. A group-III nitride single crystal layer having a heterojunction is formed.

Embodiments

(14) (Preparation of Silicon Single Crystal Substrate)

(15) First, a silicon single crystal substrate having a miscut angle is prepared. At this juncture, a relationship is realized in which <11-2> axis of the silicon single crystal is inclined with respect to a substrate surface, and <1-10> axis is hardly inclined with respect to the substrate surface. That is, a surface is exposed which satisfies the relationship of a <111> axis being inclined exclusively in the <11-2> direction from a normal line on the substrate surface. That is, θy0 shown in FIG. 1 is nearly zero, and θx0 is caused to have a value. θy0 need not be precisely zero, but may have a small value.

(16) Generally, a relationship tan θ0=(tan.sup.2 θx0+tan.sup.2 θy0).sup.1/2 is satisfied. Here, θ0 is an angle formed by the normal line n and the <111> axis of the silicon single crystal. In a case where θy0 is small, θ0 and θx0 are approximately equal. An absolute value of θx0 (approximately equal to θ0) is inclined in a range of 0.1° to 1.0°. Similarly, tan θ1=(tan.sup.2 θx1+tan.sup.2 θy1).sup.1/2. Here, θ1 is an angle formed by the normal line n and a <0001> axis of group-III nitride single crystal.

(17) When absolute value of θx0 is 0.1° or less, an average value of a width W of terraces 14 shown in FIG. 3 becomes too wide (1 μm or more), two-dimensional nucleation and growth starts on the terraces 14, and there is the chance that the irregularities shown in FIG. 9 occur. When the absolute value of θx0 is 1.0° or more, an inclination angle of the terraces 14 shown in FIG. 3 becomes too large, and a height D of steps 12 becomes too large. It is known, in step-flow growth, that when a step grown at one time has a thickness of 1 or 2 atomic layers, a crystal layer with few crystal defects and a flat surface is grown (a repeated step-terrace shape that varies in thickness within a range of 1 or 2 atomic layers is macroscopically extremely flat). When the absolute value of θx0 is 1.0° or more, there is the possibility of the steps grown at one time being thick, and the step bunching phenomenon occurring.

(18) (Creation of Silicon Oxide Layer)

(19) When a silicon single crystal substrate having a miscut angle is prepared, usually, a native oxide layer is formed on a surface of the prepared silicon single crystal substrate. Since the native oxide layer may be too thick, the following processes are performed.

(20) (1) The silicon single crystal substrate is washed with sulfuric acid and hydrogen peroxide, is washed with ammonia and hydrogen peroxide, and/or is washed with hydrochloric acid and hydrogen peroxide;

(21) (2) a part of the native oxide layer is removed and thinned by exposing the silicon single crystal substrate to 1% hydrofluoric acid;

(22) (3) the silicon single crystal substrate is rinsed with pure water and then dried.

(23) The surface of the silicon single crystal substrate which has undergone the aforementioned processes is covered with a thin silicon oxide layer.

(24) (Creation of Alumina Layer)

(25) An alumina layer having a thickness of 0.5 to 20 nm is formed. For this purpose, it is preferred that the alumina layer is formed by ALD (atomic layer deposition) method. The alumina layer may be formed by the sputtering method. If the thickness of the alumina layer is 0.5 nm or less, the surface of the silicon oxide layer is not completely covered. If the thickness of the alumina layer is 20 nm or more, the orientation of the <111> axis of the silicon single crystal is not transmitted to a surface of the alumina layer even if thermal processing, to be described, is performed. In this step, it is preferred that an alumina layer having a thickness of 1 to 3 nm is formed.

(26) (Thermal Processing)

(27) Thermal processing is performed in which the silicon single crystal substrate on which the silicon oxide layer and the alumina layer have been stacked is heated to 1000 to 1200° C. Thermal processing at 1000° C. or below is insufficient, and at 1200° C. or more the Al of the alumina and the Si of the silicon oxide layer react, impairing crystalline. By performing the thermal processing, the alumina is crystallized into alpha-phase. Alumina has larger enthalpy of formation than silicon oxide, and when the alumina layer is crystallized, the adjacent silicon oxide is deoxidized, and SiO.sub.2 changes into SiOx (x<2). FIG. 4 shows an XPS spectrum of the Si of the silicon oxide layer (is orbital) before thermal processing (curve C1), and an XPS spectrum of the silicon oxide layer after thermal processing (curve C2). The height of peaks A, B is reduced in the XPS spectrum (C2) after thermal processing compared to the XPS spectrum (C1) before thermal processing. XPS spectrum (C2) is similar to XPS spectrum of the silicon single crystal. By performing the thermal processing, the silicon oxide layer is deoxidized, and it is confirmed that it has been altered to SiOx (x<2).

(28) When the silicon oxide layer is deoxidized and the alumina layer is crystallized into alpha-phase, the influence of the <111> axis of the silicon single crystal being inclined is propagated to the surface of the alumina layer, and a c-axis of the alpha-phase alumina crystal also inclines. As shown in FIG. 1, the <111> axis of the silicon single crystal is primarily inclined to the <11-2> direction. Consequently, the c-axis of the alumina crystal is also primarily inclined to the <11-2> direction.

(29) It is preferred that thermal processing is performed in a noble gas such as argon, etc. When thermal processing is performed in a noble gas, nitriding of the silicon single crystal can be prevented.

(30) (Alternative to Creation and Thermal Processing of Alumina Layer)

(31) As described above, the aim of forming the alumina layer and performing thermal processing is to crystallize the oxide layer while deoxidizing the silicon oxide layer, and to align the orientation of the oxide crystal with the crystal orientation of the silicon single crystal. The material that generates this phenomenon is not restricted to the alumina layer. The phenomenon can be obtained by forming a layer of oxide having larger enthalpy of formation than the silicon oxide on the silicon oxide layer and performing thermal processing thereon. The alumina layer is a preferred embodiment, but the embodiment is not restricted to the alumina layer.

(32) (Growth of Group-III Nitride Single Crystal)

(33) Group-III nitride single crystal is grown by the metal-organic chemical vapor deposition (MOCVD) method on a surface of the alumina crystal in which the c-axis is inclined with respect to the surface. In the embodiment, the crystal growth of AlN, and then the crystal growth of GaN are promoted.

(34) First, the substrate is heated to 1000 to 1100° C. in a hydrogen or nitrogen atmosphere and the growth of AlN is started. It is preferred that, at the time of starting the crystal growth of AlN, the crystal growth starts at a temperature 100° C. lower than the thermal processing temperature of alumina. When the crystal growth starts at a temperature 100° C. lower than the thermal processing temperature of alumina, nitriding of the substrate can be prevented. Then, the crystal growth of AlN is promoted using ammonia as a nitrogen source and using trimethyl aluminum as an aluminum source. The c-axis of AlN crystal grown in this manner is oriented with respect to the alumina crystal. Consequently, the AlN crystal is oriented with respect to <111> axis of the silicon single crystal having 3-fold symmetry. Since <111> axis of the silicon single crystal is inclined with respect to the substrate surface (is not orthogonal thereto), the c-axis of the AlN crystal also grows so as to be inclined with respect to the substrate surface. Consequently, as shown in FIG. 3, step-flow growth of AlN crystal 8 occurs. FIG. 3 schematically shows the layered structure of a silicon single crystal substrate 2 having a miscut angle, a deoxidized silicon oxide layer 4, a thermally processed and crystallized alumina layer 6, and an AlN layer 8 grown thereon by step-flow growth.

(35) Moreover, the AlN layer 8 may also be grown by performing the MOCVD method at a temperature range of 400 to 800° C. Alternatively, the AlN layer 8 may be crystallized by thermal processing after an amorphous AlN layer has been formed by the ALD method.

(36) Other group-III nitride single crystal may be epitaxially grown on a surface of the AlN layer 8. In the embodiment of FIG. 3, a GaN layer 10 is epitaxially grown. A heterojunction interface is formed between the AlN layer 8 and the GaN layer 10. The c-axis 10a of the GaN layer 10 is inclined with respect to a surface of the GaN layer 10. Consequently, step-flow growth of the GaN crystal 10 occurs, as shown in FIG. 3.

(37) In FIG. 3, the height of the steps 12 and the inclination angle of the terraces 14 are shown in an exaggerated manner. The actual height of the steps 12 is from one to a few atomic layers, and the inclination angle of the terraces 14 is extremely small. That is, the surface of the GaN layer 10 has an extremely high degree of flatness. The crystal growth of e.g., a thin layer of Al.sub.xGa.sub.yIn.sub.1-x-yN is possible on the surface of the flat GaN layer 10. An extremely flat heterojunction interface can be obtained between the GaN layer and the layer of Al.sub.xGa.sub.yIn.sub.1-x-yN. It is possible to design the composition of mixed crystal so that an Al.sub.xGa.sub.yIn.sub.1-x-yN conduction band has higher energy than a GaN conduction band. Thus, an electron cloud can be generated at the heterojunction interface of the GaN layer and the Al.sub.xGa.sub.yIn.sub.1-x-yN. The heterojunction interface is extremely flat, and the mobility of elections is high. A semiconductor device can be realized in which highly concentrated electrons having high mobility along an extremely flat heterojunction interface are present (the semiconductor device consequently having a high performance).

(38) FIG. 1 shows a <0001> axis of GaN single crystal. FIG. 2 (a) shows a diagram of a cross-sectional view of a plane including the normal line n and a <11-2> axis of the silicon single crystal (ny-plane). <111>ny, in which the <111> axis is projected onto the ny-plane from the x axis direction, and <0001>ny, in which <0001> axis is projected onto the ny-plane from the x axis direction, are rotated in a clockwise direction from the normal line n, and are θx0≠0 and θx1≠0 as shown in the figure. <111> axis of the silicon and <0001> of the GaN are inclined to the same side (the same direction).

(39) FIG. 5 shows the relationship between θx0 and θx1 shown in FIG. 2 (a). As described above, since θy0 and θy1 of FIG. 2 (b) are both approximately zero, θx0 is near to θ0, and θx1 is near to θ1. FIG. 5 may be said to show the relationship between θ0 and θ1. As shown in FIG. 5, according to the present embodiment, θ0 and θ1 correlate well. A relationship is established in which θ1/θ0 is approximately 0.6 to 0.7. The slope of a straight line indicating the relationship of θ0 and θ1 varies according to the crystal growth conditions of the GaN layer. By adjusting the growth conditions, the value of θ1/θ0 can be adjusted within the range of 0.6 to 1.0.

(40) Further, as shown in FIG. 2 (c), in a plan view of the surface of the silicon single crystal substrate 2 or the GaN layer 10, an angle θ formed by the <111> axis of the silicon single crystal and the <0001> axis of the group-III nitride single crystal is approximately zero. A layered substrate can be obtained in which the orientation of the <111> axis of the silicon single crystal and the orientation of the <0001> axis of the group-III nitride single crystal are well matched.

(41) FIG. 6 is an AFM image of a surface of a GaN single crystal. The repeated terrace-step shape schematically shown in FIG. 3 is actually observed. If θx0 is approximately equal to θ0, and the absolute value thereof is in the angular range of 0.1 to 1.0°, when the average value of the width of the terrace (the width of the terrace measured in a direction orthogonal to the step) is W, and the lattice constant of the <0001> axis of the GaN single crystal is C, a relationship can be obtained in which absolute value of (W×tan θx1)=0.5×C to 20.0×C. In this case, each step is grown by step-flow growth at a thickness of 2 atomic layers or less. A GaN single crystal having a flat surface and few crystal defects can be obtained. While promoting the growth of the GaN single crystal layer 10, the crystal growth of GaN single crystal doped with impurities may be obtained. In the case of step-flow growth at a thickness of 2 atomic layers or less, it is possible to control whether to introduce impurities to a group-III site or to a group-V site. It is possible to create a substrate in which not only the concentration of impurities, but also the behavior of impurities is stable.

(42) FIG. 7 shows the relationship between thickness of the GaN single crystal layer 10 and XRC (x-ray rocking curve) full width at half maximum. Using samples in which AlN was grown at 1.060° C. and the crystal growth of GaN was obtained thereon, an x-ray rocking curve with 002 diffraction was measured. The full width at half maximum of a sample having a GaN layer thickness of 0.5 μm was 952 arcsec, the full width at half maximum of a sample having a layer thickness of 0.8 μm was 670 arcsec, and the full width at half maximum of a sample having a layer thickness of 1.5 μm was 449 to 514 arcsec.

(43) Single crystal GaN could be obtained which had a layer thickness of 1.5 μm or less and had a full width at half maximum of 450 to 500 arcsec (2.2 to 2.4×10.sup.−3 rad). The XRC full width at half maximum can be converted to the total value ρs of screw dislocation density and mixed dislocation density. Non-Patent Document 8 reports the relationship of Equation 1 below being satisfied.
ρs=Γ.sup.2/4.35b.sup.2  [Equation 1]

(44) Γ=Full Width at Half Maximum (rad)

(45) b=Length of Burgers Vector

(46) When converting the fall width at half maximum obtained with the sample having a film thickness of 1.5 μm into dislocation density using Equation 1, the dislocation density became 5×10.sup.8 cm.sup.−2 or less. The converted dislocation density was confirmed as valid from an AFM image. In case of growing AlN directly on a silicon substrate, and growing GaN thereon, dislocation density was 5×10.sup.8 cm.sup.−2 or more when measured in the same manner as above. According to the technique disclosed in the present specification, single crystal GaN could be obtained which had a layer thickness of 1.5 μm or less and in which dislocation density was 5×10.sup.8 cm.sup.−2 or less.

(47) According to the embodiment, it is possible to obtain a substrate in which the high quality group-III nitride single crystal layers 8, 10 having a small dislocation density are stacked on the silicon single crystal substrate 2. Various semiconductor device utilizing a group-III nitride single crystal can be manufactured by executing the processes, on this substrate, of etching gate recess, forming a gate insulating layer, forming a gate electrode, forming a source electrode and drain electrode, forming a sintered electrode, forming element isolation, and forming an interlayer dielectric, etc.

(48) If the purpose is to obtain the high quality group-III nitride single crystal layer 10 with small dislocation density, it is not essential to set the silicon single crystal substrate at a miscut angle. The present technique can be utilized to obtain the high quality group-III nitride single crystal layer 10 with small dislocation density on the surface of a silicon single crystal substrate having no miscut angle.

(49) In the present embodiment, as shown in FIG. 3, the GaN layer 10 is stacked above the AlN layer 8. Instead, by sequentially stacking, above the AlN layer 8, a strain relaxation layer made from AlGaN, a channel layer made from GaN, a barrier layer made from AlxInyGa1−x−yN, and a cap layer made from GaN, it is possible to create a heterojunction field-effect transistor structure. The GaN layer used as the channel layer is flat and has few crystal defects, allowing a transistor having excellent characteristics to be obtained. Alternatively, an AlGaN layer, an n-type cladding layer, a multiple quantum well active layer, a p-type electron barrier layer, and a p-type contact layer may be stacked above the AlN layer 8. The n-type cladding layer, multiple quantum well active layer, p-type electron barrier layer, p-type contact layer, etc. can be obtained by group-III nitride single crystal. According to this structure, it is possible to manufacture a light emitting diode in which the AlGaN layer functions as a strain relaxation layer. In this light emitting diode, a single crystal containing In is grown by step-flow growth, and consequently segregation of In is suppressed, improving luminous efficiency.

(50) FIG. 10 schematically shows an apparatus for growing a high quality group-III nitride single crystal layer with small dislocation density on a silicon single crystal substrate.

(51) In (1) to (3) of FIG. 10, reference number 42 indicates a chamber for forming, on a silicon single crystal substrate whose surface is covered by a silicon oxide layer, a layer of oxide having larger enthalpy of formation than silicon oxide. Reference number 52 of FIG. 10 (1) indicates a chamber for performing the thermal processing of the silicon single crystal substrate on which the layer of oxide has been formed, and further forming a group-III nitride single crystal layer. Reference number 58 of (2) and (3) of FIG. 10 indicates a chamber for performing the thermal processing of the silicon single crystal substrate, and reference number 66 indicates a chamber for foliating the group-III nitride single crystal layer. The chamber for performing the thermal processing of the silicon single crystal substrate, and the chamber for forming the group-III nitride single crystal layer may be identical, or may be provided separately. The chambers 42, 52, 58, 66 each have a vacuum pump I′ attached thereto, allowing the gas type, pressure, gas flow rate, etc. within the chambers to be adjusted.

(52) The chambers are connected to one another by transfer passages 48, 62, 72, etc. The transfer passages 48, 62, 72, etc. are also shut off from the outside air, allowing processing in which samples are not exposed to the outside air during processing. Reference numbers 46, 50, 56, 60, 64, 70, etc. are shutters for opening and closing between the chambers and the transfer passages. Reference number 42a is an opening for putting the silicon single crystal substrate on which the native oxide layer is being formed into the chamber 42, and reference number 44 is a shutter for opening and closing the opening 42a. Reference number 52a is an opening for taking out, from the chamber 52, the layered substrate on which the group-III nitride single crystal layer has been formed on the silicon single crystal substrate, and reference number 54 is a shutter for opening and closing the opening 52a. Reference number 66a is an opening for taking out, from the chamber 66, the layered substrate on which the group-III nitride single crystal layer has been formed on the silicon single crystal substrate, and reference number 68 is a shutter for opening and closing the opening 66a.

(53) According to the manufacturing apparatus of FIGS. 10 (1) to (3), a layered substrate in which a group-III nitride single crystal layer is formed on a silicon single crystal substrate can be manufactured in a state of samples not being exposed to outside air.

(54) Specific examples of the present invention have been described in detail, however, these are mere exemplary indications and thus do not limit the scope of the claims. The art described in the claims includes modifications and variations of the specific examples presented above. Technical features described in the description and the drawings may technically be useful alone or in various combinations, and are not limited to the combinations as originally claimed. Further, the art described in the description and the drawings may concurrently achieve a plurality of aims, and technical significance thereof resides in achieving any one of such aims.

REFERENCE SIGNS LIST

(55) 2: Silicon Single Crystal Substrate 2a: <111> axis 4: Silicon Oxide Layer 6: Alumina Layer 6a: c-Axis 8: AlN Layer 8a: c-Axis 10: GaN Layer 10a: c-Axis 12: Step 14: Terrace