Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device includes a fuse pattern disposed over a semiconductor substrate, an epoxy mold compound (EMC) layer disposed over the fuse pattern, a first package substrate disposed over the EMC layer, an insulating film disposed over the first package substrate, and a second package substrate disposed over the insulating film. To the first package substrate, a Vss voltage or a negative voltage lower than the Vss voltage is applied to prevent impurities from migrating to the fuse pattern.

Claims

1. A semiconductor device, comprising: a fuse pattern disposed over a semiconductor substrate and configured to receive a first voltage; an epoxy mold compound (EMC) layer disposed over the fuse pattern; a first package substrate disposed over the EMC layer and configured to receive a second voltage; an insulating film disposed over a surface of the first package substrate; and a second package substrate disposed over a surface of the insulating film and configured to receive a third voltage, wherein the second voltage is lower than the first voltage and the third voltage, and wherein the insulating film directly contacts the first package substrate and the second package substrate, and the EMC layer comprises impurities including bismuth ions (Bi.sup.+3), wherein impurities in the EMC layer migrate towards the first package substrate when the first, second and third voltages are applied.

2. The semiconductor device according to claim 1, wherein the first package substrate and the second package substrate each include copper.

3. The semiconductor device according to claim 1, wherein the fuse pattern includes copper.

4. The semiconductor device according to claim 1, wherein the fuse pattern is coupled to a metal contact, the metal contact penetrating an interlayer insulating film formed over the semiconductor substrate and coupled to the semiconductor substrate.

5. The semiconductor device of claim 1, wherein the first package substrate is a conductive layer.

6. The semiconductor device of claim 1, wherein the first voltage is equal to the third voltage.

7. The semiconductor device of claim 1, wherein the second voltage prevents impurities from migrating towards the fuse pattern.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above and other aspects, features and other advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

(2) FIG. 1 illustrates a cross-sectional view of a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

(3) Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of exemplary embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments of the present invention should not be construed as being limited to the particular shapes of regions illustrated herein, but may include deviations in shapes that result, for example, from manufacturing. In the drawings, lengths and sizes of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements.

(4) FIG. 1 illustrates a cross-sectional view of a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention.

(5) Referring to FIG. 1, the semiconductor device according to an embodiment of the present invention is described as follows.

(6) The semiconductor device includes an interlayer insulating film 210 disposed over a semiconductor substrate 200, a metal contact 220 disposed in the interlayer insulating film 210, a fuse pattern 230 coupled to the metal contact 220 and disposed over the interlayer insulating film 210, an epoxy mold compound (EMC) layer 240 disposed over the fuse pattern 230 and the interlayer insulating film 210, a first package substrate 250 disposed over the EMC layer 240, and an insulating film 260 and a second package substrate 270 disposed over the first package substrate 250.

(7) The fuse pattern 230 shown in FIG. 1 is a pattern that results after a fuse cutting process is performed. The fuse pattern 230 may be formed of a metal material, for example, copper. The first package substrate 250 and the second package substrate 270 may be formed of a metal material, including, for example, copper. The insulating film 260 prevents an electric short between the first package substrate 250 and the second package substrate 270.

(8) A Vss voltage or a negative voltage lower than the Vss voltage is applied to the first package substrate 250 so as to prevent metal ions generated in the second package substrate 270 from moving towards the EMC layer 240. Thus, the amount of metal ions in the EMC layer 240 can be reduced. Moreover, impurities that may be present in the EMC layer 240 move towards the first package substrate 250 so that the impurities in the EMC layer may be further reduced. As a result, migration of impurities to the fuse pattern 230 can be reduced. The impurities 280 may include bismuth ions (Bi+3).

(9) Referring to FIG. 1, a method for manufacturing a semiconductor device according to an embodiment of the present invention is described as follows.

(10) The interlayer insulating film 210 is formed over the semiconductor substrate 200 including lower structures. After the interlayer insulating film 210 is etched to form a contact hole, a metal material is buried in the contact hole to obtain a metal contact 220. The fuse pattern 230 is formed over the interlayer insulating film 210 so as to be coupled to the metal contact 220. The fuse pattern 230 is formed of a metal material, for example, copper. A fuse pattern 230 (shown in FIG. 1) is configured to be cut, for example, by a blowing process.

(11) A package process is performed to form an EMC layer 240 over the overall upper portion including the fuse pattern 230 and the interlayer insulating film 210. The semiconductor package process is performed to protect the semiconductor chip from the outside, facilitate electric connection with external terminals and electric apparatus, and secure the reliability of the semiconductor chip.

(12) The first package substrate 250 is formed over the EMC layer 240. The insulating film 260 is formed over the first package substrate 250, and the second package substrate 270 is formed over the insulating film 260. The first package substrate 250 and the second package substrate 270 may be formed of a metal material, for example, copper. The insulating film 260 prevents an electric short between the first package substrate 250 and the second package substrate 270.

(13) A Vss voltage or a negative voltage lower than the Vss voltage is applied to the first package substrate 250, which prevents movement of metal ions or impurities towards the EMC layer 240 from the second package substrate 270. Thus, the metal ions present in the EMC layer 240 are reduced. Reducing the amount of metal ions or impurities present in the EMC layer 240 provides an effect of preventing migration of the metal ions or impurities to fuse pattern 230, for example, after the fuse is cut or blown. A Vdd voltage is applied to the second package substrate 270, the Vss voltage is lower than the Vdd voltage. A voltage that is applied the fuse pattern 230 is equal to the voltage that is applied the second package substrate 270.

(14) Moreover, the impurities 280, which may for example, be generated from the package process, are moved towards the first package substrate 250 (along the B direction) to prevent the impurities 280 that remain in the EMC layer 240 from migrating to the fuse pattern 230. The impurities 280 may include bismuth ions (Bi.sup.+3).

(15) The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the embodiments described herein. Nor is the invention limited to any specific type of semiconductor device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.