PIECEWISE LINEAR GAIN AMPLIFIER

Abstract

A piecewise linear gain amplifier circuit includes a differential preamplifier and a plurality of transconductors. The differential preamplifier is electrically coupled to a differential input having an input voltage. The transconductors are electrically coupled in parallel with each other. Each transconductor includes a respective differential input that is electrically coupled to a differential output of the differential preamplifier. In addition, each transconductor includes a respective differential output that is electrically coupled to a common differential PWL output. Each transconductor has a different linear input range. An optional attenuation circuit can be electrically coupled in parallel to the differential preamplifier. The differential output of the attenuation circuit can be electrically coupled to a differential input of another transconductor, and that transconductor can have a differential output that is electrically coupled to the common differential PWL output.

Claims

1. A piecewise linear (PWL) gain amplifier circuit comprising: a differential preamplifier electrically coupled to a differential input, the differential input having an input voltage across the differential input; an attenuation circuit electrically coupled to the differential input, the attenuation circuit in parallel electrically with the differential preamplifier; and a plurality of transconductors, each transconductor having a respective differential output that is electrically coupled to a common differential PWL output, wherein the plurality of transconductors comprises: a first transconductor having a differential input that is electrically coupled to a differential output of the differential preamplifier, the first transconductor having a first linear input range; a second transconductor having a differential input that is electrically coupled to the differential output of the differential preamplifier, the second transconductor having a second linear input range, the first and second transconductors in parallel electrically with each other; and a third transconductor having a differential input that is electrically coupled to a differential output of the attenuation circuit, the third transconductor having a third linear input range, wherein: the first linear input range is less than the second linear input range, and. the second linear input range is less than the third linear input range.

2. The PWL gain amplifier circuit of claim 1, wherein each transconductor comprises a differential transconductor.

3. The PWL gain amplifier circuit of claim 2, wherein each differential transconductor comprises: a first transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal of the first transistor electrically coupled to a first line of the differential output of the differential preamplifier; a first degeneration resistor electrically coupled to the source terminal of the first transistor; a second transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal of the second transistor electrically coupled to a second line of the differential output of the differential preamplifier; and a second degeneration resistor electrically coupled to the source terminal of the second transistor.

4. The PWL gain amplifier circuit of claim 3, wherein the first and second transistors of each differential transconductor comprise NMOS transistors.

5. The PWL gain amplifier circuit of claim 3, wherein for each differential transconductor: the drain terminal of the first transistor is electrically coupled to a first line of the respective differential output of a respective transconductor, and the drain terminal of the second transistor is electrically coupled to a second line of the respective differential output of the respective transconductor.

6. The PWL gain amplifier circuit of claim 5, wherein: a first load resistor is electrically coupled to a first line of the common differential PWL output, and a second load resistor is electrically coupled to a second line of the common differential PWL output.

7. The PWL gain amplifier circuit of claim 6, wherein the first and second lines of the common differential PWL output are electrically coupled to first and second input terminals, respectively, of an operational amplifier, the operational amplifier and the first and second load resistors forming a transimpedance amplifier.

8. The PWL gain amplifier circuit of claim 7, wherein: the operational amplifier comprises first and second output terminals; a first feedback line is electrically coupled to the first input terminal, the first output terminal, and the first load resistor; and a second feedback line electrically is coupled to the second input terminal, the second output terminal, and the second load resistor.

9. The PWL gain amplifier circuit of claim 1, wherein the differential preamplifier comprises: a first preamplifier transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal of the first preamplifier transistor electrically coupled to a first line of the differential input; a first preamplifier degeneration resistor electrically coupled to the source terminal of the first preamplifier transistor; a second preamplifier transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal of the second preamplifier transistor electrically coupled to a second line of the differential input; a second preamplifier degeneration resistor electrically coupled to the source terminal of the second preamplifier transistor; a first preamplifier load resistor electrically coupled to the drain terminal of the first preamplifier transistor; and a second preamplifier load resistor electrically coupled to the drain terminal of the second preamplifier transistor.

10. The PWL gain amplifier circuit of claim 9, wherein the first and second preamplifier transistors comprise NMOS transistors.

11. The PWL gain amplifier circuit of claim 9, wherein each differential transconductor comprises: a first transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal of the first transistor electrically coupled to a first line of the differential output of the differential preamplifier; a first degeneration resistor electrically coupled to the source terminal of the first transistor; a second transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal of the second transistor electrically coupled to a second line of the differential output of the differential preamplifier; and a second degeneration resistor electrically coupled to the source terminal of the second transistor.

12. The PWL gain amplifier circuit of claim 11, wherein: a first transconductor bias current flows through the first or second degeneration resistor of the first differential transconductor, the first and second degeneration resistors of the first differential transconductor having a first degeneration resistance, a second transconductor bias current flows through the first or second degeneration resistor of the second differential transconductor, the first and second degeneration resistors of the second differential transconductor having a second degeneration resistance, and a preamplifier bias current flows through the first or second preamplifier degeneration resistor, the first and second degeneration resistors of the differential preamplifier having a preamplifier degeneration resistance.

13. The PWL gain amplifier circuit of claim 12, wherein the preamplifier bias current (I.sub.PRE), the first transconductor bias current (I.sub.B1), the second transconductor bias current (I.sub.B2), the preamplifier degeneration resistance (R.sub.PRE), the first degeneration resistance (R.sub.S1), and the second degeneration resistance (R.sub.S2), have the following relationship: $I_{B1}\times R_{S1}<I_{B2}\times R_{S2}<\frac{I_{PRE}\times R_{PRE}}{G_{PRE}}$ where G.sub.PRE is a gain of the differential preamplifier.

14. The PWL gain amplifier circuit of claim 12, wherein: a first load resistor is electrically coupled to a first line of the common differential PWL output, a second load resistor is electrically coupled to a second line of the common differential PWL output, the first and second load resistors have a load resistance (R.sub.TIA), a first transition voltage (V.sub.OX) corresponds to an outer limit of the first linear input range of the first transconductor, a second transition voltage (V.sub.OY) corresponds to an outer limit of the second linear input range of the second transconductor, and the first transition voltage (V.sub.OX), the second transition voltage (V.sub.OY), the first transconductor bias current (I.sub.B1), the second transconductor bias current (I.sub.B2), and the load resistance (R.sub.TIA) have the following relationship:
|V.sub.OX|=2I.sub.B1×R.sub.TIA, and
|V.sub.OY|=2I.sub.B2×R.sub.TIA.

15. The PWL gain amplifier circuit of claim 12, wherein: the first and second transconductor bias currents (I.sub.B1, I.sub.B2) are proportional to 1/R.sub.TIA, such that the first and second transition voltages (V.sub.OX, V.sub.OY) are substantially constant over a variation in a semiconductor manufacturing process, a temperature of the PWL gain amplifier circuit, and/or a supply voltage at the common differential PWL output.

16. The PWL gain amplifier circuit of claim 1, wherein: when an absolute value of the input voltage is less than a first transition voltage, the differential preamplifier and each transconductor contribute to a voltage gain of the input voltage, and the first transition voltage corresponds to an outer limit of the first linear input range of the first transconductor.

17. The PWL gain amplifier circuit of claim 16, wherein: when the absolute value of the input voltage is between the first transition voltage and a second transition voltage, only the differential preamplifier and the second and third transconductors contribute to the voltage gain of the input voltage, the second transition voltage is higher than the first transition voltage, and the second transition voltage corresponds to an outer limit of the second linear input range of the second transconductor.

18. The PWL gain amplifier circuit of claim 17, wherein: when the absolute value of the input voltage is greater than the second transition voltage, only the differential preamplifier and the third transconductor contribute to the voltage gain of the input voltage.

19. A piecewise linear (PWL) gain amplifier circuit comprising: a differential preamplifier electrically coupled to a differential input, the differential input having an input voltage across the differential input; and a plurality of transconductors electrically coupled in parallel with each other, each transconductor having: a respective differential input that is electrically coupled to a differential output of the differential preamplifier, and a respective differential output that is electrically coupled to a common differential PWL output, wherein each transconductor has a different linear input range.

20. The PWL gain amplifier circuit of claim 19, wherein: the plurality of transconductors comprises a first transconductor having a first linear output range and a second transconductor having a second linear output range, and the first linear input range is less than the second linear output range.

21. The PWL gain amplifier circuit of claim 19, wherein: the plurality of transconductors further comprises a third transconductor having a third linear output range, and the second linear output range is less than the third linear output range.

22. The PWL gain amplifier circuit of claim 19, wherein each transconductor comprises a differential transconductor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] For a fuller understanding of the nature and advantages of the concepts disclosed herein, reference is made to the detailed description of preferred embodiments and the accompanying drawings.

[0017] FIG. 1 is an example graph of a simplified 3-segment voltage transfer function of a PWL gain amplifier according to an embodiment.

[0018] FIG. 2 is a circuit diagram of a PWL gain amplifier circuit according to an embodiment.

[0019] FIG. 3 is a circuit diagram of a PWL gain amplifier circuit according to an embodiment.

[0020] FIG. 4 is an enlarged view of the differential preamplifier illustrated in FIG. 3.

[0021] FIG. 5 is an enlarged view of an example differential-pair transconductor illustrated in FIG. 3.

[0022] FIG. 6 is a graph of the linear input range of a transconductor according to an embodiment

[0023] FIG. 7 is a circuit diagram of a PWL gain amplifier circuit according to an alternative embodiment.

[0024] FIG. 8 is a circuit diagram of a PWL gain amplifier circuit according to an alternative embodiment.

[0025] FIG. 9 is an example graph of a simplified 3-segment voltage transfer function that can be produced with the PWL gain amplifier circuit illustrated in FIG. 8.

DETAILED DESCRIPTION

[0026] A piecewise linear (PWL) gain amplifier includes a differential preamplifier and a plurality of transconductors. Each transconductor has a respective linear input range (LIR). The differential preamplifier (PREAMP) has a differential input having an input voltage V.sub.in across the differential input. The differential output of the PREAMP is electrically coupled to the transconductors, which are electrically coupled in parallel with each other. The LIR of the first transconductor is less than that of the second transconductor; the LIR of the second transconductor is less than that of the third transconductor, and so on.

[0027] A first transition voltage corresponds to the outer limit of the LIR of the first transconductor. A second transition voltage corresponds to the outer limit of the LIR of the second transconductor. When the absolute value of the input voltage is below the first transition voltage (e.g., between the first transition voltage and 0 V), the PREAMP and each transductor contribute to the voltage gain of the input voltage V.sub.in. When the absolute value of the input voltage is between the first transition voltage and the second transition voltage, only the PREAMP, the second transconductor, and the third transconductor contribute to the voltage gain of the input voltage V.sub.in. When the absolute value of the input voltage is higher than the second transition voltage, only the PREAMP and the third transductor contribute to the voltage gain of the input voltage V.sub.in.

[0028] An optional attenuation circuit can be electrically coupled in parallel with the PREAMP. The attenuation circuit has a differential input having an input voltage V.sub.in across the differential input. The differential output of the attenuation circuit is electrically coupled to another transconductor (e.g., a fourth transconductor) that has a higher LIR than the transconductors that are electrically coupled to the PREAMP. The optional attenuation circuit and transconductor can increase the dynamic range of the PWL gain amplifier.

[0029] FIG. 1 is an example graph 10 of a simplified 3-segment voltage transfer function of a PWL gain amplifier according to an embodiment. The graph 10 illustrates three linear gain regions labeled as G.sub.X, G.sub.Y, and G.sub.Z. These regions (G.sub.X, G.sub.Y, and G.sub.Z) are the incremental voltage gains between |V.sub.in| and |V.sub.out| for the PWL amplifier where G.sub.X>G.sub.Y>G.sub.Z. When |V.sub.in|<V.sub.X, the amplifier exhibits a gain of G.sub.X, followed by a gain of G.sub.Y for V.sub.X<|V.sub.in|<V.sub.Y, and then a voltage gain of G.sub.Z for |V.sub.in|>V.sub.Y (where V.sub.X<V.sub.Y). V.sub.X and V.sub.Y are the first and second transition voltages, respectively, in graph 10.

[0030] FIG. 2 is a circuit diagram of a PWL gain amplifier circuit 20 according to an embodiment. The gain amplifier circuit 20 is configured to implement an N-segment PWL voltage transfer function have N linear gain regions. In some embodiments, the PWL gain amplifier circuit 20 can implement the 3-segment PWL linear voltage transfer function illustrated in graph 10. N can be a positive integer that is greater than or equal to 2 (e.g., 2, 3, 4, or another positive integer greater than or equal to 2).

[0031] The PWL gain amplifier circuit 20 includes a differential preamplifier A.sub.0, an attenuation circuit B.sub.0, and a plurality of transconductors G.sub.m1, G.sub.m1, . . . G.sub.mN (in general, transconductor G.sub.m). The differential preamplifier A.sub.0 and attenuation circuit B.sub.0 are electrically coupled in parallel to each other and have a respective differential input 200, 210 that has a differential input voltage V.sub.in (e.g., a positive input voltage V.sub.ip and a negative input voltage V.sub.in on each line of the respective differential input 200, 210).

[0032] Each transconductor G.sub.m has a differential input 220 and a differential output 225. The transconductors G.sub.m1, G.sub.m2, . . . G.sub.mN−1 are electrically coupled in parallel with each other. The differential inputs 220 of transconductors G.sub.m1, G.sub.m2, . . . G.sub.mN−1 are electrically coupled to a differential output 215 of the differential preamplifier A.sub.0. The differential input 220 of transconductor G.sub.mN is electrically coupled to a differential output 205 of the attenuation circuit B.sub.0. In addition, the differential input 220 of transconductor G.sub.mN is electrically isolated from the differential inputs 220 of the other transconductors (i.e., transconductors G.sub.m1, G.sub.m2, . . . G.sub.mN−1).

[0033] The differential outputs 225 of the transconductor G.sub.m are electrically coupled to each other at a common differential PWL output 230 having a differential output voltage V.sub.out. Each side 232, 234 of the common differential PWL output 230 is electrically coupled to a respective load resistor R.sub.TIA to amply the differential output voltage V.sub.out to a supply voltage V.sub.DD at supply line 240.

[0034] Each transconductor G.sub.m has an LIR over which the output current is a linear function (or approximately a linear function) of the differential input voltage at the differential input of the transconductor G.sub.m. G.sub.m1 has a first LIR, G.sub.m2 has a second LIR, G.sub.m3 has a third LIR, and so on. G.sub.mN−1 has an (N−1) LIR. The LIR of G.sub.m1<LIR of G.sub.m2<LIR of G.sub.m3< . . . <LIR of G.sub.mN−1. The attenuation circuit B.sub.0 decreases the magnitude of the input voltage V.sub.in, which contributes to G.sub.mN having the largest LIR, thus increasing the dynamic range of the PWL gain amplifier circuit 20. As such, each transconductor G.sub.m has a different LIR with G.sub.mN having the largest LIR.

[0035] The transductors G.sub.m can comprise differential pair transconductors or other transconductors. Each transconductor G.sub.m can be the same type or different type of transconductor than the other transductors G.sub.m.

[0036] In operation, when the absolute value of the input voltage is lower than a first transition voltage (e.g., between the first transition voltage and 0), the differential preamplifier A.sub.0 and each transductor G.sub.m contribute to the voltage gain of the input voltage V.sub.in. The first transition voltage corresponds to the outer limit of the LIR of G.sub.m1. When the absolute value of the input voltage is between the first transition voltage and a second transition voltage, the differential preamplifier A.sub.0 and all transductors G.sub.m except G.sub.m1 contribute to the voltage gain of the input voltage V.sub.in. Transconductor G.sub.m1 does not contribute to the voltage gain of the input voltage V.sub.in when the absolute value of the input voltage V.sub.in is greater than the first transition voltage because transconductor G.sub.m1 is saturated.

[0037] The second transition voltage corresponds to the outer limit of the LIR of G.sub.m2. When the absolute value of the input voltage is between the second transition voltage and a third transition voltage, the differential preamplifier A.sub.0 and all transductors G.sub.m except G.sub.m1 and G.sub.m2 contribute to the voltage gain of the input voltage V.sub.in. Transconductors G.sub.m1 and G.sub.m2 do not contribute to the voltage gain of the input voltage V.sub.in when the absolute value of the input voltage V.sub.in is greater than the second transition voltage because transconductors G.sub.m1 and G.sub.m2 are saturated.

[0038] In general, the M.sup.th transition voltage corresponds to the outer limit of the LIR of G.sub.mM. M is a positive integer that is greater than or equal to 1 and less than or equal to N. When the absolute value of the input voltage is between the (M−1).sup.th transition voltage and the M.sup.th transition voltage, the differential preamplifier A.sub.0 and all transductors G.sub.m except transductor(s) G.sub.m1 . . . G.sub.mM contribute to the voltage gain of the input voltage V.sub.in. In other words, the differential preamplifier A.sub.0 and transconductors G.sub.mM+1 . . . G.sub.mN contribute to the voltage gain of the input voltage V.sub.in when the absolute value of the input voltage is between the (M−1).sup.th transition voltage and the M.sup.th transition voltage. Transconductors G.sub.m1 . . . G.sub.mM do not contribute to the voltage gain of the input voltage V.sub.in when the absolute value of the input voltage is between the (M−1).sup.th transition voltage and the M.sup.th transition voltage.

[0039] When the absolute value of the input voltage is greater than the (N−1).sup.th transition voltage, only the differential preamplifier A.sub.0 and transductor G.sub.mN contribute to the voltage gain of the input voltage V.sub.in. Transconductors G.sub.m1 . . . G.sub.mN−1 do not contribute to the voltage gain of the input voltage V.sub.in when the absolute value of the input voltage is between the (M−1).sup.th transition voltage and the M.sup.th transition voltage.

[0040] FIG. 3 is a circuit diagram of a PWL gain amplifier circuit 30 according to an embodiment. PLW amplifier circuit 30 includes a differential preamplifier 300, an attenuation circuit 310 and three differential-pair transconductors D1, D2, and D3. PWL gain amplifier circuit 30 can be the same as PWL gain amplifier circuit 20 when PWL gain amplifier circuit 20 includes three transductors G.sub.m (i.e., transconductors G.sub.m1, G.sub.m2, and G.sub.m3, where N=3).

[0041] The differential preamplifier 300 includes first and second preamplifier transistors M.sub.PRE,P, M.sub.PRE,N. The preamplifier transistors M.sub.PRE,P, M.sub.PRE,N are illustrated as NMOS transistors. In other embodiments, both M.sub.PRE,P, M.sub.PRE,N can be PMOS transistors. In a preferred embodiment, the preamplifier transistors M.sub.PRE,P, M.sub.PRE,N are the same type of transistor (e.g., both NMOS or both PMOS). An enlarged view of differential preamplifier 300 is illustrated in FIG. 4. The gate terminal 302 of each preamplifier transistor MOP, MON is electrically coupled to a respective line of differential input 311. Specifically, a positive input line 312 is electrically coupled to the gate terminal 302 of preamplifier transistor M.sub.PRE,P, and a negative input line 314 is electrically coupled to the gate terminal 302 of preamplifier transistor M.sub.PRE,N. A respective degeneration resistor R.sub.PRE is electrically coupled to a source terminal 304 of each preamplifier transistor M.sub.PRE,P, M.sub.PRE,N. A respective preamplifier load resistor R.sub.L is electrically coupled to a drain terminal 306 of each preamplifier transistor M.sub.PRE,P, M.sub.PRE,N. The degeneration resistors R.sub.PRE preferably have the same resistance value. In addition, the preamplifier load resistors R.sub.L preferably have the same resistance value.

[0042] A bias current I.sub.PRE flows through each degeneration resistor R.sub.PRE and twice the bias current I.sub.PRE (i.e., 2I.sub.PRE) flows through the bias transistor 301 to ground. The bias transistor 301 can function as a bias current source. In another embodiment, the bias transistor 301 can be cascoded. The bias transistor 301 is preferably the same type of transistor (e.g., NMOS or PMOS) as the preamplifier transistors M.sub.PRE,P, M.sub.PRE,N. The differential preamplifier 300 has a differential output 305 represented as positive output line 308 and negative output line 309. The gain (G.sub.PRE) of the differential amplifier 300 is approximately equal (e.g., +/−10%) to R.sub.L/R.sub.PRE. Differential preamplifier 300 can be the same as or different than differential preamplifier A.sub.0.

[0043] Returning to FIG. 3, the attenuation circuit 310 includes a first resistor R.sub.A that is electrically coupled in series with a respective input line 312, 314 and a second resistor RB that is electrically coupled in parallel with first resistors R.sub.A. As such, the attenuation circuit 310 attenuates the input voltage V.sub.in by a factor of

[00002]$\frac{R_B}{R_B+R_A}.$

The attenuation circuit 310 can have other configurations, and thus provide other attenuation factors in other embodiments. The attenuation circuit 310 has a differential output 315 represented as positive output line 318 and negative output line 319. The attenuation circuit 310 can be the same as or different than attenuation circuit B.sub.0.

[0044] Each differential-pair transconductor D1, D2, and D3 (in general, differential-pair transconductor DN) includes first and second preamplifier transistors M.sub.P, M.sub.N and first and second degeneration resistors R.sub.S. For example, differential-pair transconductor D3 includes first and second differential-amplifier transistors M.sub.LP, M.sub.LN and first and second degeneration resistors R.sub.SL. The degeneration resistors R.sub.SL preferably have the same resistance value. Differential-pair transconductor D1 includes first and second differential-amplifier transistors M.sub.1P, M.sub.1N and first and second degeneration resistors R.sub.S1. The degeneration resistors R.sub.S1 preferably have the same resistance value. Differential-pair transconductor D2 includes first and second differential-amplifier transistors M.sub.2P, M.sub.2N and first and second degeneration resistors R.sub.S2. The degeneration resistors R.sub.S2 preferably have the same resistance value. The differential-pair transconductors D1, D2, and D3 can be the same as transconductors G.sub.m1, G.sub.m2, and G.sub.m3, respectively, when PWL gain amplifier circuit 20 includes only three transductors G.sub.m.

[0045] FIG. 5 is an enlarged view of an example differential-pair transconductor DN, which can correspond to differential-pair transconductor(s) D1, D2, and/or D3 in FIG. 3. Differential-pair transconductor DN includes differential-pair transistors M.sub.P, M.sub.N, and degeneration resistors R.sub.S.

[0046] The differential-pair transistor M.sub.P, M.sub.N are illustrated as NMOS transistors. In other embodiments, one or both differential-amplifier transistor(s) M.sub.P, M.sub.N can be PMOS transistors. In a preferred embodiment, differential-pair transistor(s) M.sub.P, M.sub.N are the same type of transistor (e.g., NMOS or PMOS). Each differential-pair transistor M.sub.P, M.sub.N includes a gate terminal 502, a source terminal 504, and a drain terminal 506. The gate terminal 502 of each differential-amplifier transistor M.sub.P, M.sub.N is electrically coupled to a respective input line. For D1 and D2, the gate terminals 502 are electrically coupled to the output lines 308, 309 (e.g., the differential output 305) of the differential preamplifier 300. For example, the gate terminal 502 of differential-pair transistor M.sub.P in D1 and D2 is electrically coupled to positive output line 308, which is electrically coupled to the drain terminal 306 of preamplifier transistor M.sub.PRE,P. In addition, the gate terminal 502 of differential-pair transistor M.sub.N in D1 and D2 is electrically coupled to negative output line 309, which is electrically coupled to the drain terminal 306 of preamplifier transistor M.sub.PRE,N. Thus, D1 and D2 each has a differential input that is electrically coupled to the differential output 305 of the differential preamplifier 300.

[0047] For D3, the gate terminals 502 are electrically coupled to the output lines 318, 319 (e.g., the differential output 315) of the attenuation circuit 310. For example, the gate terminal 502 of differential-pair transistor M.sub.P in D3 is electrically coupled to the positive output line 318 of attenuation circuit 310. In addition, the gate terminal 502 of differential-pair transistor M.sub.N in D3 is electrically coupled to the negative output line 319 of attenuation circuit 310. Thus, D3 has a differential input that is electrically coupled to the differential output 315 of the attenuation circuit 310.

[0048] A respective degeneration resistor R.sub.S is electrically coupled to the source terminal 504 of each differential-amplifier transistor M.sub.P, M.sub.N. Fora given differential-pair transconductor, the degeneration resistors R.sub.S preferably have the same resistance value. The degeneration resistors R.sub.S of different differential-pair transconductors can have the same or different values. A bias current I.sub.BN flows through each degeneration resistor R.sub.S and twice the bias current I.sub.BN (i.e., 2I.sub.BN) flows through the bias transistor 501 to ground. The bias transistor 501 can function as a current source. In another embodiment, the bias transistor 501 can be cascoded. The bias transistor 501 is preferably the same type of transistor (e.g., NMOS or PMOS) as the differential-pair transistors M.sub.P, M.sub.N.

[0049] The drain terminal 506 of each differential-amplifier transistor M.sub.P, M.sub.N is electrically coupled to a respective side of a differential output 510. For example, the drain terminal 506 of differential-amplifier transistor M.sub.P is electrically coupled to a common positive output line 512. In addition, the drain terminal 506 of differential-amplifier transistor M.sub.N is electrically coupled to a common negative output line 514. As illustrated in FIG. 3, each differential output 510 is electrically coupled to a common differential PWL output 520, which is electrically coupled to a differential PWL amplifier circuit output 530. The differential PWL amplifier circuit output 530 has a positive output voltage V.sub.op and a negative output voltage V.sub.om where the PWL output voltage V.sub.out=V.sub.op− V.sub.om. The common differential PWL output 520 can be the same as common differential PWL output 230. For example, the common differential PWL output 520 includes first and second sides 522, 524 (e.g., positive and negative sides, respectively) that can the same as the first and second sides 322, 324 (e.g., positive and negative sides, respectively) of common differential PWL output 230.

[0050] In some embodiments, the preamplifier transistors M.sub.PRE,P, M.sub.PRE,N and the differential-amplifier transistors M.sub.N, M.sub.P can be sized to have approximately equal current densities (e.g., within +/−1-5% of each other). The bias currents and degeneration resistor values can be chosen and/or configured such that the following relationship applies:

[00003]$I_{B1}\times R_{S1}<I_{B2}\times R_{S2}<\frac{I_{PRE}\times R_{PRE}}{G_{PRE}}$

[0051] In this configuration, the input voltage required to completely steer the entire respective bias currents towards one leg of the differential pair will be smallest for D1 followed by D2 and then the PREAMP. This can be represented mathematically by Equations (1) and (2).

|V.sub.in|>V.sub.X=2(I.sub.B1×R.sub.S1/G.sub.PRE).Math.I.sub.M.sub.1P=2I.sub.B1,I.sub.M.sub.1N=0(V.sub.in>V.sub.X)&I.sub.M.sub.1P=0,I.sub.M.sub.1N=2I.sub.B1(V.sub.in<−V.sub.X)  (1)

|V.sub.in|>V.sub.Y=2(I.sub.B2×R.sub.S2/G.sub.PRE).Math.I.sub.M.sub.2P=2I.sub.B2,I.sub.M.sub.2N=0(V.sub.in>V.sub.Y)& I.sub.M.sub.2P=0,I.sub.M.sub.2N=2I.sub.B2(V.sub.in<−V.sub.Y)  (2)

[0052] The corresponding output voltages when input voltage V.sub.in equals V.sub.X and V.sub.Y (depicted above) are represented by Equations (3) and (4).

|V.sub.OX|=2I.sub.B1×R.sub.TIA  (3)

|V.sub.OY|=2I.sub.B2×R.sub.TIA  (4)

[0053] In addition to the PREAMP, D1, and D2, FIG. 3 depicts another differential pair, D3, realized by NMOS transistors M.sub.LP and M.sub.LN. The input voltage to D3 is attenuated by

[00004]$\frac{R_B}{R_B+R_A},$

which together with the degeneration resistor R.sub.SL ensures that the voltage required to steer the entire bias current towards one leg of D3 is significantly larger than V.sub.Y (see Equation (2)). Essentially, this realizes a near-constant gain for the entire input voltage range of the PWL amplifier and is represented by Equation (5).

[00005]$\begin{array}{cc}{G}_Z\approx \frac{R_B}{\left(R_A+R_B\right)}\times \frac{R_{TIA}}{R_{SL}}& \left(5\right)\end{array}$

[0054] Using Equations (1)-(5), the PWL voltage transfer characteristics of graph 10 can now be described with respect to PWL gain amplifier circuit 30. When 0<|V.sub.in|<V.sub.X, the PREAMP, D1, D2, and D3 contribute to the total voltage gain, which can be characterized as

[00006]$G_X\approx \frac{R_L}{R_S}\times \left(G_{m1}+G_{m2}\right)\times R_{TIA}+G_Z,$

where G.sub.m1 and G.sub.m2 are the total effective transconductances realized by D1 and D2, respectively, when |V.sub.in|=V.sub.X. Next, when V.sub.X<|V.sub.in|<V.sub.Y, D1 is saturated and the PREAMP, D2, and D3 contribute to the total voltage gain, which can be characterized as

[00007]$G_Y\approx \frac{R_L}{R_S}\times G_{m2}\times R_{TIA}+G_Z.$

Finally, when |V.sub.in|>V.sub.Y, the voltage gain is equal to G.sub.Z as depicted in Equation (5). As such, the LIR of D1<LIR of D2<LIR of D3.

[0055] It is noted that by changing the values of the resistors and bias currents, the gains GX, GY, and GZ as well as the breakpoints of the voltage transfer characteristic (V.sub.X, V.sub.Y, V.sub.OX, V.sub.OY) (e.g., the values of V.sub.X, V.sub.Y, V.sub.OX, and/or V.sub.OY) can be programmed and/or configured. Especially, if the bias currents I.sub.B1 and I.sub.B2 are made inversely proportional to the load resistor R.sub.TIA, the output transition voltages V.sub.OX and V.sub.OY are substantially constant (e.g., within less than or equal to +/−1%) against variations in semiconductor manufacturing process, temperature (e.g., temperature of the PWL gain amplifier circuit 30), and/or supply voltage. For example, a semiconductor foundry manufactures integrated circuits at “typical” process conditions, in which case the NMOS and PMOS transistors (e.g., M) are manufactured with “typical” parameters (e.g., speed, etc.). The semiconductor foundry may shift (e.g., vary) the process overtime, which may result in relatively slower or relatively faster conditions.

[0056] Therefore, in operation, when the absolute value of the input voltage is lower than a first transition voltage V.sub.X (e.g., between 0 and V.sub.X), the differential preamplifier 300 and each differential-pair transductor D1-D3 contribute to the voltage gain of the input voltage V.sub.in. The first transition voltage corresponds to the outer limit of the LIR of differential-pair transductor D1. When the absolute value of the input voltage is between the first transition voltage V.sub.X and a second transition voltage V.sub.Y, the differential preamplifier A.sub.0 and differential-pair transductor D2 and attenuator together with D3 contribute to the voltage gain of the input voltage V.sub.in. Differential-pair transductor D1 does not contribute to the voltage gain of the input voltage V.sub.in when the input voltage V.sub.in is greater than the first transition voltage V.sub.X because differential-pair transductor D1 is saturated. The second transition voltage V.sub.Y corresponds to the outer limit of the LIR of differential-pair transductor D2.

[0057] When the absolute value of the input voltage is greater than the second transition voltage V.sub.Y, only the differential preamplifier 300 and the differential-pair transductor D3 contribute to the voltage gain of the input voltage V.sub.in. Differential-pair transductors D1 and D2 do not contribute to the voltage gain of the input voltage V.sub.in when the input voltage V.sub.in is greater than the second transition voltage V.sub.Y because differential-pair transductor D1 and D2 are saturated.

[0058] FIG. 6 is a graph 60 of the LIR of a transconductor according to an embodiment. The LIR extends from a negative input voltage −V.sub.LIR to a positive input voltage +V.sub.LIR. In the LIR, the output current I.sub.out varies linearly (or approximately linearly) with the input voltage V.sub.in. The linear relationship between the input voltage V.sub.in and output current I.sub.out is the gain 600 of the transconductor. When the absolute value of the input voltage V.sub.in is greater than V.sub.LIR, the transconductor is saturated and the gain is 0 (or approximately 0). Graph 60 can represent the LIR of any of the transconductors described herein including transconductors G.sub.m and differential-pair transconductors D1, D2, and D3, though the gain 600 of each transconductor may be different.

[0059] FIG. 7 is a circuit diagram of a PWL gain amplifier circuit 70 according to an alternative embodiment. PWL gain amplifier circuit 70 is the same as PWL amplifier gain circuit 20 except that in PWL gain amplifier circuit 70 the common differential PWL output 230 is electrically coupled to an operational amplifier (Opamp) and load resistors R.sub.TIA are wrapped around the Opamp in respective feedback circuits to form a transimpedance amplifier 700. For example, the Opamp includes first and second input terminals 702, 704 and first and second output terminals 712, 714. A first feedback line 710 is electrically coupled to the first input terminal 702, the first output terminal 712, and the first load resistor R.sub.TIA. A second feedback line 720 is electrically coupled to the second input terminal 704, the second output terminal 714, and the second load resistor R.sub.TIA.

[0060] FIG. 8 is a circuit diagram of a PWL gain amplifier circuit 80 according to an alternative embodiment. PWL gain amplifier circuit 80 is the same as PWL amplifier gain circuit 20 except that PWL gain amplifier circuit 80 does not include the attenuation circuit B.sub.0 and the corresponding transconductor G.sub.mN. Thus, PWL gain amplifier circuit 80 has one less transconductor G.sub.m (e.g., for a total of N−1 transconductors G.sub.m) compared to PWL gain amplifier circuit 80 (e.g., which has a total of N transconductors G.sub.m). Each transconductor G.sub.m has a different LIR. In some embodiments, the PWL gain amplifier circuit 80 can be configured such that the LIR of G.sub.m1<LIR of G.sub.m2 . . . <LIR of G.sub.mN.

[0061] In some embodiments, the output of the PWL gain amplifier circuit 80 can include a transimpedance amplifier that is the same as transimpedance amplifier 700 in PWL gain amplifier circuit 70.

[0062] FIG. 9 is an example graph 90 of a simplified 3-segment voltage transfer function that can be produced with PWL gain amplifier circuit 80 according to an embodiment. Graph 90 is the same as graph 10 except that region G.sub.Z has a gain of 0 (i.e., a slope of 1). Both graph 10, 90 illustrate the relationship G.sub.X>G.sub.Y>G.sub.Z. Graph 90 can be produced when the PWL gain amplifier circuit 80 includes 2 transconductor (i.e., N=2). Graph 90 can be modified to include additional linear gain regions when N>2.

[0063] The graph 90 illustrates three linear gain regions labeled as G.sub.X, G.sub.Y, and G.sub.Z. These regions (G.sub.X, G.sub.Y, and G.sub.Z) are the incremental voltage gains between |V.sub.in| and |V.sub.out| for the PWL amplifier where G.sub.X>G.sub.Y>G.sub.Z. When |V.sub.in|<V.sub.X, the amplifier exhibits a gain of G.sub.X, followed by a gain of G.sub.Y for V.sub.X<|V.sub.in|<V.sub.Y, and then a voltage gain of G.sub.Z for |V.sub.in|>V.sub.Y (where V.sub.X<V.sub.Y). V.sub.X and V.sub.Y are the first and second transition voltages, respectively, in graph 90.

[0064] The invention should not be considered limited to the particular embodiments described above, but rather should be understood to cover all aspects of the invention as fairly set out in the attached claims. Various modifications, equivalent processes, as well as numerous structures to which the invention may be applicable, will be apparent to those skilled in the art to which the invention is directed upon review of this disclosure. The claims are intended to cover such modifications and equivalents.

[0065] Also, some aspects may be embodied as one or more methods. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.