Circuit arrangement and method for controlling semiconductor switching element

Abstract

In order to reduce the problems with sharp-edged control voltages of semiconductor switching elements, it is provided that the control terminal (6) of the semiconductor switching element (1) is connected to the output terminal (7) of the semiconductor switching element (1) via a ramp generation unit (5), and the ramp generation unit (5) flattens the sharply ascending and descending edges of the driver control voltage (V.sub.S) into the form of a ramp, in order to generate a transistor control voltage (V.sub.G) at the output of the ramp generation unit (5).

Claims

1. A circuit arrangement for controlling a semiconductor switching element having a control terminal and an output terminal, the circuit arrangement comprising: a gate driver, which is configured to generate a sharp-edged driver control voltage (V.sub.S) having sharply ascending and descending edges for the semiconductor switching element and is connected to the control terminal of the semiconductor switching element; a ramp generation unit, which is arranged to connect the control terminal of the semiconductor switching element to the output terminal of the semiconductor switching element and to generate a transistor control voltage (V.sub.G) at an output of the ramp generation unit, in which the sharply ascending and descending edges of the driver control voltage (V.sub.S) are flattened into a ramp form; the gate driver being configured to supply power to the ramp generation unit; and a transistor arranged at an output side of the ramp generation unit, the transistor being controlled by a voltage (V.sub.R) that ascends or descends in the form of a ramp, whereby a transistor current (I.sub.1) descending or ascending in a ramp form flows via the transistor.

2. The circuit arrangement according to claim 1, further comprising a signal transformer connected between the gate driver and the ramp generation unit.

3. A circuit arrangement for controlling a semiconductor switching element having a control terminal and an output terminal, the circuit arrangement comprising: a gate driver, which is configured to generate a sharp-edged driver control voltage (V.sub.S) having sharply ascending and descending edges for the semiconductor switching element and is connected to the control terminal of the semiconductor switching element; a ramp generation unit, which is arranged to connect the control terminal of the semiconductor switching element to the output terminal of the semiconductor switching element and to generate a transistor control voltage (V.sub.G) at an output of the ramp generation unit, in which the sharply ascending and descending edges of the driver control voltage (V.sub.S) are flattened into a ramp form; and the gate driver being configured to supply power to the ramp generation unit, wherein the ramp generation unit further comprises a first transistor and an RC charging circuit comprising a resistor and a capacitor, and wherein an output terminal of the first transistor is connected to an output terminal of the ramp generation unit, the RC charging circuit is connected to an input terminal of the ramp generation unit via the resistor, and the capacitor of the RC charging circuit is connected to the transistor control terminal of the first transistor.

4. A circuit arrangement for controlling a semiconductor switching element having a control terminal and an output terminal, the circuit arrangement comprising: a gate driver, which is configured to generate a sharp-edged driver control voltage (V.sub.S) having sharply ascending and descending edges for the semiconductor switching element and is connected to the control terminal of the semiconductor switching element; a ramp generation unit, which is arranged to connect the control terminal of the semiconductor switching element to the output terminal of the semiconductor switching element and to generate a transistor control voltage (V.sub.G) at an output of the ramp generation unit, in which the sharply ascending and descending edges of the driver control voltage (V.sub.S) are flattened into a ramp form; and the gate driver being configured to supply power to the ramp generation unit, wherein the ramp generation unit further comprises a first transistor, a second transistor, and an RC charging circuit comprising a resistor and a capacitor, and wherein respective output terminals of the first transistor and of the second transistor are connected to one another and to an output terminal of the ramp generation unit; the transistor control terminal of the second transistor is connected to the input terminal of the ramp generation unit; the RC charging circuit is connected to the input terminal of the ramp generation unit via the resistor; and the capacitor of the RC charging circuit is connected to the transistor control terminal of the first transistor and of the second transistor.

5. A method for controlling a semiconductor switching element comprising: generating, via a gate driver, a sharp-edged driver control voltage (V.sub.S) to a control terminal of the semiconductor switching element; supplying, from the gate driver, power and an input current (I.sub.2) to the ramp generation unit; generating a ramp-shaped output current (I.sub.G) of the ramp generation unit by branching a ramp-shaped current (I.sub.1) off from the input current (I.sub.2) in the ramp generation unit; supplying the ramp-shaped output current (I.sub.G) into the control terminal of the semiconductor switching element, which results in a transistor control voltage (V.sub.G) having edges that ascend and descend in a ramp form; applying the driver control voltage (V.sub.S) in the ramp generation unit to an RC charging circuit; and applying a voltage (V.sub.R), which is applied to a capacitor of the RC charging circuit, to a transistor control terminal of a transistor to control the transistor, so that the ramp-shaped current (I.sub.1) flows via the transistor.

6. The method according to claim 5, further comprising: applying the voltage (V.sub.R) at the capacitor of the RC charging circuit to respective transistor control terminals of two series connected transistors, wherein the transistors are connected to one another and to the control terminal of the semiconductor switching element via the respective transistor output terminals thereof.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention shall now be described in greater detail, with reference to FIGS. 1 to 14, which, by way of example, illustrate advantageous embodiments of the invention in a schematic and non-restrictive manner.

(2) FIG. 1 illustrates a circuit arrangement for controlling a semiconductor switching element according to the invention;

(3) FIG. 2 illustrates an embodiment of the ramp generation unit according to the invention;

(4) FIG. 3 illustrates an alternative embodiment of the ramp generation unit according to the invention;

(5) FIG. 4 illustrates a simplified representation of a ramp generation unit according to the invention;

(6) FIGS. 5 to 8 illustrate curves of the characteristic currents and voltages of the ramp generation unit;

(7) FIG. 9 illustrates another embodiment of the ramp generation unit according to the invention; and

(8) FIGS. 10 to 14 illustrate curves of characteristic currents and voltages of this ramp generation unit.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(9) The particulars shown herein are by way of example and for purposes of illustrative discussion of the embodiments of the present invention only and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of the present invention. In this regard, no attempt is made to show structural details of the present invention in more detail than is necessary for the fundamental understanding of the present invention, the description taken with the drawings making apparent to those skilled in the art how the several forms of the present invention may be embodied in practice.

(10) As is schematically depicted in FIG. 1, a semiconductor switching element 1 is used, for example, as an electronic switch in an electrical circuit 2, for example, a DC-DC converter, as indicated in FIG. 1. In particular, such semiconductor switching elements 1 are found in power electronics, for example, in DC/AC converters, AC/DC converters, or DC/DC converters for various uses, e.g., in a charging device in the kW range, a welding device, or a power inverter of a photovoltaic system. Such power electronics circuits share the fact that the semiconductor switching element 1 must be switched at a high frequency. A standard gate driver 3 is used in order to switch the semiconductor switching element 1; at the output, under the control of a control unit 4, the standard gate driver 3 generates a sharp-edged driver control voltage V.sub.S of a certain frequency in order to control the semiconductor switching element 1. The driver control voltage V.sub.S is applied to the control terminal 6 of the semiconductor switching element 1, in order to control the current flow via the semiconductor switching element 1 in accordance with the predetermined switching behavior of the semiconductor switching element 1. On the input side, the gate driver 3 is controlled by a control unit 4, for example, by means of pulse width modulation (PWM). Such power electronics circuits 2 are well known so there is no need to provide a more detailed description here.

(11) A ramp generation unit 5 according to the invention is connected between a control terminal 6 and an output terminal 7 (e.g., an emitter terminal in the case of an IGBT or a source terminal in the case of a MOSFET) of the semiconductor switching element 1; the ramp generation unit 5 ensures that the voltage rise of the square edges of the sharp-edged driver control voltage V.sub.S from the standard gate driver 3 is reduced. The output terminal 7 is typically at a reference potential, such as a zero potential. A transistor control voltage V.sub.G that has defined ascending and descending ramps is intended to be generated thereby, in contrast to the sharp edges of the driver control voltage V.sub.S. The electrical power for operating the ramp generation unit 5 comes directly from the gate driver 3, so that there is no need to provide any additional supply voltage input for the ramp generation unit 5. The ramp generation unit 5 is an electrical additional circuit which, despite posing a burden on the gate driver 3 in terms of performance (because the gate driver 3 provides the electrical energy for the ramp generation unit 5), also ensures that a standard gate driver 3 can be used and that only the disadvantages associated with the sharp-edged driver control voltage V.sub.S are eliminated. Possible implementations of the ramp generation unit 5 shall be described below, with reference to FIGS. 2 and 3.

(12) The basic idea of the ramp generation unit 5 lies in applying the driver control voltage V.sub.S delivered from the gate driver 3 to the input side of the ramp generation unit 5 and arranging the transistor T1 at the output side of the ramp generation unit 5, wherein the transistor T1 is controlled either by a voltage ascending in the form of a ramp (at an ascending edge of the driver control voltage V.sub.S) or a voltage descending in the form of a ramp (at a descending edge of the driver control voltage V.sub.S), so that a transistor current I.sub.1 that descends or ascends in the form of a ramp flows through the transistor T1. Since the transistor T1 is connected to the output 11 of the ramp generation unit 5, the waveform of the transistor current I.sub.1 predetermines the waveform of the output current I.sub.G of the ramp generation unit 5, and hence also the waveform of the transistor control voltage V.sub.G, with which the semiconductor switching element 1 is controlled. A transistor current I.sub.1 ascending or descending in the form of a ramp thus brings about an output current I.sub.G that ascends or descends in the form of a ramp, and consequently also a transistor control voltage V.sub.G that ascends or descends in the form of a ramp.

(13) In the embodiment according to FIG. 2, a signal transformer 10 having potential isolation is provided for signal transmission between the gate driver 3 and the ramp generation unit 5, while in the embodiment according to FIG. 3, no potential isolation is provided and the gate driver 3 is connected directly to the ramp generation unit 5. In both cases, the ramp generation unit 5 is supplied with electrical power exclusively by the gate driver 3. A gate resistor R.sub.G and also an inductor L (e.g., a known multilayer ferrite for filtering EMV interference) may be provided before the control terminal 6 of the semiconductor switching element 1 in a known manner. In the following description, applicable protective circuitry in the ramp generation unit 5, such as diodes and resistors, shall be discussed only where it is relevant to the function of the ramp generation unit 5 according to the invention. Otherwise, it may be assumed that a person skilled in the art will recognize the function of the protective circuitry.

(14) The ramp generation unit 5 comprises input terminals 12 and output terminals 11. One of the input terminals 12 and one of the output terminals 11 are connected to one another and to a reference potential, such as a zero potential, in a known manner, for which reason the following discussion shall pertain also to an input terminal 12 and an output terminal 11. The output of the gate driver 3 or the output of the signal transformer 10 is connected to the input terminal 12. In the ramp generation unit 5 in the illustrated embodiments according to FIGS. 2 and 3, an input terminal 12 is connected to an output terminal 11 via a line 8 in which a current-limiting resistor R3 and optionally a diode D3 are arranged. In the ramp generation unit 5, a transistor T1, which here is a PNP bipolar transistor, is connected in parallel to the output terminal 11 of the ramp generation unit 5. The transistor T1 is thus connected between the line 8 and the reference potential, and therefore branches off from the line 8. Instead of a PNP bipolar transistor, it shall be readily understood that it would also be possible to use another transistor type for the transistor T1.

(15) In FIG. 2, the transistor T1 is embodied as a known Darlington pair circuit by means of two transistors, also known as a Darlington transistor; however, this has no special significance for the invention. The Darlington transistor of FIG. 2 is also generally referred to here as the transistor T1.

(16) The transistor T1 here is connected to the transistor output terminal E, for example, an emitter terminal, and the transistor input terminal C, for example, a collector terminal, (at the output-side transistor of the Darlington pair circuit, in the case of a Darlington transistor), between the output terminals 11 of the ramp generation unit 5. The transistor output terminal E of the transistor T1 is then connected to the control terminal 6 of the semiconductor switching element 1, optionally via the gate resistor R.sub.G and the inductor L.

(17) An RC charging circuit 13 composed of a capacitor C1 and resistors R1, R2 is connected to the transistor control terminal B, for example, a base terminal, of the transistor T1 (at the input-side transistor of the Darlington circuit pair, in the case of a Darlington transistor). The resistors R1, R2 are switched on via the diodes D1, D2 respectively connected in series to a resistor R1, R2, in accordance with the current direction. The capacitor C1 of the RC charging circuit 13 is connected between the transistor control terminal B and the transistor input terminal C of the transistor T1 (at the input-side transistor, in the case of a Darlington transistor). The RC charging circuit 13 is also connected to the input of the ramp generation unit 5, by the connection of the resistors R1, R2 to the input terminal 12.

(18) The function of the ramp generation unit 5 shall now be described with reference to FIG. 4, which illustrates the ramp generation unit 5 in a simplified manner, and FIGS. 5 to 8, which illustrate characteristic signal patterns.

(19) The sharp-edged driver control voltage V.sub.S of the gate driver 3 is applied to the input terminal 12 of the ramp generation unit 5 (FIG. 5), and an input current I.sub.2 flows into the ramp generation unit 5 from the gate driver 3. Thus, the driver control voltage V.sub.S is also applied to the RC charging circuit 13, which is connected to the input terminal 12, whereby the capacitor C1 thereof is charged (voltage V.sub.R) until the voltage levels are matched (FIG. 5). The ascending voltage V.sub.R via the capacitor C1, which is applied to the transistor control terminal B of the transistor T1, controls the PNP-type transistor T1, resulting in a current I.sub.1 that descends in the form of a ramp via the transistor T1 (FIG. 6). The transistor current I.sub.1 via the transistor T1 branches off from the output terminal 11 of the ramp generation unit 5, which causes the difference from the input current I.sub.1 and the transistor current I.sub.1 to result in the output current I.sub.G of the ramp generation unit 5, i.e., I.sub.G=I.sub.2−I.sub.1. The current via the RC charging circuit 13 is disregarded here. Thus, a transistor control voltage V.sub.G having a flat ascending edge in the form of a ramp is applied to the control terminal 6 at the semiconductor switching element 1 through the output current I.sub.G, which descends in the form of a ramp, and (where applicable) at the gate resistor R.sub.G. The sharply ascending edge of the driver control voltage V.sub.S has thus been flattened to the form of a ramp by the ramp generation unit 5. Appropriate dimensioning of the RC charging circuit 13 makes it possible to precisely tune this effect.

(20) The ramp generation unit 5 thus seeks to generate a strictly monotonically ascending transistor control voltage V.sub.G. The current peaks or dips in the current patterns of the transistor current I.sub.1 (FIG. 6) and of the output current I.sub.G (FIG. 7) are a consequence of the well-known Miller effect in the semiconductor switching element 1. Also, the Miller effect brings about a temporary flattening of the ascending and descending edges of the transistor control voltage V.sub.G (FIG. 8).

(21) Analogously, the sharply descending edges of the driver control voltage V.sub.S of the gate driver 3 are flattened by the ramp generation unit 5, as depicted also in FIGS. 5 to 8. The descending transistor current I.sub.1 is then again branched off from the output stream I.sub.G, resulting in flattening of the descending edges of the transistor control voltage V.sub.G into the form of a ramp.

(22) FIG. 9 illustrates a modification of the ramp generation unit 5 according to the invention. Here, the transistor T1 is still connected by the transistor output terminal E to the output 11 of the ramp generation unit 5. The input terminal 12, however, is no longer directly connected to the line 8 here to the output terminal 11, optionally via a resistor R3 and diode D3. A second transistor T2 having a polarity inverse to that of the transistor T1 (the second transistor T2 here being of the NPN-type), is connected to the transistor output terminal E of the first transistor T1, and the transistor input terminal C2 of the second transistor T2 is connected to the line 8. The transistor control terminal B2 of the second transistor T2 is connected to the transistor control terminal B of the first transistor T1, whereby the RC charging circuit 13 with the voltage V.sub.R is applied also at the transistor control terminal B2 of the second transistor T2.

(23) The effect of this circuit is identical to that of the above-described embodiment of the ramp generation unit 5 according to FIG. 2 or 3, and the voltage edges of the driver control voltage V.sub.S are again flattened in the form of a ramp, as depicted in particular in FIGS. 10 to 14.

(24) The only difference is that now the ascending ramp-shaped edge of the transistor control voltage V.sub.G is generated by the second transistor T2, and the descending ramp-shaped edge of the transistor control voltage V.sub.G is generated by the first transistor T1.

(25) The advantage of this circuit according to FIG. 9 is that the standard gate driver 3 of this circuit is less burdened because for the ascending edge, as the output current I.sub.G is equal to the input current I.sub.2, which also corresponds to the current via the second transistor T2. This advantage does, however, come at the cost of an additional component in the form of the second transistor T2.

(26) It is noted that the foregoing examples have been provided merely for the purpose of explanation and are in no way to be construed as limiting of the present invention. While the present invention has been described with reference to an exemplary embodiment, it is understood that the words which have been used herein are words of description and illustration, rather than words of limitation. Changes may be made, within the purview of the appended claims, as presently stated and as amended, without departing from the scope and spirit of the present invention in its aspects. Although the present invention has been described herein with reference to particular means, materials and embodiments, the present invention is not intended to be limited to the particulars disclosed herein; rather, the present invention extends to all functionally equivalent structures, methods and uses, such as are within the scope of the appended claims.