EFFICIENCY MEASURING APPARATUS, ACTIVE EQUALIZER INDUCTOR DESIGN TOOL AND EQUALIZER DESIGN APP

Abstract

An efficiency measuring apparatus that measures the efficiency of charge transfer between battery cell sections in an active EQU unit. The apparatus includes a pair of series connected battery cell sections, a first FET switch and a second FET switch. The apparatus further includes an inductor electrically coupled between the cell sections, to the drain terminal of the first FET switch and the source terminal of the second FET switch. The apparatus also includes a gate driver electrically coupled to the gate terminal of the first FET switch, and an oscillator providing a PWM signal to the gate driver, where the gate driver opens and closes the first FET switch to transfer charge from the one cell section to the other one cell section through the inductor.

Claims

1. An efficiency measuring apparatus that measures the efficiency of charge transfer between battery cells and groups of battery cells, said apparatus comprising: a pair of series connected battery cell sections; a first FET switch including a gate terminal, a drain terminal and a source terminal, wherein the source terminal of the first FET switch is electrically coupled to one of the cell sections; a second FET switch including a gate terminal, a drain terminal and a source terminal, wherein the source and gate terminals of the second FET switch are electrically coupled and the drain terminal of the second FET switch is electrically coupled to the other one of the cell sections; an inductor electrically coupled between the cell sections, to the drain terminal of the first FET switch and the source terminal of the second FET switch; a gate driver electrically coupled to the gate terminal of the first FET switch; and an oscillator providing a pulse width modulation (PWM) signal to the gate driver, wherein the gate driver opens and closes the first FET switch to transfer charge from the one cell section to the other one of the cell sections through the inductor.

2. The apparatus according to claim 1 wherein the source terminal of the first FET switch is electrically coupled to the drain terminal of the second FET switch by a line.

3. The apparatus according to claim 2 further comprising a snubber circuit coupled to the line, wherein the snubber circuit limits the drain terminal to source terminal voltage when the first FET switch is gated off.

4. The apparatus according to claim 3 wherein the snubber circuit includes a pair of capacitors electrically coupled in parallel.

5. The apparatus according to claim 4 wherein one of the capacitors is an electrolytic capacitor and the other capacitor is a ceramic capacitor.

6. The apparatus according to claim 1 further comprising an inverter, said inverter being responsive to the PWM signal form the oscillator, inverting the PWM signal and providing the inverted PWM signal to the gate driver.

7. The apparatus according to claim 1 further comprising an RC filter circuit electrically coupled in parallel with the other one of the cell sections.

8. The apparatus according to claim 1 wherein the first and second FET switches and the inductor make up an active battery cell equalization circuit.

9. The apparatus according to claim 1 wherein a type of the first and second FET switches and the gate driver are selected based on the voltage of the battery cell sections.

10. The apparatus according to claim 9 wherein the battery cell sections have a voltage of 24 volts or less.

11. The apparatus according to claim 9 wherein the battery cell sections have a voltage of 48 volts or less.

12. A method for selecting an inductor and a pair of FET switches for an active battery cell equalization circuit, said method comprising: determining inductor design specifications including an operating voltage, current and frequency of the equalization circuit; calculating an inductance of the inductor using the design specifications; calculating an inductor power of the inductor using the design specifications; selecting an inductor core design to be used in the inductor; calculating the number of turns for the windings of the selected core design using the calculated inductance; determining a level of saturation for the selected core design; determining inductor core losses for the selected core design; determining inductor winding losses for the selected core design; determining total inductor losses for the selected core design; and determining an efficiency for the selected core design.

13. The method according to claim 12 wherein selecting an inductor core design includes selecting an inductor core design from a group of available core designs.

14. The method according to claim 13 wherein calculating the number of turns of the windings, determining a level of saturation, determining core losses, determining winding losses, determining total inductor losses and determining an efficiency includes calculating the number of windings, determining a level of saturation, determining core losses, determining winding losses, determining total inductor losses and determining an efficiency for all of the core designs in the group.

15. The method according to claim 12 wherein selecting an inductor core design includes providing input parameters for a desired inductor core design.

16. The method according to claim 12 further comprising selecting a potential pair of FET switches for the equalization circuit, determining switching losses and conduction losses of the selected FET switches and determining an efficiency of the selected FET switches.

17. The method according to claim 16 wherein determining switching losses P.sub.SW includes using the equation:
P.sub.SW=0.5×V.sub.DS×I.sub.pk×(t.sub.SW(ON)+t.sub.SW(OFF))×f, where I.sub.PK is peak current, t.sub.SW(ON) is turn-on transition time, t.sub.SW(OFF) is turn-off transition time, f is the operating frequency and V.sub.DS is a peak voltage of the selected FET switch during the off state.

18. The method according to claim 16 wherein determining conduction losses P.sub.c1 includes using the equation:
P.sub.c1=lrms.sup.2×R.sub.DS(on)×D, where D is duty cycle, R.sub.DS(ON) is FET switch drain-to-source resistance and Irms is the rms current flowing through the gate terminal of the FET switch.

19. The method according to claim 12 further comprising determining an overall charge transfer efficiency of the equalization circuit.

20. A method for designing an active battery cell equalization circuit or a combined active battery cell equalization and passive battery cell equalization circuit to be used for equalizing voltage of cell sections in a battery, said method comprising: setting a number of the cell sections; setting a charge transfer efficiency variable for the equalization circuit; setting a diagonal matrix element for a matrix modeling the equalization circuit; setting a diagonal −1 matrix element for the matrix; setting a discharge capacity value for each cell section; setting a discharge current for the battery; setting a median voltage of the cell sections; calculating equalization circuit currents, battery discharge time, discharge capacity of the cell sections and percentage of rated discharge capacity of the cell sections; and calculating power loss, energy loss, energy discharge and discharge energy efficiency of the battery.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 is a schematic block diagram of a battery system including a number of battery sections each having a number of battery cells and including a BEQ;

[0010] FIG. 2 is a schematic diagram of a passive EQU unit employed in the BEQ shown in FIG. 1;

[0011] FIG. 3 is a schematic diagram of an active EQU unit employed in the BEQ shown in FIG. 1;

[0012] FIG. 4 is a schematic diagram of an efficiency measuring apparatus for low power batteries;

[0013] FIG. 5 is a schematic diagram of an efficiency measuring apparatus for high power batteries;

[0014] FIGS. 6A and 6B are a spreadsheet illustrating an example of using an inductor design tool for selecting an inductor for an active EQU unit;

[0015] FIG. 7 is a flow chart diagram showing a process for using the inductor design tool;

[0016] FIG. 8 is a graphical model showing current flow for charge transfer in an active EQU unit; and

[0017] FIG. 9 is a flow chart diagram showing a computer and software process for implementing an active EQU unit design app.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] The following discussion of the embodiments of the disclosure an efficiency measuring apparatus that measures the efficiency of charge transfer between battery cell sections is merely exemplary in nature, and is in no way intended to limit the disclosure or its applications or uses.

[0019] FIG. 1 is a schematic block diagram of a battery system 10 including five battery sections 12, 14, 16, 18 and 20 each having a certain number of battery cells 22. The battery system 10 also includes a BEQ 24 having a passive EQU unit 26 for each battery section 12-20, and a plurality of active EQU units 28, 30, 32 and 34, where the active EQU unit 28 is provided between the battery sections 12 and 14, the active EQU unit 30 is provided between the battery sections 14 and 16, the active EQU unit 32 is provided between the battery sections 16 and 18 and the active EQU unit 34 is provided between the battery sections 18 and 20. The BEQ 24 operates in a well known manner, such as described above.

[0020] FIG. 2 is a representative schematic diagram 40 of, for example, one of the passive EQU units 26 that includes an EQU circuit 42 for each cell 22 in the particular battery section 12-20. Each EQU circuit 42 includes a resistor 44 and an FET switch 46 electrically coupled in series. When the FET switch 46 is closed by a controller 48, the cell 22 is discharged through a discharge resistor 50 and the discharge voltage is measured by the controller 48.

[0021] FIG. 3 is a representative schematic diagram 60 of, for example, the active EQU units 28 and 30. The EQU unit 28 includes a pair of FET switches 62 and 64 and an inductor 66 and the EQU unit 30 includes a pair of FET switches 68 and 70 and an inductor 72. The FET switches 62, 64, 68 and 70 are closed and opened to charge and discharge the inductors 66 and 72 to transfer charge between the battery sections 12, 14 and 16 so that the sections 12, 14 and 16 have the same or similar SOC in a manner well understood by those skilled in the art.

[0022] FIG. 4 is a schematic diagram of an efficiency measuring apparatus 80 that measures the efficiency of charge transfer between battery cell sections 82 and 84 each including up to six cells or 24V. The apparatus 80 includes an active EQU circuit 86 having FET switches 88 and 90 and an inductor 92 that transfers charge between the battery cell sections 82 and 84, where the battery cell section 84 has the highest capacity and the battery cell section 82 has the lowest capacity. The FET switch 90 takes charge away from the high capacity battery cell section 84 and the body diode in the FET switch 88 charges the low capacity battery cell section 82. The FET switches 88 and 90 alternate being on and off.

[0023] The source terminal of the FET switch 88 is coupled to the drain terminal of the FET switch 90 and one side of the inductor 92, the drain terminal of the FET switch 88 is coupled to the positive side of the battery cell section 82, the source terminal of the FET switch 90 is coupled to the negative side of the battery cell section 84 through a parasitic inductor 96, and the negative side of the battery cell section 82 and the positive side of the battery cell section 84 are coupled to the other side of the inductor 92. A snubber circuit 98 including an electrolytic capacitor 100 and a ceramic capacitor 102 is coupled in parallel with a line 104 coupling the drain terminal of the FET switch 88 and the source terminal of the FET switch 90. An RC filter circuit 106 including an electrolytic capacitor 108 and a resistor 110 is coupled in parallel with the battery cell section 82. A fan circuit 112 for cooling the apparatus 80 includes a fan 114, a fan switch 116, a main switch 118 and a power source 120.

[0024] An oscillator 122 provides a pulse width modulation (PWM) signal to a gate driver 124 that provides a drive signal through a resistor 126 to the gate terminal of the FET switch 90 that closes the FET switch 90 when the PWM signal is high and opens the FET switch 90 when the PWM signal is low. When the FET switch 90 closes, current flows clockwise in the loop made up of the FET switch 90, the battery cell section 84 and the inductor 92, which stores charge in the inductor 92 from the battery cell section 84. When the FET switch 90 opens, the charge stored in the inductor 92 flows through the body diode of the FET switch 88, which causes current flow counter-clockwise in the loop made up of the inductor 92, the FET switch 88 and the battery cell section 82, which charges the battery cell section 82. When the FET switch 90 is gated off, the drain-to-source voltage of the FET switch 90 has a high transient overshoot, and thus the snubber circuit 98 limits the voltage increase. The voltages on the battery cell sections 82 and 84 can be measured during the charge transfer by an oscilloscope (not shown) to provide the charging efficiency.

[0025] FIG. 5 is a schematic diagram of another more robust efficiency measuring apparatus 130 that measures the efficiency of charge transfer between battery cell sections 132 and 134 that include up to twelve cells or 48V, where like elements to the apparatus 80 are identified by the same reference numbers. The apparatus 130 requires more robust FET switches 136 and 138 and a more robust gate driver 140 than the apparatus 80 because of the higher voltages. The more robust gate driver 140 has an inverted low input at pin 3, which requires the PWM signal from the oscillator 122 to be inverted by an inverter 142 before being sent to the gate driver 140.

[0026] The inductor 92 in the active EQU circuit 86 stores energy during cell equalization and is the main factor that determines the energy transfer efficiency from the battery cell section 84 to the battery cell section 82. The inductor 92 has winding losses due to the resistance of the coil and core losses because of hysteresis and eddy current mechanisms. If the inductor 92 generates too much loss, then the charge transfer efficiency decreases. Therefore, in order to maximize the charge transfer efficiency between the battery cell sections 84 and 82, the inductor 92 should be properly designed to maximize the charge transfer efficiency between the cell sections 84 and 82. In addition, various inductor designs should be compared prior to selecting the inductor 92. The following discussion describes an inductor design tool that can be used for this purpose particularly referencing the apparatus 80 with the understanding it equally applies to the apparatus 130.

[0027] FIGS. 6A and 6B are a spreadsheet illustrating an example of using the inductor design tool for selecting the inductor 92 for the active EQU circuit 86. At step 1, the designer enters the design specifications of the active EQU circuit 86 including the operating voltage V, the inductor peak current lpk and the frequency f, and the tool calculates the inductor power P and the required inductance L. At step 2, the tool provides available inductor core designs from which a desirable core design can be selected and using the inductance L calculates the number of winding turns N for each core design and/or a selected core design. At step 3, the tool provides the level of saturation for each core design and/or the selected core design. At step 4, the tool predicts the inductor core losses for each core design and/or the selected core design. At step 5, the tool predicts the winding losses, the total inductor losses and inductor efficiency for each core design and/or the selected core design. Once the user has decided which inductor to use in the active EQU circuit 86 using the tool, then that inductor is used as the inductor 92 in the efficiency measuring apparatus 80.

[0028] An FET switch design tool can also be employed to select the proper FET switches 88 and 90 to be used in the efficiency measuring apparatus 80. Specifically, conduction losses P.sub.C1 and switching losses P.sub.SW in the FET switches 88 and 90 are considered for providing an effective active EQU circuit 86. The conduction losses P.sub.C1 occur when an FET switch 88 or 90 is on and conducts current. The key parameter responsible for conduction losses P.sub.C1 is the resistance between the drain and source terminals of the FET switches 88 and 90. To accurately model the conduction losses P.sub.C1, it is necessary to understand the mode of operation of the active EQU circuit 86 on the apparatus 80. The active EQU circuit 86 operates in three phases that are dependent on the status of the FET switches 88 and 90. In phase 1, the drive signal from the gate driver 124 is high, and this turns the FET switch 90 on while the FET switch 88 is off. In phase 2, the drive signal from the gate driver 124 is low, and this turns the FET switch 90 off while the body diode of the FET switch 88 conducts. In phase 3, both of the FET switches 88 and 90 are off. There is no inductor current and no energy is transferred through the active EQU circuit 86. In phase 1, the conduction losses P.sub.C1 can be estimated by multiplying the duty cycle D, the average FET switch current Irms and the FET drain-to-source resistance R.sub.DS(ON) as specified on the datasheet as:

P.sub.c1=lrms.sup.2×R.sub.DS(on)×D,

where Irms is the rms current flowing through the gate terminal of the FET switch 88 or 90.

[0029] In phase 2, the body diode of the FET switch 88 is conducting and the conduction loss P.sub.C2 can be estimated as:

P.sub.c2=l.sub.2×V.sub.f×(1−D),

where D is the duty cycle, l.sub.2 is the current flowing from the inductor 92 to the FET switch 88 and V.sub.f is the diode forward voltage as specified on the datasheet.

[0030] The total conduction losses P.sub.c can be estimated by adding P.sub.c1 and P.sub.c2 as:

P.sub.c=P.sub.c1+P.sub.c2.

[0031] The switching losses P.sub.SW occur when the FET switches 88 and 90 transition between the on and off states. The switching losses P.sub.SW increase as the switching frequency increases because the transition period becomes a larger portion of the duty cycle D. The FET switch 88 has parasitic capacitances between the ground-to-source terminals CGS and the drain-to-source terminals CDS. When the FET switch 90 is turned off, the inductance L and the capacitance CDS of the FET switch 88 form a series LC resonant circuit that produces high frequency oscillations. When the FET switch 88 is turned on, the capacitance CGS must be charged first before the on state is reached. Thus, during turn on, the time to charge this capacitance is t.sub.SW(ON) and it can be found from the FET datasheet. Similarly, during turn off, the time to discharge the capacitance CGS is t.sub.SW(OFF). The switching losses P.sub.SW can be estimated by:

P.sub.SW=0.5×V.sub.DS×I.sub.pk×(t.sub.SW(ON)+t.sub.SW(OFF))×f,

where I.sub.PK is the peak current, t.sub.SW(ON) is the turn-on transition time, t.sub.SW(OFF) is the turn-off transition time, f is the operating frequency and V.sub.DS is the peak voltage of the FET switch 88 or 90 during the off state.

[0032] FIG. 7 is a flow chart diagram 150 showing a computer and software process for implementing the inductor and FET switch design tools described above. The process starts at oval 152 and the tool prompts the user to input the voltage, current and frequency at box 154. The tool outputs a list of available inductor core designs at box 156 and then prompts the user to determine whether the user wants to us an existing core design at decision diamond 158. If the user does want to use an existing core design at the decision diamond 158, then the tool prompts the user to select the core design at box 160. The tool then calculates and displays the inductor saturation, the DC saturation, inductor core loss, the inductor winding loss, the inductor total loss, the FET switch losses and the inductor efficiency at box 162, and the tool ends at box 164. If the user does not want to use existing core designs at the decision diamond 158, then the tool prompts the user to provide the input parameters for the desired inductor at box 166, which are displayed at box 168. The tool then calculates and displays the inductor saturation, the DC saturation, inductor core loss, the inductor winding loss, the inductor total loss, the FET switch losses and the inductor efficiency at box 170, and the tool ends at box 172.

[0033] Once the FET switches 88 and 90 and the inductor 92 are selected for the active EQU circuit 86, an active EQU design app can be employed to simulate the performance of the active EQU circuit 86 on the battery cell sections 82 and 84. The app can also predict the size of the equalization currents. This is crucial for understanding the design parameters of the active EQU circuit 86 needed to balance the battery cell sections 82 and 84. FIG. 8 is a graphical model 180 of current flow in the active EQU circuit 86 showing how much charge is transferred between the battery cell sections 82 and 84, represented as battery cell sections 182, 184, 186, 188 and 190, where Ah is discharge capacity, I is the equalization current and n is the charge transfer efficiency calculated by the apparatus. In this example, section 182 is the weakest section, and thus current flows from the section 190 to the section 182.

[0034] The discussion below explains the development of a mathematical model for a BEQ, where the mathematical model provides a basis for designing the BEQ and creating the Matlab code for the design. As stated earlier, the BEQ consists of passive EQU units and active EQU units. The passive EQU units equalize the cells in a section and the active EQU units transfer charge from section to section. During the charge cycle, both the passive EQU units and the active EQU units operate on the battery. The passive EQU unit does not add charge to the section, so it has no use during the discharge cycle. During the discharge cycle, the active EQU units alone balance the sections.

[0035] The battery contains M cells connected in series. The BEQ divides the battery into the cell sections 182-190 in the model 180, which corresponds to the battery sections 12, 14, 16, 18 and 20 in the battery system 10. Each section 182-190 will typically contain either 4, 6 or 12 cells. The battery will have N sections, where N is the number of sections for the BEQ as:

N=Total number of cells in the stack/Number of cells

[0036] The convention is that the capacity of a section 182-190 is the capacity of the weakest cell within that section. The system variables are Ahi=rated discharge capacity Ah of section i (2 to N), ampere-hours; Ahw=Ah1=discharge capacity of the weak section, ampere-hours; u=level of unbalance of the weak cell as a portion of the rated discharge capacity Ah, 0 to 0.99; Id=discharge current, amperes; Ipi=DC passive EQU unit current for all of the cells in section I, amperes; t=discharge time, hours; Ik=DC active EQU unit current flowing from one section to another section (k=N−1), amperes; and n=efficiency of each active EQU unit, 0 to 1.00.

[0037] During the discharge cycle, weak cells discharge faster than other cells, but the BEQ is designed so that the higher capacity sections will simultaneously transfer charge to the weak sections so that the entire battery, sections 182-190, will be fully discharged at the same time t. The mathematical model for the BEQ during the discharge cycle is shown in FIG. 8. This example is for the case where the active EQU unit current flows from right to left.

(Id+Ip1−n×I1)t=Ah1   Section 182

(Id+Ip2+I1−n×I2)t=Ah2   Section 184

(Id+Ip3+I2−n×I3)t=Ah3   Section 186

(Id+Ip4+I3−n×I4)t=Ah4   Section 188

(Id+Ip5+I4)t=Ah5   Section 190

[0038] Generalization for any number of sections N yields the mathematical model for the BEQ below:

For 1≤I≤N−1:

[0039]
(Id+Ipi+Ii−1−n×Ii)t=Ahi   Section i

For the last section i=N:

(Id+IpN+IN−1)t=AhN   Section N

[0040] As stated above, there is no passive EQU unit equalization during the discharge cycle, therefore:

Ip1=Ip2= . . . =IpN=0

[0041] The inverse time variable P is defined as:

P=1/t

[0042] Rearranging the equations above yields the mathematical model of the BEQ in matrix form as:

[00001]$\left[\begin{array}{ccccc}n& 0& 0& 0& \mathrm{Ah}1\\ -1& n& 0& 0& \mathrm{Ah}2\\ 0& -1& n& 0& \mathrm{Ah}3\\ 0& 0& -1& n& \mathrm{Ah}4\\ 0& 0& 0& -1& \mathrm{Ah}5\end{array}\right].Math.\left[\begin{array}{c}I1\\ I2\\ I3\\ I4\\ P\end{array}\right]=\left[\begin{array}{c}\mathrm{Id}\\ \mathrm{Id}\\ \mathrm{Id}\\ \mathrm{Id}\\ \mathrm{Id}\end{array}\right]$

[0043] The matrix form for a system with N battery sections is:

[00002]$\begin{array}{c}\mathrm{TO}\mathrm{section}\\ S1\\ S2\\ .Math.\\ \mathrm{SN}\end{array}=\left[\begin{array}{ccccc}n& 0& 0& 0& \mathrm{Ah}1\\ -1& & & & .\\ .& & & & .\\ 0& 0& -1& n& {\mathrm{Ah}}_{N-1}\\ 0& 0& 0& -1& \mathrm{AhN}\end{array}\right].Math.\left[\begin{array}{c}I1\\ .\\ .\\ I_{N-1}\\ P\end{array}\right]=\left[\begin{array}{c}\mathrm{Id}\\ \mathrm{Id}\\ \mathrm{Id}\\ \mathrm{Id}\\ \mathrm{Id}\end{array}\right]$$\begin{array}{cc}\begin{array}{c}\mathrm{FROM}\mathrm{current}\\ I1I2.Math.\mathrm{IN}-1\end{array}& \mathrm{AhN}\end{array}$

[0044] The current flows from the high capacity section to the low capacity section. The convention for the current direction Idr follows. [0045] For current leaving the section, Idir=−1. [0046] For current entering the section, Idir=+1.

[0047] FIG. 9 is a flow chart diagram 200 showing a computer and software process for implementing the active EQU design app (EDA) discussed above. The app starts at oval 202 and then prompts the user for the number of sections in the battery and displays that number at box 204. For example, how many sections are in the battery? Display 6.

[0048] The app then prompts the user for the EQU transfer efficiency variable n at box 206. For example, what is the efficiency? Enter a value from 0.0 to 1.0, for example, 0.7569.

[0049] The app then prompts the user for the diagonal matrix element and displays the matrix at box 208. The system has N sections.

[0050] The app then prompts the user for the diagonal −1 matrix element and displays the matrix at box 210. For example, ENTER 0 FOR THE LAST ENTRY In.

[0051] CONVENTION: Efficiency range is 0-0.99. [0052] Current direction Idir(n) is (+) for current I entering the section N and (−) for current I leaving the section N. [0053] Current flows from a high capacity section to a low capacity section. [0054] The entry should be of the form [Ef(1)*Idir(1) Ef(2)*Idir(2) . . . Ef(n−1)*Idirn(n−1) 0]. [0055] [0.7569 0.7569 0.7569 0.7569 0.7569 0] [0056] D= [0057] 0.7569 0 0 0 0 0 [0058] 0 0.7569 0 0 0 0 [0059] 0 0 0.7569 0 0 0 [0060] 0 0 0 0.7569 0 0 [0061] 0 0 0 0 0.7569 0 [0062] 0 0 0 0 0 0

[0063] The app then prompts the user for the current direction at the box 210 and displays the matrix, which are the diagonal −1 matrix elements. Current direction for each active EQU unit current. [0064] E.g contribution of active EQU unit current I into the section 184, I2 into the section 186 . . . I(n−1) into the section 190. [0065] Current direction is +1 for I leaving a section and −1 for I entering a section. [0066] The entry should be of the form of [Idir(1) Idir(2) . . . Idir(n−1)]. [0067] [−1 −1 −1 −1 −1] [0068] D2= [0069] 0.7569 0 0 0 0 0 [0070] −1.0000 0.7569 0 0 0 0 [0071] 0 −1.0000 0.7569 0 0 0 [0072] 0 0 −1.0000 0.7569 0 0 [0073] 0 0 0 −1.0000 0.7569 0 [0074] 0 0 0 0 −1.0000 0

[0075] The app then prompts the user for the discharge capacity Ah and displays the Ah values at box 212. LAST COLUMN VECTOR ENTRY [0076] Enter the capacity in amp-hour for each section from the section 182 to the section 190. [0077] The entry should be of the form of [AH1; AH2; . . . ; AHn]. [0078] [44.8;64;51.2;64;64;64] [0079] A= [0080] 0.7569 0 0 0 0 44.8000 [0081] −1.0000 0.7569 0 0 0 64.0000 [0082] 0 −1.0000 0.7569 0 0 51.2000 [0083] 0 0 −1.0000 0.7569 0 64.0000 [0084] 0 0 0 −1.0000 0.7569 64.0000 [0085] 0 0 0 0 −1.0000 64.0000

[0086] The app then prompts the user for the discharge current I.sub.d at box 214. What is the discharge current I.sub.d? 16

[0087] The app then displays the EQU currents I.sub.n, discharge time, discharge capacity Ah and percent of rated discharge capacity Ah at box 216. For example. [0088] 1: EQU current is 4.24 A [0089] 2: EQU current is 2.61 A [0090] 3: EQU current is 5.28 A [0091] 4: EQU current is 3.98 A [0092] 5: EQU current is 2.27 A [0093] The discharge time is 3.5035 hours. [0094] AH Discharge is 56.056 AH. [0095] Per Cent of Rated AH is 87.59.

[0096] The app then prompts the user for the medium voltage of the cell section at box 218, for example, what is the cell medium voltage? 14.4.

[0097] The app then displays the power loss, energy loss, energy discharge and discharge energy efficiency at box 220, and the app ends at oval 222.

[0098] As will be well understood by those skilled in the art, the several and various steps and processes discussed herein to describe the disclosure may be referring to operations performed by a computer, a processor or other electronic calculating device that manipulate and/or transform data using electrical phenomenon. Those computers and electronic devices may employ various volatile and/or non-volatile memories including non-transitory computer-readable medium with an executable program stored thereon including various code or executable instructions able to be performed by the computer or processor, where the memory and/or computer-readable medium may include all forms and types of memory and other computer-readable media.

[0099] The foregoing discussion discloses and describes merely exemplary embodiments of the present disclosure. One skilled in the art will readily recognize from such discussion and from the accompanying drawings and claims that various changes, modifications and variations can be made therein without departing from the spirit and scope of the disclosure as defined in the following claims.