Complementary current field-effect transistor devices and amplifiers

Abstract

The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

Claims

1. A method for processing analog signals using a complementary current-injection field effect transistor (CiFET) as a voltage gain structure for converting voltage-in to voltage-out, comprising: a. providing the CiFET that comprises a complimentary pair of source-to-drain paths, a common gate port, a common drain port and first and second diffusion ports (iPorts), wherein each of the first and second iPorts separates the corresponding one of the source-to-drain paths into two channels in series, wherein the common gate port is connected to a gate for each of the pair of source-to-drain paths, and each of the gates is capacitively coupled to the two channels of the corresponding one of the pair of source-to-drain paths, and the common drain port is connected to the drains of the pair of source-to-drain paths; b. applying an input voltage to the common gate port; c. utilizing the voltage at the common drain port as the CiFET output.

2. The method as recited in claim 1 further comprising the step of applying an input current to one or both of the first and second iPorts.

3. A method for processing analog signals using a current-injection field effect transistor (iFET) as a current gain structure for converting current-in to current-out, comprising: a. providing the iFET that comprises a source-to-drain path, a gate port, a drain port and a diffusion port (iPort), wherein the iPort separates the source-to-drain path into two channels in series, wherein the gate port is connected to a gate for the source-to-drain path, and the gate is capacitively coupled to the two channels of the source-to-drain path, and the drain port is connected to the drain of the source-to-drain path; b. applying an input current to the iPort; c. utilizing the current flow at the drain port as the iFET output.

4. A method for processing analog signals using a current-injection field effect transistor (iFET) as a trans-conductance gain structure for converting voltage-in to current-out, comprising: a. providing the iFET that comprises a source-to-drain path, a gate port, a drain port and a diffusion port (iPort), wherein the iPort separates the source-to-drain path into two channels in series, wherein the gate port is connected to a gate for the source-to-drain path, and the gate is capacitively coupled to the two channels of the source-to-drain path, and the drain port is connected to the drain of the source-to-drain path; b. applying an input voltage to the gate port; c. utilizing the current flow at the drain port as the iFET output.

5. A method for processing analog signals using a complementary current-injection field effect transistor (CiFET) as a trans-resistance gain structure for converting current-in to voltage-out, comprising: a. providing the CiFET that comprises a complimentary pair of source-to-drain paths, a common gate port, a common drain port and first and second diffusion ports (iPorts), wherein each of the first and second iPorts separates the corresponding one of the source-to-drain paths into two channels in series, wherein the common gate port is connected to a gate for each of the pair of source-to-drain paths, and each of the gates is capacitively coupled to the two channels of the corresponding one of the pair of source-to-drain paths, and the common drain port is connected to the drains of the pair of source-to-drain paths; b. applying an input current to one or both of the first and second iPorts; c. utilizing the voltage at the common drain port as the CiFET output.

Description

BRIEF DESCRIPTION OF FIGURES

(1) FIG. 1a illustrates a high quality CMOS OpAmp prior art transistor schematic from a prominent textbook “Analysis and Design of Analog Integrated Circuits,” 5.sup.th Ed, by Gray, Hurst Lewis and Meyer, p 484 as a prior art amplifier for comparison;

(2) FIGS. 1b to 1d are a baseline set of representative performance plots illustrating frequency domain performance and power supply dependency of the prior art OpAmp of FIG. 1a;

(3) FIGS. 1e and 1g show cross-sectional views of prior art MOSFET channel construction weak-inversion and strong-inversion, respectively, and FIGS. 1f and 1h show plots showing exponential relationship between drain current and drain voltage when weak-inversion and when strong-inversion, respectively;

(4) FIG. 1i shows schematic diagram of a prior art 2-finger invertor;

(5) FIGS. 1j and 1k show physical layout abstractions of the 2-finger inverters shown in FIG. 1i;

(6) FIG. 1L shows a three (3) dimensional perspective view of the 2-finger inverter of FIG. 1i;

(7) FIG. 1m shows cross-sectional view at Section AA shown in FIG. 1L;

(8) FIG. 1n shows a physical layout of a prior art split channel MOS transistor;

(9) FIG. 1o shows a three (3) dimensional perspective view of a prior art linear MOS field-effect transistor;

(10) FIG. 2a illustrates a three (3) dimensional prospective view of a MOS field-effect transistor (or iFET) with a new mid-channel bi-directional current port (iPort) of the present invention;

(11) FIG. 2b illustrates a cross-sectional view of iFET of the present invention with visualized channel charge distributions;

(12) FIG. 2c shows a graph of drain voltage V.sub.ds and drain current I.sub.d when there is no iPort injection current, while FIG. 2d shows another graph when max iPort injection current is provided;

(13) FIG. 2e illustrates how the new iPort current terminal replaces half of a differential pair in an iFET amplifier of the present invention;

(14) FIGS. 2f to 2L illustrate channel ionization and trans-impedance characterization of the iFET along with suggested schematic symbols;

(15) FIG. 2m illustrates a schematic diagram of a trans-impedance iFET amplifier of the present invention;

(16) FIG. 3a illustrates a schematic diagram of complimentary pair of iFETs of the present invention;

(17) FIGS. 3b and 3c illustrate a physical layout abstraction of the complementary iFET (or CiFET) compound device shown in FIG. 3a;

(18) FIG. 3d shows a three (3) dimensional perspective view of the CiFET compound device shown in FIG. 3a;

(19) FIG. 3e illustrates cross-sectional view at Section AA of FIG. 3d;

(20) FIGS. 3f and 3g illustrate a CiFET operational modeling and a suggested schematic symbol therefor;

(21) FIGS. 3h to 3k illustrate various CiFET compound device transfer characteristics and properties of the present invention; and

(22) FIG. 3L illustrates the availability of self-biased reference voltage terminals;

(23) FIG. 3m illustrates the wide range and linearity of the PTAT temperature measurement characteristics of the PTAT self-biased reference terminal of FIG. 3L;

(24) FIGS. 3n, 3o, 3p, 3q, 3r, 3s, 3t, 3u and 3v are representative performance plots of the CiFET compound device illustrations of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(25) A MOS structure referred to herein as an iFET, where the letter “i” refers to a current and “FET” refers to a Field Effect Transistor, is the enabling element of several high performance and novel designs of the present invention. The present invention is based on the addition of a direct connection to a mid-point in a Field Effect Transistor (or FET) channel and the realization that this is a low impedance port (current port, or herein referred to as “iPort”) having trans-impedance current input to voltage output gain properties realized by providing a bidirectional current sink/source mid-channel with a very low input impedance at a low saturation voltage, and additionally connecting reciprocal iFETs pairs of opposite “conductivity type” or polarity type (P-type & N-type) interconnected to take advantage of their complementary nature to operate as a team and with symmetry to self-bias near the midpoint between power supplies. In addition, the relative conductance of the first and second channels of the iFETs can be adjusted (threshold choice, relative sizing, and doping profiles) to tailor the gain, speed, quiescent current and input impedance of such an complementary iFET (or CiFET) compound device of the present invention.

(26) The iFET, with its iPort provides an uncommon and unexpected solution to the compensation problem, and then continues to provide new or alternative solutions to other old problems, exceeding industry expectations. The advantages of operating circuits in “weak-inversion” have long been known but, so also have the problems. The CiFET enables circuits to exploit the high gain and wider dynamic range available in “weak-inversion,” without sacrificing superior speed performance. The CiFET compound device provides a standard active IC gain device that is superior to ordinary analog MOSETs making digital ICs host analog functionality. It is not a tradeoff.

(27) The following is a list of some of the unusual aspects of a CiFET based circuit, including, but not limited to: Operates at low power supply voltage; High gain; Extremely linear; Very high speed (wide band); Self-Biasing; Low noise; Quick recovery (DC); Uses all digital parts and processes; iPorts respond to charge (things in nature are charge based) rather than Volts across a Resistance; and iPort has wide dynamic range with constant gain in an open loop.

(28) Referring to FIGS. 2a and 2b, according to a preferred embodiment of the present invention, an iFET 200, is shown which is comprised of substrate 26a or 26b, source terminal 24a or 24b, and drain terminal 29a or 29b, defining therebetween two channels 23a and 25a, or 23b and 25b on the substrate 26a or 26b, respectively. Typically the first (source channel 23a, or 23b) is connected to the power supply (not shown) while the second (drain channel 25a, or 25b) connects to the load (not shown in FIG. 2a). The substrate 26a or 26b is N- or P-type. The two channels, source and drain channels 23a and 25a, or 23b and 25b, respectively, are connected to each other as shown in FIGS. 2a, and 2b, at the iPort control terminal 21a or 21b, and the channels 23a and 25a, or 23b and 25b, share a common gate control terminal 27a or 27b, respectively. The source channel portion of the gate control terminal s27a/s27b is capacitively coupled to the source channel 23a/23b; while the drain channel portion of the gate control terminal d27a/d27b is capacitively coupled to the drain channel 25a/25b. This configuration means that the iFET 200 has more than one control input terminal.

(29) The gate control terminal 27a or 27b operates like a conventional MOSFET insulated gate, with its high input impedance and a characteristic trans-conductance (g.sub.m) transfer function. Typical values of (g.sub.m) for a small-signal MOSFET transistor are 1 to 30 millisiemens (1 millisiemen=1/1K-ohm) each, a measure of trans-conductance.

(30) The iPort control terminal 21a or 21b is low impedance with respect to the source terminal 24a or 24b, and has a transfer function that looks more like beta (β) of a bipolar transistor, but is actually trans-resistance (or r.sub.m), or more generally, especially at high frequencies, trans-impedance, measured in K-ohms, where the output voltage is a consequence of an input current. Typical resistance values (or values of r.sub.m) for a small-signal iFET transistor 200 are 50KΩ to 1MΩ, a measure of trans-resistance. Current input to voltage output (trans-impedance) is the basis for the assertion that 1 uA in will yield an output of 100 mV (or a gain of 100,000:1) at a large signal level, or 1 pA in will yield an output of 100 nanoV (or a gain of 100,000:1) in an LNA (both results from the same circuit).

(31) These values have been shown to remain true for a single minimum sized CiFET, with inputs from 1 pico-ampere to 10 micro-amperes, using the same circuit in simulation and limited device measurements. In 180 nm CMOS construction the noise floor limits measurements below about 10 pico amps. iFETS can be constructed with different length to width proportions with very predictably differing results.

(32) High gain, uncharacteristic or surprising results differing from the state of the art designs, is the result of the “weak-inversion” like exponential characteristics of the source channel 23b of the iFET 200 operating in a highly ionized super-saturation mode 28b.

(33) Speed in this super-saturated source channel 23b is not limited by the transit time of carriers along the source channel 23b, but the high concentration of ionized charge carriers in the active channel only have to push the surrounding charge a little as charge is either added or removed from the source channel 23b by means of the iPort control terminal 21b, resulting in a diffusion current which is defined by exponential relationship as has been realized when a MOSFET is operated in weak-inversion. This is in contrast to an electric field causing the charge to transit the channel, which is a square-law function of the gate control voltage. In this configuration, speed is faster than logic built from the same fundamental transistors and unhampered by the “weak-inversion” stage that has higher gains like bipolar transistors. As opposed to bipolar transistors, control current can go either in or out of the iPort control terminal 21b as well as operate with no iPort current, which is useful for creating a self-bias operating point.

(34) In a self-biased CiFET all of the channels are operated with a higher than normal gate to channel voltage and a lower than normal voltage gradient along the channel. This provides lower noise which is facilitated by the self-biasing approach. The potential at drain terminal 29a or 29b is the same as potential at the gate control terminal 27a or 27b, greatly reducing the pinch-off effect found in conventional analog circuit designs.

(35) The iFET 200, because of the common gate connection over the source channel 23a/23b and drain channel 25a/25b, a higher than conventionally applied voltage is placed on the source channel gate control terminal s27a/s27b (or SG) with respect to the source terminal 24a/24b and source channel 23a/23b when compared to the gate voltage 17e used for weak-inversion 13e of FIGS. 1e and 1f. This higher than expected voltage 22b FIG. 2b is responsible for a much thicker (lower resistance highly ionized) conduction layer 28b, allowing the mainstream of carriers to avoid the traps in the surface of the crystal lattice just under the gate s27b, hence—much lower noise similar to the manner in which a junction field effect transistor (or j-FET) conduction channel is located below the surface.

(36) Trans-resistance (r.sub.m) is the “dual” of trans-conductance (g.sub.m). When looking up trans-resistance, most of the references are to inductors and capacitors, suggesting that the iFET may be useful in synthesizing inductors. Thus ultra-pure sine-wave oscillators can be made from CiFET stages that do not use inductors.

(37) The iFET works in the following ways: A low noise amplifier requires a low impedance channel. A low impedance channel is low in voltage gain but high in current gain. To establish voltage gain, a second stage, operating as a current to voltage converter, is required. A cascoded pair (one on top of the other) of transistors provides such a configuration. Biasing requirements for a cascoded pair preclude its use at low voltage unless a convenient solution for the biasing problem is found. The CiFET device structure provides the solution to this problem through self-biasing of a complementary pair. The impedance of the source channel 23b can be designed to accommodate the impedance of the particular signal source driving it (see later section on ratio).

(38) Regarding FETs in general, carriers are attracted to the surface by the gate field, a low gate voltage creates a thin surface-layer on the channel (where the conductivity takes place) while a higher gate voltage creates a thicker under-layer. The thin layer of carriers is impeded by the non-uniform surface defects resulting in electrical noise, while a thicker layer of carriers finds a smoother path below the surface, thus reducing total electrical noise. This indicates that higher gate voltage translates to lower noise.

(39) Referring to FIG. 2b, in the iFET 200 the electric field created by the gate voltage Vg 22b on the gate control terminal 27b causes carriers to rise from the substrate 26b into the source channel 23b region converting the semiconductor material to an ionized conductor with a relatively large number of carriers per volume which is identified as “super-saturation” 28b, thus establishing a high level of conductivity.

(40) Injection current 20b introduced into the iPort control terminal 21b increases the diffused charge density (number of carriers per volume) throughout the source channel 23b, thus making the source channel 23b even more conductive. The rate of conductivity change is exponential, similar to that found in “weak-inversion.” This exponential rate of conductivity change is due to the low voltage gradient along the source channel 23b (source terminal 24b to iPort control terminal 21b voltage gradient).

(41) The iFET exponential relationship between source channel 23b charge 28b and gate voltage 25b provides access to exponential/logarithmic functionality, where the addition of two logarithmic functions is equivalent to multiplication when an antilog is applied. A reversing antilog or exponential operation recovers the analog output through the opposing complementary CiFET loading device structure. This complement is obtained through opposing diffusion types, similar to CMOS logic, instead of some other transistor linear circuit configuration. Such exponential relationship may be used for various low noise amplifier applications as well as many analog mathematical operations. The exponential relationship is also responsible for the wider dynamic range of these CiFET circuits.

(42) Again, referring to the source region in FIG. 2b, removing charge from the gate control terminal 27b or/and iPort control terminal 21b (number of carriers per volume) results in reduced conductivity of the semiconductor material in the source channel 23b. In this respect, the iPort control terminal 21b-to-source terminal 24b connection operates in a manner similar to the base-region of a bipolar transistor (which is exponential): the more control current to the iPort control terminal 21b, the more the device conductivity (g.sub.m or 1/r.sub.m). In addition to the base current operation of a bipolar transistor, the iPort works symmetrically around zero injection current in either direction, thus it possesses true bidirectional operation for four quadrant operations.

(43) The drain channel 25b of the iFET 200 operates more like a conventional FET, in that the thickness of the drain channel 25b is greater near the iPort control terminal 21b (same thickness as the source channel 23b) and tapers as it reaches its diffusion region around the drain terminal 29b (the decreasing voltage differential between drain channel 25b and gate control terminal 27b diminishes the gate 27b to channel 25b field) establishing the output resistance of the transistor as set by the gate voltage V.sub.g. The tapered decreasing channel 25b depth near the drain 29b is from the lower gate 27b to drain 29b voltage which decreases the number of carriers that are ionized up from the semiconductor body 26b below into the conduction channel 25b. When loaded with a complementary iFET, the resulting CiFET device FIG. 3e is biased at a lower gate 27b to drain 29b voltage (close to the voltage found on the gate), decreases the drain channel output resistance (thicker channel 25b at the drain diffusion). This lower drain channel resistance results in lower noise and a high output drive capability to establish the desired drain voltage at the drain 29b regardless of the capacitive load.

(44) A thick source conduction channel 23b within the iFET 200, operating at a low voltage gradient along this channel, has a low voltage gain but it has a high power gain as a result of the low input impedance which efficiently accepts input signal energy from the iPort in the form of input current. This source channel also contributes a very minimal noise.

(45) The conduction region 25b around the drain terminal 29b, operating at a higher voltage along its conduction channel 25b, provides the desired voltage gain with a minimal noise contribution when operated with the drain voltage being the same as the gate voltage V.sub.g 27b. This voltage equality is contributed by a unique biasing construct of the CiFET FIG. 3e, to be explained hereinafter.

(46) FIG. 2b further shows iFET channel charge distributions, according to the present invention, with their operating points 23c, 25c, and 23d, 25d graphed for a zero iPort injection current FIG. 2c and for a maximum positive iPort injection current FIG. 2d respectively. Vertical lines from V.sub.t at 27c/27d represent threshold voltage in FIGS. 2c and 2d. This threshold voltage is the dividing line between weak inversion and strong inversion. At threshold voltage 50% of the channel current is diffusion driven and 50% is driven by the electric field along the channel, thus below threshold voltage 27c/27d the channel current is becoming predominately diffusion driven which possesses exponential characteristics. In super-saturation, the channel is essentially all diffusion driven, thus exponential characteristics define the channel carrier conduction or channel conductance. With zero iPort injection current at 20b in FIG. 2b, as shown in FIG. 2c, bias current at I.sub.d produces the bias point output at 25c with voltage Vd 29c as it is measured at the drain terminal 29b, along with an iPort 21b voltage at its bias current I.sub.d point 23c.

(47) FIG. 2d illustrates how a small amount of iPort current 20d impressively changes the drain channel output voltage to a point at 25d: With a maximum positive iPort 20b injection current, the ΔI.sub.d bias current from 23d to 20d produces the Vd output voltage at 29d (seen at the drain terminal 29b), along with an essentially constant iPort 21b voltage at its bias point 23d. The iPort voltage remained basically constant while the drain voltage changed by nearly half of the power supply voltage, thus input current changes the output voltage, demonstrating a trans-impedance transfer function. This trans-impedance output voltage 29b, 29c, 29d changes as if the input current is flowing through the trans-impedance r.sub.m resistance, while it is actually flowing into the super-saturated source channel, which has an input resistance that is much lower. The source channel is a current to exponential voltage (at the iPort) converter and the drain channel provides the anti-log conversion back to form the output drain voltage, while providing all the drive required for various capacitive loads.

(48) The iFET 200 of the present invention can be viewed as a differential amplifier (or long tailed pair), as shown in FIG. 2e, where drain channel 25e converts the “−Voltage” input to the “Voltage Derived Current” and the iPort “+Current” input is a current (rather than a voltage). The source channel 23e converse “Bias” from negative power voltage Vss 24e. A balance is still required between the current input 21e and the voltage derived current from the drain channel 25e, with the difference being presented as a voltage change on the output terminal 29e. While this output suffers from some non-linear transfer characteristics, the use of an adaptive load with a complementary non-linearity compensates, resulting in an ultra-linear transfer function and can be viewed as a “black box” as shown in FIG. 2g.

(49) FIG. 2h shows series transistor channel arrangement in the iFET, illustrating the current-voltage arrangements of the two channels 23h and 25h which corresponds to 23b and 25b of FIG. 2b, produces voltage V.sub.out at 29h. With zero iPort 21h injection current, the current through the drain channel 25h is constrained to be the exact same current that passes through the source channel 23h. Without leakages or an iPort current, there is nowhere else for the current to go except through the series path of these two channels. If the two series transistors in FIG. 2h are sized equally, their gate to channel control voltages want to be the same. That is V.sub.gi 27h wants to be the same as V.sub.gs in FIG. 2h, thus forcing the iPort voltage V.sub.i at iPort 21h to be the same voltage as the source voltage V.sub.s at the source 24h. This restraint ideally forces low impedance at the iPort input terminated with zero volts to the source. By altering the relative conductance ratio of these two channels, the input impedance and termination voltage can be set. Since both transistor channels are made together and adjacent to each other, the input impedance and termination voltage are a very fixed and consistent pair of parameters, similar to matching of a differential pair of transistors. Their bandgap relationship configuration is a PTAT for the N channel iFET (Vittoz, Eric A. et al., “A Low-Voltage CMOS Bandgap Reference”, IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 3, June 1979, at page 573 to 577) and a CTAT reference for a P channel iFET (Anvesha A, et al., “A Sub-1V 32 nA Process, Voltage and Temperature Invariant Voltage Reference Circuit”, 2013 26.sup.th International Conference on VLSI Design and the 12.sup.th International Conference on Embedded Systems, IEEE Computer Society, 2013).

(50) FIG. 2i illustrates a slightly higher level circuit prospective of the iFET operation, which exemplifies a trans-resistance transfer function. Here an input current to a virtual PTAT reference voltage provides an output voltage change that is multiplied by the trans-resistance r.sub.m and strongly buffered. This trans-resistance r.sub.m gain ratio is typically in the range of 50K to 2 Meg.

(51) FIG. 2j is a behavioral schematic of the iFET operational model which illustrates the iFET behavioral relationship in a more detailed schematic. The current I.sub.inj the iPort sees a low R.sub.in to a PTAT voltage above V.sub.s at the iPort input. At the output this I.sub.inj current input becomes a voltage that has a magnitude that looks like it went through a high resistor r.sub.m, but is sourced at the output V.sub.out with a low impedance variable output voltage source. This low impedance can equally drive highly varying capacitive loads as normally encountered in integrated circuit instantiations. This functionality is depicted with FIG. 2g at the “black box” level where a current input produces an r.sub.m times higher V.sub.out. This black box depiction of a trans-resistance amplifier is the dual of the normal MOS amplifier depicted in FIG. 2f where an input voltage produces an output current that is the input voltage multiplied by g.sub.m. It is highly desirable to provide a voltage output instead of a current output that must be turned back into a voltage by running this current into a load resistance. The load significantly effects the voltage in the g.sub.m amplification black box while it does not in the r.sub.m black box amplifier.

(52) FIGS. 2k and 2L are suggested schematic symbol for the iFET device.

(53) FIG. 2m captures yet another application of the iFET 200, which provides a methodology of obtaining a voltage output from a bi-directional current input on the iPort. This follows a trans-impedance r.sub.m transfer-function which is precisely defined over an extremely wide dynamic range FIG. 3h. At this iPort terminal 21m, a bi-directional input current into an iFET 23m provides a proportionally large voltage change on the output 29m which is biased with a load current 28m. This operates through the weak-inversion like exponential characteristic of the iFET source channel 23b as shown in FIG. 2b by altering the amount of charge in the super-saturated 28b source channel of the iFET 200. The gate is provided with bias voltage, V.sub.bias 27m. This trans-impedance r.sub.m transfer-function is set by the relative conductance ratio of the iFET source channel 23b to drain channel 25b as plotted in FIG. 3i. Here the conductance ratio is plotted along the-axis and the trans-resistance r.sub.m or more generally, the trans-impedance is plotted up the right axis. This plot 3i also plots the directly related iPort input resistance on the left axis.

(54) Non-Inverting Nature

(55) Regarding the iPort control terminal 21b as shown in FIG. 2b, in the case of an N-channel device, a positive current 20b on the iPort control terminal 21b, such an input displaces the current coming in through the upper channel 25b, causing the drain (output) connection 29b to move in a positive direction—thus the non-Inverting nature of the iPort 21b input.

(56) Interestingly, unlike other semiconductor devices, a negative current 20b can be extracted from the iPort 21b, causing a drain (output) 29b shift in the negative direction.

(57) Proper Bias

(58) An iFET 200 (as shown in FIGS. 2a, 2b) has both gates 27a, 27b connected together and requires a proper bias voltage 22b on the gate 27a, 27b to establish the desired operating point.

(59) Symmetry

(60) A P-channel device can be constructed and behaves in a similar fashion to its N-channel counterpart.

(61) It should be emphasized that while the gate input 27a, 27b is inverted with respect to the drain, the iPort 21a, 21b is NOT inverted in EITHER the PiFET or NiFET devices diffusion types with respect to their output drains.

(62) The “Rule-of-Thumb” View:

(63) Referring to FIG. 2d or 2j, the operation of the iFET transistor is extremely simple to think about; not much more than Ohm's law is needed, and it can be seen as followings: A small + or − current input on the iPort results in a voltage out that is “K” times larger, but with the same sign as the input. 1. “K” does not change over an enormous dynamic range of operation. 2. “K” is on the order of 100,000, defined as trans-resistance (r.sub.m) and can be viewed as a simple functional block shown in FIG. 2g. r.sub.m units are ohms which is V.sub.out/I.sub.in. r.sub.m of FIG. 2g represents the transfer function of the iPort control terminal of an iFET in accordance with the present invention. 3. The r.sub.m block in FIG. 2g is the “dual” of the g.sub.m block in FIG. 2f, which defines the normal MOSFET transfer function. Accordingly, current and voltage have been interchanged, and thus r.sub.m as shown in FIG. 2g can be viewed as a simple resistance in ohms, while g.sub.m as shown in FIG. 2f is conductance in units of 1/ohms.

(64) The r.sub.m circuit of FIG. 2g has low impedance on both the input and output while the g.sub.m circuit of FIG. 2f has high impedance on both the input and output. The benefits of the r.sub.m iFET circuit of FIG. 2g are essentially zero voltage swing at the input and all the output current drive required to establish the output voltage, yielding parasitic capacitance insensitivity on both the input and output, thus very high speed. The resulting r.sub.m circuit of FIG. 2g through 2j is essentially constant with frequency and operates with much lower power supply voltages than the g.sub.m circuit of FIG. 2f, in that the trans-impedance r.sub.m iFET device's operation is basically not threshold voltage limited. The power supply voltage does not stop at the sum of threshold voltages or a threshold voltage and a saturation voltage as in prior art analog circuits, but functions well below 600 mv and operates usefully down to a millivolt of power supply voltage. Gain typically hits its maximum in the range of 600 mv to 1.0 volt of power supply voltage. Clearly not threshold voltage limited. Many of the iFET benefits are worth the trouble of re-thinking the approach to analog MOS circuit design.

(65) The useful power gain is partially realized as current gain. Although MOS circuits are perceived as voltage mode circuits, analog MOS circuits work much better as current or charge controlled circuits. After all MOS transistors operate on the instantaneous charge in their channels and do so with great precision as seen throughout this specification. The iPort input terminates in a non-varying, low value resistance (typically 50Ω-50 kΩ depending on design). The circuit allows matching an antenna impedance for maximum power transfer into the iPort input. The output is a voltage source with a low driving impedance, providing the load with whatever current is required to establish the desired voltage with precision.
Additional iFET observations of the present invention are as follows: r.sub.m does not change over the entire operating range from near clipping, all the way down to the noise floor. AC performance of an iFET is FLAT from DC to faster than logic speed. Analog voltages only move a little while logic has to get unstuck from one rail and go all the way to the other power supply rail. The iPort control terminal, being a current input, is free of voltage derived parasitic effects because the iPort control terminal has very minimal voltage change. FIG. 3k shows the input termination voltage at iPort control terminal from ½ mv to about 100 mv, depending on the iFET ratio (or input impedance), from its respective power supply rail, allowing a high compliance voltage from the other rail to bias the input such as desirable for transducer or some other input circuit. The iPort termination voltages are either a PTAT or a CTAT (proportional to absolute temperature or the complementary to absolute temperature) bandgap reference depending on the N or P semiconductor diffusion type respectively. The output in the complementary CiFET configuration swings around the self-bias midway voltage (“sweet-spot”) between the power supply rails, where it is free of power supply induced noise. Power supply induced noise cancels with this “sweet-spot” as the analog-zero reference. The advantages of operating circuits in “weak-inversion” have long been known but, so also have the problems. The iFET enables circuits to exploit the high gain and wide dynamic range available in “weak-inversion,” without sacrificing superior speed performance. In the “Behavioral Model” FIG. 2j the iPort current is converted to a voltage by a resistance (r.sub.m), whose value determines the gain. This “trans-resistance” (r.sub.m) is established by the ratio of the “drain channel” to “source channel” conductance, and remains constant throughout the entire operational range. Simulation has shown this resistance (r.sub.m) to typically be in the range of 100,000Ω, set by the relative channel sizing. r.sub.m is the dual of g.sub.m, but with more control. a. The output is a low-impedance source follower that can deliver its voltage with all the necessary transient current to drive the next circuit and capacitive load to get there. b. The input is a constant low resistance termination (related to r.sub.m but much lower) with a constant termination voltage of about 100 mv from the respective power supply rail. This offset voltage is a “bandgap” reference, established by the ratio of the “drain channel” to “source channel” conductance.
The CiFET Amplifier is the Basic Analog-in-DIGITAL Building Block:

(66) The complementary nature of a CMOS inverter of FIG. 1i is of interest for processing analog signals. If the inverter output is tied back to its input, it self-biases near the midpoint of power supply voltage. Care, of course, must be taken to size the individual transistors weakly enough as to not exceed what the IC process can handle, such as maximum current the contacts are rated for in both their AC and DC ratings. Local temperature rise is also a consideration, but self-biasing combats temperature degradation.

(67) When sized with similar pull-up conductance to pull-down conductance, the self-bias point is nicely centralized between the power supplies where noise from both the positive and negative power supplies tend to cancel. The variation in process parameters will move this midpoint voltage around a bit, but it is always relative the transistor conductance ratios. At this midpoint, the gain is arguably at the maximum available for the pair of transistors used. In addition, the pull-up performance is equal to the pull-down conductance yielding symmetric DC, AC, and transient response in either direction. The effective threshold voltages cancel each other out in that the circuit always works at its best. The AC bandwidth performance of this conventional inverter is extremely wide as compared to any analog circuit configuration as illustrated in the Bode Plot of AC Gain and Phase in FIG. 3t. You get the most bang for the least amount of parasitic loading. For the 180 nm IC process used as a comparison baseline, the 3 db gain is about 1.2 GHz with a phase shift of about 45 degrees from DC. One would be hard pressed to run equivalent low power logic at 1 GHZ in the 180 nm reference technology using a minimum power logic family.

(68) A primary limiting factor to the use of a logic inverter for an analog voltage amplifier is that the logic inverter has only about 25 db or 18× of voltage gain available with a single inverter stage, as illustrated in the standardized Bode gain-phase plot of FIG. 3t. The required minimum analog voltage gain has to be at least 80 db or 10,000×. The voltage gain defines how well the analog output signals reach their desired amplitude.

(69) Closed loop analog voltage amplifiers require inverting gain so that the output feedback can move the input back to a virtual ground input voltage. Without the amplifier being inverting, the positive feedback would result in a latched output, like a flip-flop when the feedback loop is closed. Using a series of say three inverters is virtually impossible to stabilize with any frequency response left over in a closed loop application, which is essential for practical analog amplifiers.

(70) While a single iFET has interesting characteristics on its own, a complementary pair of iFETs prove to be much more beneficial. The resulting device is arguably the highest possible power gain and widest bandwidth use of FETs possible. FIG. 3a is the schematic diagram of such a complementary pair of iFETs herein named CiFET for complementary current input field effect transistors. This is the core of the present invention.

(71) FIGS. 3b and 3c structurally relate the CiFET transistor 300 schematic diagram of FIG. 3b to the adjacent physical layout abstraction of FIG. 3c. The NiPort 31b of the NiFET transistor 301 in FIG. 3b relates to the NiPort 31c in the physical layout abstraction of FIG. 3c. The PiPort 32b of the PiFET transistor 302 relates to PiPort 32c in FIG. 3c. The reference numbers cross relate the transistor schematic to the physical layout. Likewise, these reference numerals also cross reference to the 3-dimensional sketch of FIG. 3d and the cross section AA view of FIG. 3e. This set of CiFET FIGS. 3a through 3e and their cross-reference relationship is a reflection of the prior art 2-finger inverter of FIGS. 1i to 1m.

(72) Essentially, the two pairs of opposite diffusion type transistors 101 and 102 in the inverter device structure 100 FIG. 1L, and again in FIG. 1m, are each connected in parallel: 13m in parallel with 15m as well as 14m in parallel with 16m for the 2-finger inverter 100. These two pairs of parallel transistors are also connected to the output terminal 19m with the cross-hatched metal connection 18m, or equivalently shaded portion 18k in FIG. 1k or 18n bold wire in FIG. 1m.

(73) These same two pairs of transistors 33d, 35d (or 33e, 35e) and 34d, 36d (34e, 36e) are connected in series in FIGS. 3d and 3e in order to form their respective iFET device structures 301 and 302 thus forming the CiFET device structure 300 with their respective iPort control terminals Ni, Pi access using the intermediate diffusions 31d, 32d. Just a metal mask modification from the connections 18k, 18m, 18n in FIGS. 1k, 1L, 1m to the connections 38d, 38e in FIGS. 3d and 3e, respectively, yields unprecedented analog performance as is presented in the remaining figures of this present invention. Thus CiFET designs are completely compatible, and portable, to any IC process of which all possess their most fundamental logic inverter; while being a radical improvement from the state of the art in high gain, high precision, and small scale primitive analog building blocks. The complementary pairs of iFETs are built entirely from logic components, without analog extensions, while enabling scaling and portability. Both the footprint and the power consumption per gain/bandwidth are drastically reduced from the present state of the art, while retaining superior noise performance.

(74) Referring to FIG. 3a, the complementary pair of iFETs (or CiFET) 300 comprises P-type iFET (or PiFET) 302 and N-type iFET (or NiFET) 301, comprising input terminal 30a connected to both the gate control terminal of PiFET 302 and the gate control terminal of NiFET 301, function as the common gate terminal 30a. CiFET 300 receives power, Power+ (or positive supply voltage) and Power− (or negative supply voltage), where Power− is connected to the source terminal of NiFET 301 and Power+ is connected to the source terminal of PiFET 302. Each of PiFET 302 and NiFET 301 comprises iPort control terminal (31a and 32a) for receiving injection current. The drain terminal of PiFET 302 and NiFET 301 are combined to provide output 39a.

(75) Referring to FIG. 3d (or FIGS. 3c, 3e), the CiFET 300 comprising PiFET 302 and NiFET 301, laid out on the substrate (or body B+ and B− respectively) like a mirror image along well border shown therein. PiFET 302 comprises source terminal S+ s34d (or s34c, s34e), drain terminal D+ d36d (or d36c, d36e), and iPort control terminal Pi, defining source+channel 34d (or 34c, 34e) Between the source terminal S+ and the iPort control terminal Pi diffusion region 32d (or 32c, 32e, or 32b in FIG. 3b), and drain+channel 36d (or 36c, 36e) between the drain terminal D+ and the iPort control terminal Pi diffusion region 32d (or 32c, 32e, or 32b in FIG. 3b); NiFET 301 also comprises source terminal S− s33d (or s33c, s33e), drain terminal D− d35d (or d35c, d35e), and iPort control terminal Ni, defining source−channel 33d (or 33c, 33e) between source−terminal S− s33d (or s33c, s33e) and the iPort control terminal Ni diffusion region 31d (or 31c, 31e, or 31b in FIG. 3b), and drain−channel 35d (or 35c, 35e) between drain−terminal D− d35d (or d35c, d35e) and the iPort control terminal Ni diffusion region 31d (or 31c, 31e, or 31b in FIG. 3b). CiFET 300 further comprises a common gate terminal 30d (or 30c, 30e, or 30b in FIG. 3b) over source+channel 34d (or 34c, 34e), drain+channel 36d (or 36c, 36e), source−channel 33d (or 33c, 33e), and drain−channel 35d (or 35c, 35e). Accordingly, the common gate terminal 30d (or 30a, 30b, 30c, 30e) is electrically coupled to the iPort control terminals Pi and Ni.

(76) In many analog circuits, biasing is a problem. Using iFETs in complementary pairs 301 and 302 as shown in FIG. 3d allows them to “self-bias” when the drain output 39d (or 39a, 39b, 39c, 39e) is connected to the gate input 30d (or 30a, 30b, 30c, 30e), thus eliminating drift problems and additionally, the amplifier finds the maximum gain point on its operating curve. This self-bias connection is illustrated in FIGS. 3f and 3g as 38f, 38g and also in FIG. 3L as “Bias” for an analog zero reference.

(77) In the “Behavioral Model” of CiFET of the present invention as shown in FIG. 3f, the currents I.sub.inj at the iPort control terminals 31f and 32f are converted to a voltage by trans-resistance (r.sup.m), whose value determines the gain. This “trans-resistance” (r.sub.m) is established by the ratio of the “drain channel” to “source channel” conductance, and remains constant throughout the entire operational range. Simulation has shown this resistance (r.sub.m) to typically be in the range of 100,000Ω, set by the relative channel sizing. r.sub.m in Ω is the dual of g.sub.m (1/Ω).

(78) The output V.sub.output 39f is a low-impedance source follower that can deliver its voltage with all the necessary current to drive the next circuit and any capacitive loading in between. The common gate input terminals 30f/30g represent the common gate input terminals 30a/30b/30c/30d/30e of their previous related FIGS. 3a/3b/3c/3d/3e. The CiFET structurally differs only in the output 39a/39b/39c/39d/39e metal connection 38c/38d/38e from that of the two finger inverter of FIGS. 1i/1j/1k/1L/1m output 19i/19j/19k/19m/19n metal hookup 18k/18m/18n. The CiFET is only a metal connection difference from the two-finger inverter, and can be further optimized by adjusting the individual transistor conductance for the intended CiFET purpose. Only a couple of optimizations are required for most purposes.

(79) The input is a constant low resistance termination (related to r.sub.m but much lower) with a constant offset voltage of about 100 mv from the respective power supply rail. This offset voltage is a PTAT/CTAT “bandgap” reference, established by the ratio of the “drain channel” to “source channel” conductance.

(80) A standard CiFET compound device cell can be physically constructed and used like a logic cell for designing analog. Normally this is the only active circuit component needed for analog circuits. Like a transistor, but the CiFET cell does everything needed for an active component.

(81) Now, referring to FIG. 3g, V.sub.input 30g is connected to the gate terminals of NiFET and PiFET. Positive power voltage (Power+) is connected the source terminal of PiFET, while negative power voltage (Power−) is connected to the source terminal of NiFET. NiFET provides the channel 33g and PiFET provides the channel 34g. NiFET further comprises NiPort 31g; while PiFET comprises PiPort 32g. Drain terminals of NiFET and PiFET are connected together to form V.sub.output 39g. Self-Bias path 38g is provided from V.sub.output 39g to V.sub.input 30g for repeatability.

(82) How then is the proper bias voltage produced? The simplest way of generating the bias voltage is to use iFETs in complementary pairs 301 and 302, creating an inverting device 300 as shown in FIGS. 3d and 3L, and then using the output 39d to provide negative feedback “Bias” connection in FIG. 3L to the input 30d. The CiFET as a compound device will “self-bias” at a point approximately midway between the power supplies, where the gain is maximized and the speed or slew rate is symmetrically poised for its most rapid changes. At this self-bias voltage point, the current through all of the complementary iFET channels 33d, 35d, 36d, 34d is exactly the same current, thus equal. There is no other DC current path for the PiFET 302 drain d36d to go through except into the NiFET 301 drain d35d, and thus a specific set of gate to channel voltages within the CiFET conduction channels are established for this equality of currents (or conductivity). Also since both iFETs 301 and 302 have the same current, the pull-up ability is exactly equal to the pull-down ability, which defines the maximum slew rate bias point.

(83) Since the complementary pair 300 of iFETs 301 and 302 is self-biased, any parametric factors are auto-compensated for changes in operating environment. Because of inherent matching between adjacent parts on an IC, the bias generator can be used to bias other iFETs nearby. The real-time self-biasing circuit corrects for parametric changes (in various forms).

(84) Each of the transistors in an inverter of the present invention acts as a “dynamic” load for its complement, allowing the gate voltage to be significantly higher than the traditional bias point of an analog circuit gate. With the complementary iFET compound device's higher than normal gate voltage, the source and drain conduction channels are deep, yielding lower noise.

(85) The dominant noise source in a traditional analog circuit is primarily related to the “pinch-off” region near the drain 19g of the conduction channel 15g illustrated in FIG. 1g. The length of this pinch-off region is effected by the magnitude of the drain to source voltage. Biasing the Drain 19g, 29b FIGS. 1g, 2b (or output) at the same voltage as the gate 17g, 27b (zero differential) causes the drain conduction channel to avoid the channel pinch-off (shallow channel) phenomena usually encountered in analog circuits. Another way of stating this is: a transistor gets noisier as the drain approaches its design maximum voltage, the self-biased inverter operates its transistors at half the design maximum voltage and the gate is at the same voltage as the drain (zero differential), therefore the self-biased inverter is much quieter. With lower drain voltage, the ionized conduction channel carriers diffused down away from the surface carrier traps which are just below their gate.

(86) The operation of the CiFET amplifier differs from the operation of a conventional analog amplifier, with its current mirror loads, in that:

(87) The “Source” channel, as illustrated in the individual iFET FIG. 2b, has an extremely small (˜100 mv) voltage from source terminal 24b to iPort control terminal 21b while the gate terminal 27b is at ˜½ Vsupply when complementary diffusion type iFETS 301, 302 are combined into a single CiFET device structure 300 FIG. 3d. This puts the iFET Source channel 23b, 33d, 34d into “Super-Saturation” 28b, a condition similar to weak-inversion 18e FIG. 1e but with high gate overdrive. Gate overdrive results in an unusually thick conduction layer 23b and along with a low source 24b to iPort 21b voltage resulting in that conduction layer 23b remaining thick and deep all the way along the channel. Notice the differences in the thickness between the weak-inversion 18e conduction channel 13e in FIG. 1e and the super-saturated 28b conduction channel 23b in FIG. 2b. This thick channel difference is why the iFET operates so well. It takes the desired exponential property of the conduction channel found in weak-inversion 18e and fixes its high resistance limitation to a very low resistance conduction channel, with the same exponential properties—a long wished for FET transistor performance metric.

(88) The “Drain” channel 25b operates with its' Drain terminal 29b at ˜½ Vmax, greatly reducing the pinch-off (and DIBBL) effect. This reduced pinch-off condition is further enhanced by the fact that the “Gate terminal” 27b is operated at ˜½ Vsupply (same as ½ Vmax), meaning no potential difference between the Drain 29b and the Gate 27b. Notice the difference in the thickness between the drain conduction channel 15g in FIG. 1g and that of 25b in FIG. 2b.

(89) Another important aspect of the iFET and CiFET compound device is its constant voltage low impedance current input 20b FIG. 2b that frees it from the speed robing effects of parasitic capacitance. With current input, the input voltage remains nearly constant, thus parasitic capacitance has little effect on input signal level changes.

(90) This subtle but significant difference is one of the enabling features that makes weak-inversion like exponential response work and gives the complementary iFET amplifier its linear response, superior low noise, wider dynamic range, and speed advantages.

(91) MOSFETs do not make particularly good amplifiers compared to equivalent bipolar circuits. They have limited gain, they are noisy, and their high impedance makes them slow. Process parameters are also soft, so that matching a differential input is difficult, unlike bipolar. Bipolar Diff-Amps are developed to the point where the input offset is pretty good, but the move to CMOS never really delivered as good a solution.

(92) It has long been known that superior gain and wide dynamic range performance can be obtained from CMOS operated in weak-inversion. But complications arising from high impedance, due to impractically low currents and high output resistance, preclude taking advantage of the superior gain (equivalent to that of bipolar transistors), dynamic range (exceeding that of bipolar transistors), and logarithmic performance (allowing numerous decades of amplification) that are characteristic of weak-inversion. However, the CiFET conduction channels circumvent these high-impedance limitations of weak-inversion due to the CiFET's deep conduction channels 33d, 36d, 33e, 36e FIGS. 3d, 3e respectively. The CiFET is a low-impedance device that also incorporates the noise benefits of majority carriers in a deep channel found in junction-FETs to the MOSFET. Improved signal to noise ratios are essential for analog system operation with sub 1 volt power supplies of ultra-deep sub-μm IC systems. When signals are reduced, the noise must at least be proportionally reduced to maintain the signal to ratio. System performance is all about s/n ratio in the end.

(93) While a MOSFET in weak-inversion, working into a current source load, delivers a logarithmic transfer function, the same MOSFET working into an anti-log load cancels the logarithmic nonlinearity, yielding a precisely linear transfer function. The CiFET amplifier is such a circuit, i.e.: log input, antilog load, yielding perfectly linear, wide dynamic range, low noise, and high speed performance. The low noise is a consequence of the biasing, where the source channel gate potential is unusually high and the potential across the source channel itself is maintained at near zero volts while the voltage across the drain channel is minimized. The drain channel is a level shifter, maintaining a very low voltage on the source channel while delivering high amplitude signal swings at the output with all the output drive to charge any capacitive load. The CiFET is a trans-impedance amplifier FIGS. 2g through 2j and 3f, which is a low-impedance device. The prior art trans-conductance amplifiers FIG. 2f are high-impedance devices. Low-impedance devices generally have low noise, while high-impedance devices have high noise.

(94) A 3-stage CiFET voltage amplifier delivers an open loop voltage gain of >1 million or 10.sup.6 which is 120 db and equivalent to 20 bits of digital accuracy, while still maintaining unity gain closed loop stability over its multi-GHz bandwidth. At power supply voltages below 1 volt gains can easily be around 100 million or 10.sup.8 which is 160 db and equivalent to 27 bits of digital accuracy, while still maintaining unity gain closed-loop stability over its GHz bandwidth, which is obviously limited by the noise floor. It is all about signal to noise. Gain increases as power supply voltage is dropped well below a volt. At a power supply voltage of only 10 millivolts, CiFET current input amplifiers operate with 10 db gain and closed-loop bandwidth over 1 KHz, and can operate at power supply voltages as low as 1.0 millivolt with reasonable performance. Clearly, the CiFET amplifiers are not slaved to the threshold voltage stacking that prior art amplifiers are.

(95) Taking Advantage of the Doping Profile and Ratioing:

(96) Traditionally engineers have avoided using digital logic in an analog configuration because it was believed to be unacceptably nonlinear and was difficult to bias and impossible to stabilize. Digital logic also sacrifices drive symmetry for compactness. Restoring the symmetry through proper device ratioing (˜3:1 p:n width to ˜4:1 on smaller IC processes) improves linearity, increases noise immunity, and maximizes dynamic range. Self-biasing solves the bias problem.

(97) Noise figures can be particularly optimized on front end amplifiers through proper ratioing. The iFET's electrical characteristics can be enhanced by modifying the combined and relative conductance of the source and drain channels, without modifying the available IC process (without analog extensions). When all the transistors must be the same size as in the newest IC processes, multiple transistors can be wired together to achieve the desired iFET rationing, as course resolution works fine. There are several approaches to realizing this optimization (adjusting length, width, and threshold among others).

(98) Nearly any source and drain channel size will make a functional iFET, but varying the individual iFET channel size, both relative and cumulative, increases the iFET performance depending on the objective.

(99) Fundamentally: Lower iPort input impedance is obtained via a lower source channel current density (wider source channel) as compared to the drain channel. Higher output voltage gain is obtained via higher source channel current density (narrower source channel) as compared to the drain channel. Proportionally sizing the CiFET channel interrelationships optimizes various performance metrics. Gain and symmetry are maximized when the P-channel iFET conductance to N-channel iFET conductance is equalized, thus balancing the CiFET complementary conductance. Equalizing conductance adjusts the self-bias voltage near the midpoint of the power supply voltage. This provides a symmetrical dynamic analog signal range and serves a convenient analog ground or zero reference, permitting “four quadrant” mathematical operations. Experience with deep sub-μm IC processes place the P-channel iFET to be around 3 to 4 times wider than N-channel iFET, as fixed by length or width ratios of the iFET channels. The CiFET performance is minimally affected by ambient and IC process parameter variation because of self-biasing to an optimum mid-point, regardless of conditions. The power verses speed tradeoff is controlled by the cumulative sum of all of the channel conductances used to set the idle current through the complementary iFET amplifier. This establishes the output slew rate (or output drive capability). Care must be exercised so as to not exceed both DC and transient current limitations of the biased CiFET structure. Current rating for the contacts and metal widths must be considered in determining the self-bias current and physical layout care must be considered so as to not be prone to premature failure. Local heating should also be considered. Since any logic inverter would work, it is not necessary to even make this optimization, but it is a performance booster.

(100) To be clear, the conductance of the iFET channels are a function of the individual channel width and lengths, as well as their thresholds and doping profiles. Each of the iFET channels can have individually selected sizes and/or threshold relationships to the other related channels.

(101) While iFET amplifiers can be constructed with minimum sized devices which do provide ample current at the output for very fast response and high accuracy, as stated above, care must be exercised so that the complementary iFET amplifier does not pass too much current, subjecting it to mechanical failure. The physical layout requires enough contacts and metal for the required DC and transient currents.

(102) Performance Description:

(103) FIGS. 3h to 3s exemplify performance of the CiFET device structure.

(104) FIG. 3h is a transfer function plot of the CiFET device over an extreme range of ±1 pico-amp to ±5 micro-amps of input current into either iPort, yielding a ±100 nano-volt to ±500 milli-volt output on the vertical scale. In order to cover the range, both axis are log scale. The CiFET is ratioed to provide a r.sub.m gain of 100K; Gain remains constant over the entire range; Transfer function is precisely linear; Plus and minus precisely overlay each other; Either iPort input/output precisely overlays the other; Input current can be zero; Output voltage swings around the midscale AC zero reference voltage,

(105) FIG. 3i shows how the iFET channel conductance ratio defines the trans-resistance (also known as trans-impedance indicating the same AC relationship) r.sub.m to set the CiFET device gain in which input current producing an output voltage. The iFET Ratio is along the horizontal axis as the ratio of width/length of the source channel divided by the width/length of the drain channel. The gain factor or trans-resistance is the right vertical axis in the units of Ωs using a log scale to cover the 3 decade range of values from about 1 KΩ to 1 megΩ.

(106) Also note that the iPort input resistance on the left vertical scale of the graph shown in FIG. 3i provides a precisely overlaying plot with a reduced set of values by the ratio shown on the following FIG. 3j, which is related to the peak voltage gain of the CiFET device. In other words, R.sub.in times the CiFET voltage gain yields the trans-resistance r.sub.m.

(107) The following FIG. 3k of this CiFET property set plots the iPort termination voltage over the same iFET ratio on the horizontal scale. Again, the complementary iPorts overlay each other. The scales are aligned with a match of the CiFET ratios. In reality, the N channel iPort termination voltage is a PTAT bandgap reference which has its voltage set by the iFET channel ratio relationship. The p Channel iPort is a precise complement CTAT bandgap voltage reference. When these two voltage references are added the temperature effect of the PTAT cancels the temperature dependence of the CTAT yielding temperature independent reference. Their slope offsets can be matched by the matching if the CiFET ratios and also be fine-tuned with a trim current injected into either iPort input.

(108) FIG. 3L is the transistor schematic of the CiFET used to generate these PTAT and CTAT bandgap references. The NiFET Q31L provides the PTAT reference on its iPort 31L and the PiFET Q32L provides the CTAT reference on its iPort 32L. This CiFET device also provides the analog zero bias reference on its output 30L.

(109) The precise linearity of the temperature relationship over an extremely wide temperature range of −150 to +250 degrees Centigrade is plotted in FIG. 3m. Note the total linearity. The negative or CTAT output on the PiPort overlays the CTAT when the sign is inverted. This graph suggests the usefulness in measuring temperature over extended temperature limits. The temperature sensitivity is set by the iFET ratio selection shown in FIG. 3k. A CiFET device can be tethered on a 3 wire line to sense temperature in hostile environments. This works well because the impedance of the CiFET tethered on the line would be low to minimize noise pickup.

(110) The AC gain and phase performance of the CiFET device is illustrated by a standardized Bode plot in FIG. 3n for a 75Ω iPort input resistance CiFET device, and in FIG. 3q for a 35KΩ CiFET device, with the Bode plot for a minimum sized CMOS 2-finger inverter of FIG. 1i in FIG. 3u and the reference CMOS amplifier of FIG. 1a Bode plot in FIG. 1b for comparison of all device AC properties. All Bode plot scales are the same, frequency from 0.1 Hz to 1.0 THz is the horizontal frequency axis using a log scale, gain is in dB on the vertical scale along with phase in degrees. Both gain and phase scales were set to the same set of numbers of 0 d to 180 d. The gain is the thick black line with dashed cross-hairs at the 3 db roll-off point and dotted cross-hairs at the gain cutoff frequency to provide the phase-margin on the phase trace shown as large grey square dots. There are several horizontal lines to identify gain and phase shifts. The upper dot-dash horizontal line is for a 45 degree phase shift form DC which is used to target the 3 db gain roll-off point with the dashed cross-hairs. The next grey dashed reference level is at 90 degrees followed by the dot-dot-dash line at 30 degrees to indicate a minimum acceptable phase-margin. The lower reference line is indicated by small square dots overlaying a thinner solid line to indicate the zero crossover of both gain and phase. This helps compare these three Bode plots to each other.

(111) Following these three Bode plots are three plots FIGS. 3o, 3r, 3u of the change in voltage gain over power supply voltage so that this property can be compared to the CMOS amplifier of FIG. 1a with its comparison plot in FIG. 1c. These four plots show the voltage gain as the power supply voltage is decreased in −100 milli-volt steps. The full power supply voltage for the standardized 180 nm CMOS process is 1.8 volts and is shown as a solid thick black line which is the widest bandwidth in all example plots. Form this thick black trace, the power supply steps down by a tenth of a volt in the next 7 various dot-dash combination grey traces to the thick dashed plot at a power supply of 1.0 volts. The next solid grey traces are steps from 0.9 to 0.6 volts on the power supply, followed by thin dotted traces going from 0.5 volts to 0.1 volts on the power supply. These plots show that the gain for these circuits actually goes up as power supply is reduced, with the exception of the prior art CMOS amplifier of FIGS. 1a, 1c which falls off the cliff as power supply voltage is reduced. The thin dotted cross-hair lines are on the gain at full power supply voltage and the dashed cross-hair lines is for the 1.0 volt power supply voltage.

(112) To make this set of plots easier to comprehend, additional graphs follow each plot in FIGS. 1d, 2q, 3s, 3v. These graphs relate gain and cutoff frequency to the power supply reduction. All plots have the same scales and axis variables. It can be clearly seen that the gain increases as power supply voltage is reduced. The speed or bandwidth penalty can be easily visualized with these plots. Typically bandwidth holds acceptably down to about 0.8 volts of power while gain significantly increases steadily as the power voltage is dropped down to below to about a half a volt. This is because the channels use a higher percentage of weak-inversion like diffusion current as power supply voltage is forced down. It should also be noted that the inverter also increases gain as power is reduced, for the same forced exponential mode operation point of the channels.

(113) FIG. 3p shows voltage gain and cutoff frequency as a function of power supply voltage for 75 ohm iPort CiFET device.

(114) It has been observed in FIG. 2b that the source channel 23b operates in a “Super-Saturated” mode 28b which possess exponential properties similar to weak-inversion or bipolar Beta. This mode of operation is not limited through the conventional FET threshold voltage, but rather functions with higher gain as the voltages are forced well below the conventional threshold voltage. This is because the channels are being pushed well down into their diffusion mode of operation. Here a charge injection provides additional carriers in the channel which enables an increase in current flow through the channel. This bodes well with FET transistors because field effect transistors are fundamentally charge controlled devices.

(115) This increase in gain with diminishing power supply voltage boosts weak-inversion like operation, where the charge-transport mechanism produces a higher exponential-class of gain. This is also demonstrated with the conventional CMOS inverter of FIG. 1i as shown by the standard AC performance plots of FIGS. 3t to 3v. Thus there is a methodology of obtaining higher gain with lower power supplies that, when recognized, is an alternative to analog circuits being threshold voltage limited. This completely solves the reduced voltage problem that prior art analog circuits battle in the newer IC processes.

(116) Noise Advantages:

(117) In the end, it comes down to signal-to-noise ratio. Low power supply voltage requirements in ultra-deep-sub-μm IC processes limit the maximum signal swing to a much smaller number than most analog designers are used to. So with a smaller signal, the noise must be equally small in order to maintain the desired signal to noise ratio. It is imperative that noise issues be reduced. This iFET amplifier technology not only reduces noise by an amount as would be necessary, but performs far beyond expectations, delivering ultra-quiet front ends.

(118) 1/f noise in the source channel is reduced because the self-bias scheme provides a high field strength on the source channel's gate, forcing carriers in the channel to operate below the surface where there is a smoother path (fewer obstructions) than along the surface where crystal lattice defects interfere.

(119) 1/f noise in the drain channel is also low. Unlike conventional analog designs, the gate is self-biased at the half-way point between the power supply rails as is the drain, while the iPort is within ˜100 millivolts of the power rail. With the high electric field along the drain channel, and the gate voltage equal to the drain terminal voltage, the carriers are constrained to flow mostly below the channel surface. This keeps the drain channel out of pinched off conditions, where unwanted 1/f noise would be generated.

(120) Resistance noise is minimized because the self-bias configuration puts the complementary pair at its lowest channel resistance operating point. Resistance noise is caused by collisions, between carriers and the surrounding atoms in the conductor. The lower the resistance is, the fewer the collisions.

(121) Wide band noise (white-noise) would always be an issue in high gain for high frequency circuits. While conventional designs adjust the gate voltage to establish suitable operating point(s), the designs of the present invention establish the gate voltage at the optimum point (the “sweet-spot”) and then adjust the load to establish the desired operating point. This approach establishes a higher quiescent current where (for reasons explained above) higher current density circuits have lower wide band noise.

(122) High common mode power supply rejection is inherent in the complementary iFET device structure of the present invention. Signals are with respect to the mid-point instead of being with respect to one of the power supply rails, similar to an op-amp with its “virtual” ground. Power supply noise is from one rail to the other, equal and opposite in phase with respect to each other; thus canceling around the mid-point.

(123) Ground-Loop noise is diminished because the circuit ground is “virtual” (just like in many op-amp circuits), rather than ground being one or the other power supply connections where ground or power noise is conducted into the analog signal path. . . . In the closed-loop case, “Flying Capacitors” are often employed. With “flying capacitors” there is no direct electrical connection between stages, so there is no common ground; virtual or otherwise. The use of “differential decoupling” (flying capacitors) offers transformer like isolation between stages, with the compactness of integrated circuit elements.

(124) Coupled noise from “parasitic induced crosstalk” increases by the square of the signal amplitude. Unintended capacitive coupling into a 1 volt signal causes a lot more trouble than with a 100 mV signal, by a factor of 100:1 (square law effect). The small low impedance charge or voltage signals employed in the analog sections, reduce this capacitive coupled interference substantially. Nearby Digital signals will, by definition, be high amplitude (rail-to-rail). Good layout practices are still the best defense against this digital source of noise.

(125) Additional Advantages:

(126) There are a number of additional advantages. For example, bi-directional control on the iPort means that current can flow in-to as well as out of this connection; both directions having a significant and symmetrical control effect on overall channel current. Also, a zero current imposed in the iPort is a valid zero input signal, thus the iPort signals are truly bidirectional about zero. The iPort has about five (5) orders of magnitude more dynamic control range than the gate.

(127) When the low impedance iPort is used to measure an analog Signal, the input impedance may diminish the input voltage, but the energy transfer into the iPort amplifier is high, especially for low impedance sources such as matching an antenna, transmission line, or many biological signal sources.

(128) When a high-impedance analog amplifier is necessary, the gate is sued for the input and the amplifier can contain multiple stages for high voltage gain, while the CiFET can stabilize such an amplifier.

(129) In the CiFET device there are two iPort input signals that precisely sum, thus this structure is an analog adder and can combine the two inputs at RF frequencies to form a RF mixer using a single CiFET device.

(130) The iFET of the present invention yields an analog structure that is significantly faster than logic using the same MOS devices. This speed improvement is due to the fact that the complementary structure expresses its maximum gain (and highest quiescent current) at its natural self-bias point, midway between the power supplies.

(131) Since the iPort voltage does not significantly change, it is immune to the R/C time constant effects of the surrounding parasitics, thus the iPort (current) input responds faster than the gate (voltage) input.

(132) When used as a data bus sense amplifier on a RAM, the iPort's low impedance rapidly senses minute charge transfer without moving the data bus voltage significantly. Since the iPort input impedance is low, and the iPort is terminated with a fixed low voltage, this sense amplifier approach eliminates the need for pre-charging in the memory readout cycle. Since the iFET operates at better than logic speed, IFET for sensing charge would decrease the readout time impressively.

(133) Since, in most applications of the CiFET compound device structure of the present invention, the output voltage (drain connection point) does not vary greatly, and thus making the output immune to the R/C time constant effects of the surrounding parasitics. A logic signal is slower than analog here because logic signals have to swing from rail to rail.

(134) Drain-induced barrier lowering or (DIBL) threshold reduction is avoided in the CiFET compound device operating in the analog mode. When gain and threshold voltage is important, the drains are operating around half of the power supply voltage, thus eliminating the higher drain voltages where DIBL effects are prevalent.

Definitions of Terms

(135) iFET: A 4 terminal (plus body) device similar to a Field Effect Transistor but with an additional control connection that causes the device to respond to current input stimulus.

(136) source channel: A semiconductor region between iPort diffusion and the Source diffusion. Conduction in this region is enabled by an appropriate voltage on the Gate.

(137) drain channel: A semiconductor region between Drain diffusion and the iPort diffusion. Conduction in this region is enabled by an appropriate voltage on the Gate.

(138) CiInv: A single stage, complementary iFET compound device shown in FIG. 3a.

(139) super-saturation: an exponential conduction condition similar to weak-inversion, but with high Gate overdrive and forced low voltage along the conduction channel. FIG. 2d #20.

(140) feed-forward: A technique to present a signal on an output, early on, in anticipation of the ultimate value.

(141) self-biased: Unlike fixed-bias circuits, self-biased circuits adjust to local conditions to establish an optimum operating point.

(142) dual: (of a theorem, expression, etc.) related to another by the interchange of pairs of variables, such as current and voltage as in “trans-conductance” to “trans-resistance.”

(143) trans-resistance: infrequently referred to as mutual resistance, is the dual of trans-conductance. The term is a contraction of transfer resistance. It refers to the ratio between a change of the voltage at two output points and a related change of current through two input points, and is notated as r.sub.m:

(144) $r_m=\frac{\Delta V_{\mathrm{out}}}{\Delta I_{\mathrm{in}}}$

(145) The SI unit for trans-resistance is simply the ohm, as in resistance.

(146) For small signal alternating current, the definition is simpler:

(147) trans-conductance is a property of certain electronic components. Conductance is the reciprocal of resistance; trans-conductance is the ratio of the current variation at the output to the voltage variation at the input. It is written as g.sub.m. For direct current, trans-conductance is defined as follows:

(148) $g_m=\frac{\Delta I_{\mathrm{out}}}{\Delta V_{\mathrm{in}}}$

(149) For small signal alternating current, the definition is simpler:

(150) $g_m=\frac{i_{\mathrm{out}}}{v_{\mathrm{in}}}$

(151) Trans-conductance is a contraction of transfer conductance. The old unit of conductance, the mho (ohm spelled backwards), was replaced by the SI unit, the siemens, with the symbol S (1 siemens=1 ampere per volt).

(152) translinear circuit: translinear circuit is a circuit that carries out its function using the translinear principle. These are current-mode circuits that can be made using transistors that obey an exponential current-voltage characteristic—this includes BITS and CMOS transistors in weak-inversion.

(153) Sub-threshold conduction or sub-threshold leakage or sub-threshold drain current is the current between the source and drain of a MOSFET when the transistor is in sub-threshold region, or weak-inversion region, that is, for gate-to-source voltages below the threshold voltage. The terminology for various degrees of inversion is described in Tsividis. (Yannis Tsividis (1999). Operation and Modeling of the MOS Transistor (Second Edition ed.). New York: McGraw-Hill. p. 99. ISBN 0-07-065523-5.)

(154) Sub-threshold slope: In the sub-threshold region the drain current behavior—though being controlled by the gate terminal—is similar to the exponentially increasing current of a forward biased diode. Therefore a plot of logarithmic drain current versus gate voltage with drain. source, and bulk voltages fixed will exhibit approximately log linear behavior in this MOSFET operating regime. Its slope is the sub-threshold slope.

(155) Diffusion current: Diffusion current is a current in a semiconductor caused by the diffusion of charge carriers (holes and/or electrons). Diffusion current can be in the same or opposite direction of a drift current that is formed due to the electric field in the semiconductor. At equilibrium in a p-n junction, the forward diffusion current in the depletion region is balanced with a reverse drift current, so that the net current is zero. The diffusion current and drift current together are described by the drift-diffusion equation.

(156) Drain-induced barrier lowering: Drain-induced barrier lowering or DIBL is a short-channel effect in MOSFETs referring originally to a reduction of threshold voltage of the transistor at higher drain voltages.

(157) As channel length decreases, the barrier φ.sub.B to be surmounted by an electron from the source on its way to the drain reduces.

(158) As channel length is reduced, the effects of DIBL in the sub-threshold region (weak-inversion) show up initially as a simple translation of the sub-threshold current vs. gate bias curve with change in drain-voltage, which can be modeled as a simple change in threshold voltage with drain bias. However, at shorter lengths the slope of the current vs. gate bias curve is reduced, that is, it requires a larger change in gate bias to effect the same change in drain current. At extremely short lengths, the gate entirely fails to turn the device off. These effects cannot be modeled as a threshold adjustment.

(159) DIBL also affects the current vs. drain bias curve in the active mode, causing the current to increase with drain bias, lowering the MOSFET output resistance. This increase is additional to the normal channel length modulation effect on output resistance, and cannot always be modeled as a threshold adjustment (Drain-induced barrier lowering—https://en.wikipedia.org/wiki/Drain-induced_barrier_lowering).

(160) Analogue Electronics

(161) http://en.wikipedia.org/wiki/Analogue_electronics