Process Corner Detection Circuit Based on Self-Timing Oscillation Ring

Abstract

A process corner detection circuit based on a self-timing oscillation ring comprises a reset circuit (1), the self-timing oscillation ring (2), and a counting module (3). The self-timing oscillation ring (2) consists of m two-input Miller units and inverters, and a two-input AND gate, m being a positive integer greater than or equal to 3. The circuit can be used for detecting a process corner of a fabricated integrated circuit chip, and reflecting the process corner of the chip according to the number of oscillations of the self-timing oscillation ring (2). The number of oscillations of the self-timing oscillation ring (2) in different process corners is acquired by Hspice simulation before the chip tape-out, and the process corner of the chip after the chip tape-out can be determined according to the actually measured number of oscillations.

Claims

1. A process corner detection circuit based on a self-timing oscillation ring, comprising a reset circuit (1), a self-timing oscillation ring (2), and a counting module (3), wherein the reset circuit (1) is constituted by two flip-flops DR1 and DR2, a two-input OR gate OR1, a two-input NOR gate NOR1 and a two-input NAND gate NAND1; a data input port of the flip-flop DR1 is connected to a divide-by-eight frequency signal CLK8 of a system clock, a clock port is connected to the system clock CLK, an output signal of a data output port is CLK8_1 which is connected to a data input port of the flip-flop DR2, and an output signal of an inverted data output port of the flip-flop DR1 is CLK8_1n; a clock port of the flip-flop DR2 is connected to the system clock CLK, and an output signal of a data output port is CLK8_2 which is connected to an input port of the two-input OR gate OR1; the other input port of the two-input OR gate OR1 is connected to the divide-by-eight frequency signal CLK8 of the system clock; an output signal of the two-input OR gate OR1 is a reset signal RSTn of the counting module; the two input ports of the two-input NOR gate NOR1 are connected to the signal CLK8_1 and the ground respectively, and an output signal thereof is set1; the two input ports of the two-input NAND gate NANDI are connected to a power supply VDD and the signal CLK8_1n respectively, and an output signal thereof is set0; the self-timing oscillation ring (2) is constituted by m two-input Miller units and inverters, and a two-input AND gate AND1, m being a positive integer greater than or equal to 3; the self-timing oscillation ring has m stages, each stage consisting of a Miller unit and an inverter; an output of the inverter in each stage is connected to an input port of the Miller unit in this stage, the input port of the inverter is connected to the output port of a Miller unit in a next stage, and the input port of the inverter in the m.sup.th stage is connected to the output port of the Miller unit in the first stage; the other input port of the Miller unit in the first stage is connected to the output port of the two-input AND gate AND1; the other input port of each of the other Miller units is connected to the output port of the Miller unit in a previous stage; an input port of the two-input AND gate AND1 is connected to the output port of the Miller unit in the m.sup.th stage, and the other input port is connected to the output port Q of the flip-flop DR1; the output signal of the Miller unit in the first stage serves as an output signal OSC_OUT of the self-timing oscillation ring; and the counting module (3) is constituted by n flip-flops that have reset ports and are connected in series, n being a positive integer greater than or equal to 3; the counting module has n stages, each stage being a flip-flop; the clock ports of all flip-flops are connected to the output signal OSC_OUT of the self-timing oscillation ring, and all the reset ports are connected to the reset signal RSTn output by the reset circuit; and the data input port of the flip-flop in the first stage is connected to the power supply VDD, and the data input port of the other flip-flop in each stage is connected to the data output port of the flip-flop in a previous stage.

2. The process corner detection circuit based on a self-timing oscillation ring according to claim 1, wherein the Miller unit in each stage of the self-timing oscillation ring (2) has a reset port ‘reset’ and a set port ‘set’, wherein the reset port ‘reset’ clears an output value of the Miller unit, and the set port ‘set’ sets the output value of the Miller unit for setting an initial state of the self-timing oscillation ring.

3. The process corner detection circuit based on a self-timing oscillation ring according to claim 2, wherein the Miller unit having the reset port ‘reset’ and the set port ‘set’ is constituted by three PMOS transistors MP1, MP2 and MP3, three NMOS transistors MN1, MN2 and MN3, two inverters INV1 and INV2; it has two input ports A and B, and an output port Z; the source of the NMOS tube PMOS transistor MP1 is connected to the power supply VDD, the gate is connected to an input signal A, and the drain is connected to the source of the PMOS transistor MP2; the gate of the PMOS transistor MP2 is connected to an input signal B, and the drain is connected to the drain of the NMOS transistor MN1; the gate of the NMOS transistor MN1 is connected to the input signal A, and the source is connected to the drain of the NMOS transistor MN2; the gate of the NMOS transistor MN2 is connected to the input signal B, and the source is connected to the ground GND; the source of the PMOS transistor MP3 is connected to the power supply VDD, and the gate is connected to a set signal, and the drain is connected to a node Zn connecting the drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN1; the drain of the NMOS transistor MN3 also is connected to Zn, the gate is connected to the reset signal reset, and the source is connected to the ground GND; the input port of the inverter INV1 is connected to Zn; and the output port thereof is the output port Z of the Miller unit; at the same time, Z is connected to the input port of the inverter INV2, and the output port of the inverter INV2 is also connected to Zn.

4. The process corner detection circuit based on a self-timing oscillation ring according to claim 2, wherein initial output states of the Miller units of the first m-1 stages in the self-timing oscillation ring (2) are set to be 0, and the initial output state of the Miller unit of the m.sup.th stage is set to be 1; the set ports ‘set’ of the Miller units of the first m-1 stages are all connected to the output signal set0 of the two-input NAND gate NAND1, and the reset ports ‘reset’ are all connected to the ground; and the set port ‘set’ of the Miller unit of the m.sup.th stage is connected to the power supply VDD, and the reset port ‘reset’ is connected to the output signal set1 of the two-input NOR gate NOR1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG. 1 is a structural block diagram of a circuit of the present invention;

[0022] FIG. 2 is a logical symbol of a Miller unit having a reset port and a set port in the present invention;

[0023] FIG. 3 is a circuit diagram of the Miller unit in the present invention;

[0024] FIG. 4 is a circuit diagram of a self-timing oscillation ring in the present invention;

[0025] FIG. 5 is an HSPICE simulation result diagram of the circuit in the conditions of an SS process corner, 1.8 V and 125° C. in the present invention.

DETAILED DESCRIPTION

[0026] The technical solution of the present invention is described in detail as below, but the scope of protection of the present invention is not limited to the embodiments.

Embodiment 1

[0027] As shown in FIG. 1, the process corner detection circuit based on a self-timing oscillation ring of the present invention comprises a reset circuit, a self-timing oscillation ring, and a counting module. The self-timing oscillation ring comprises at least three stages of Miller units and inverters, and the counting module comprises at least three flip-flops. In different process corners, the numbers of the oscillations of the self-timing oscillation ring within the same period are different, and the number of the flip-flops in the counting module should be larger than the largest number of the oscillations of the self-timing oscillation ring during an oscillation period. When the stage of the Miller unit and the inverter included in the self-timing oscillation ring is 9, and the stage of the flip-flop included in the counting module is 32, a detailed implementation is as follows: As shown in FIG. 1. the reset circuit is constituted by two flip-flops DR1 and DR2, a two-input OR gate OR1, a two-input NOR gate NOR1 and a two-input NAND gate NAND1; a data input port D of the flip-flop DR1 is connected to a divide-by-eight frequency signal CLK8 of a system clock, a clock port is connected to the system clock CLK, an output signal of a data output port Q is CLK8_1 which is connected to a data input port D of the flip-flop DR2, and an output signal of an inverted data output port Q of the flip-flop DR1 is CLK8_1n; a clock port of the flip-flop DR2 is connected to the system clock CLK, and an output signal of a data output port Q is CLK8_2 which is connected to an input port of the two-input OR gate OR1; the other input port of the two-input OR gate OR1 is connected to the divide-by-eight frequency signal CLK8 of the system clock; an output signal of the two-input OR gate OR1 is a reset signal RSTn of the counting module; the two input ports of the two-input NOR gate NOR1 respectively are connected to CLK8_1 and the ground, and an output signal thereof is set1; and the two input ports of the two-input NAND gate NAND1 respectively are connected to a power supply VDD and CLK8_1n, and the output signal thereof is set0.

[0028] As shown in FIG. 4, the self-timing oscillation ring is constituted by 9 two-input Miller units and inverters, and a two-input AND gate AND1; the self-timing oscillation ring has 9 stages, each stage consisting of a Miller unit and an inverter; the output of the inverter in each stage is connected to an input port of the Miller unit in this stage, the input port of the inverter is connected to the output port of the Miller unit in next stage, and the input port of the inverter in the ninth stage is connected to the output port of the Miller unit in the first stage; an input port of the Miller unit in the first stage is connected to the output port of the two-input AND gate AND1, the other input port of the Miller unit in each of the other stages is connected to the output port of the Miller unit in a previous stage, an input port of the two-input AND gate AND1 is connected to the output port of the Miller unit in the ninth stage, and the other input port is connected to the output port Q of the flip-flop DR1; and the output signal of the Miller unit in the first stage serves as the output signal OSC_OUT of the self-timing oscillation ring. The counting module is constituted by 32 flip-flops that have reset ports and are connected in series; the counting module constituted has 32 stages, each stage being a flip-flop; the clock ends of all flip-flops are connected to an oscillation output signal OSC_OUT of the self-timing oscillation ring, and the reset ports all are connected to the reset signal RSTn output by the reset circuit; and the data input port of the flip-flop in the first stage is connected to a high level (the power supply VDD), and the data input port of the flip-flop in each stage thereafter is connected to the data output port of the flip-flop in a previous stage.

[0029] The Miller unit in each stage of the self-timing oscillation ring has a reset port ‘reset’ and a set port ‘set’, as shown in FIG. 2, wherein the reset port ‘reset’ clears an output value of the Miller unit, and the set port ‘set’ sets the output value of the Miller unit so as to set an initial state of the self-timing oscillation ring.

[0030] The Miller unit having the reset port ‘reset’ and the set port ‘set’ is constituted by three PMOS transistors MP1, MP2 and MP3, three NMOS transistors MN1, MN2 and MN3 and two inverters INV1 and INV2, which has two input ports A and B, and an output port Z, as shown in FIG. 3; the source of MP1 is connected to the power supply VDD, the gate is connected to an input signal A, and the drain is connected to the source of MP2; the gate of MP2 is connected to an input signal B, and the drain is connected to the drain of MN1; the gate of MN1 is connected to the input signal A, and the source is connected to the drain of MN2; the gate of MN2 is connected to the input signal B, and the source is connected to the ground GND; the source of MP3 is connected to the power supply VDD, and the gate is connected to a set signal ‘set’, and the drain is connected to a node Zn connecting the drain of MP2 and the drain of MN1; the drain of MN3 also is connected to Zn, the gate is connected to the reset signal ‘reset’, and the source is connected to the ground GND; the input port of the inverter INV1 to Zn, and the output port thereof is the output port Z of the Miller unit; at the same time, Z is connected to the input port of the inverter INV2, and the output port of the inverter INV2 also is connected to Zn; and the aspect ratios of MP1, MP2 and MP3 are the same as the aspect ratio of the NMOS in the inverter INV1, and the aspect ratios of MN1, MN2 and MN3 are the same as the aspect ratio of the PMOS in the inverter INV1, but the aspect ratios of the PMOS and the NMOS transistors in the inverter INV2 are respectively at least less than half of the aspect ratios of the PMOS and the NMOS transistors in the inverter INV1.

[0031] The initial output states of the Miller units of the first eight stages in the self-timing oscillation ring before an oscillation are set to be 0, and the initial output state of the Miller unit of the ninth stage before an oscillation is set to be 1; the set ports ‘set’ of the Miller units of the first 8 stages are all connected to an output signal set0 of NAND1, and the reset ports ‘reset’ are all connected to the ground; and the set port ‘set’ of the Miller unit of the ninth level is connected to the power supply VDD, and the reset port ‘reset’ is connected to the output signal set1 of NOR1.

[0032] The number of 1s in the data output by the flip-flops in 32 stages in the counting module represents the number of the oscillations of the self-timing oscillation ring; and the counting result of the counting module reflects the condition of the process corner of the chip.

[0033] After finishing the design of the process corner detection circuit based on the self-timing oscillation ring, the HSPISE tool is used to perform simulation. The HSPICE simulation result of the process corner detection module is shown in FIG. 5. the process adopted by the circuit is SMIC 0.18 μm CMOS process, and the corresponding PVT conditions are an SS process corner, 1.8 V and 125° C. CLK in FIG. 5 is the system clock, OSC_out is the output of the self-timing oscillation ring, Rstn_osc is the reset signal of the counting module, and Counter [31:0] is the output of the flip-flops in 32 stages in the counting module. It can be seen from the figure that, during the period that the enabling signal CLK8_1 of the self-timing oscillation ring is at a high level, the oscillation ring outputs oscillations, while when CLK8_1 is at a low level, there is no oscillation; the reset signal Rstn_osc is a Value after performing OR operation on CLK8 and CLK8_2, which is exactly valid during two central clock periods when CLK8_1 is at a low level; and during the period that CLK8_1 is at a high level, the oscillation ring oscillates for 15 times totally, and the output value Counter [31:0] of the counting module is 7fff, containing fifteen 1, which is the same as the number of the oscillations of the oscillation ring.

[0034] The process corner detection module is simulated with different process corners and at different temperatures, and the obtained counting result of the ring oscillator is as shown in Table 1. It can be seen from Table 1 that when the chip is in an SS process corner, the number of oscillations of the ring oscillator ranges from 15 to 17; when the chip is in a TT process corner, the number of oscillations of the ring oscillator ranges from 19 to 21; and when the chip is in an FF process corner, the number of oscillations of the ring oscillator ranges from 24 to 27. In different process corners, there is no overlaps in the counting result when temperature changes.

TABLE-US-00001 TABLE 1 The Number of Oscillations of Self-Timing Oscillator at 1.8 V in Different Process Corners and at Different Temperatures Process Temperature Corner 125° C. 50° C. 25° C. −25° C. SS 15 16 16 17 TT 19 20 20 21 FF 24 25 26 27

[0035] In Table 1, 125° C. corresponds to a very extreme situation, whereas the process corner detection is performed after powering up the chip and before starting work, and at this time, the temperature of the chip may be regarded to be the same as the environment temperature, and does not reach the extreme situation. Therefore, when the process corner is determined according to the counting result of the oscillation ring, it is possible to take into account only the counting result within a normal variation range of environment temperature, i.e., situations between −25° C. and 50° C. Specific determination values are as shown in Table 2.

TABLE-US-00002 TABLE 2 Process corner determination methods corresponding to counting results Counting results N Determination result 16 ≦ N ≦ 17 SS process corner 18 ≦ N ≦ 19 Process corner between SS and TT 20 ≦ N ≦ 21 TT process corner 22 ≦ N ≦ 24 Process corner between TT and FF 25 ≦ N ≦ 27 FF process corner

[0036] It can be seen from Table 2 that when the counting result is 16 or 17, it can be determined that the chip is in an SS process corner; when the counting result is 18 or 19, it can be determined that the chip is in a process corner between SS and TT; when the counting result is from 20 to 21, it can be determined that the chip is in a TT process corner; when the counting result is from 22 to 24, it can be determined that the chip is in a process corner between TT and FF; and when the counting result is from 25 to 27, it can be determined that the chip is in an FF process corner. As stated above, although the present invention has been shown and illustrated with reference to specific preferred embodiments, it should not be interpreted as limiting of the present invention itself. Various changes in form and detail may be made on the present invention without departing from the spirit and scope thereof as defined by the appended claims.