Method of and Control System for Operating a Circuit Arrangement

Abstract

Disclosed is a method of and control system for operating a circuit arrangement, in particular a circuit arrangement of an electric vehicle for inductive power transfer to the vehicle. The circuit arrangement includes at least one phase line with at least one field receiving arrangement and at least one compensating arrangement with a variable reactance, wherein at least one current-dependent cost function is evaluated, wherein the reactance is varied such that the cost function is optimized.

Claims

1. A method of operating a circuit arrangement, wherein the circuit arrangement comprises three phase lines, wherein each phase line comprises at least one field receiving arrangement and at least one compensating arrangement with a variable reactance, wherein at least one current-dependent cost function is evaluated, wherein the reactances are varied such that the cost function is optimized, wherein the current-dependent cost function comprises at least one term per phase.

2. The method according to claim 1, wherein at least one reference input of the compensating arrangement is varied such that the cost function optimized.

3. The method according to claim 1, wherein the current-dependent cost function depends on an amplitude of the at least one phase current.

4. The method according to claim 1, wherein the circuit arrangement comprises at least one rectifier for rectifying an alternating output voltage generated by the field receiving arrangement, wherein the current-dependent cost function depends on the rectified phase current or depends on an output power of the rectifier.

5. The method according to claim 1, wherein an optimal reactance is determined by a one-dimensional optimization method.

6. The method according to claim 5, wherein the one-dimensional optimization method is a hill-climbing optimization method.

7. The method according to claim 1, wherein the current-dependent cost function depends on a sum of the amplitudes of all phase currents.

8. The method according to claim 1, wherein the reactances of the phase lines are varied sequentially.

9. The method according to claim 8, wherein the reactance of one phase line is varied for a predetermined number of times.

10. The method according to claim 1, wherein the reactance of a phase line is varied after a predetermined time period after the preceding variation of a reactance.

11. The method according to claim 1, wherein the compensating arrangement comprises a capacitive element, wherein the compensating arrangement further comprises a first switching element and a second switching element, wherein the first switching element and the second switching element are connected in series, wherein the series connection of the first and the second switching elements is connected in parallel to the capacitive element of the compensating arrangement.

12. The method according to claim 11, wherein a reference input of the compensating arrangement is a current phase angle delay, wherein the current phase angle delay defines switching times of the first and second switching elements.

13. A control system for operating a circuit arrangement, wherein the circuit arrangement comprises three phase lines, wherein each phase line comprises at least one field receiving arrangement and at least one compensating arrangement with a variable reactance, wherein the control system comprises at least one control unit and a least one means for determining at least one parameter depending on a phase current, wherein at least one current-dependent cost function is evaluatable, wherein the reactances are variable such that the cost function is optimized, wherein the current-dependent cost function comprises at least one term per phase.

Description

[0094] FIG. 1 a schematic circuit diagram of a control system,

[0095] FIG. 2 a schematic flow diagram of a method according to the invention,

[0096] FIG. 3 a schematic diagram of a variable compensating arrangement,

[0097] FIG. 4 an exemplary time course of a phase current, a phase voltage and switching times of the switching elements, and

[0098] FIG. 5 a schematic flow diagram of a hill-climbing approach.

[0099] FIG. 1 shows a schematic circuit diagram of a control system for operating a vehicle-sided circuit arrangement 1 of a system for inductive power transfer to a vehicle.

[0100] The circuit arrangement 1 comprises a field receiving arrangement 2, static compensating elements C1, C2, C3 and variable compensating arrangements CV1, CV2, CV3. The circuit arrangement 1 comprises three phases. It is shown that the field receiving arrangement 2 comprises a first set of source elements S1_1, S1_2, S1_3, a second set of source elements S2_1, S2_2, S2_3, inductances L1, L2, L3 and phase resistances R1, R2, R3.

[0101] In each phase, the respective source element S1_1, S1_2, S1_3 of the first set of source elements S1_1, S1_2, S1_3, the respective source element S2_1, S2_2, S2_3 of the second set of source elements S2_1, S2_2, S2_3, the respective leakage inductance L1, L2, L3 and the respective phase resistance R1, R2, R3 are connected in series.

[0102] The source elements S1_1, S1_2, S1_3 of the first set of source elements S1_1, S1_2, S1_3 represent a voltage source of a voltage induced by the power transfer field in a field receiving element of the respective phase, e.g. a winding structure or coil.

[0103] The source elements S2_1, S2_2, S2_3 of the second set of source elements S2_1, S2_2, S2_3 represent a voltage source of a voltage induced by an alternating electromagnetic field which is generated by the receiving elements of the remaining phase lines during reception of the power transfer field. Inductances L1, L2, L3 represent a self-inductance of the respective phase line. Resistances R1, R2, R3 represent a resistance of the respective phase line.

[0104] The field receiving arrangement 2 generates alternating phase currents I1, I2, I3 during an inductive power transfer.

[0105] Each phase further comprises one static compensating element C1, C2, C3 which is provided by capacitor with a predetermined capacitance respectively. These static compensating elements C1, C2, C3 are used to tune the circuit arrangement 1 such that the resonant frequencies provided by the series connections of the inductances L1, L2, L3, the phase resistances R1, R2, R3 and the static compensating elements C1, C2, C3 each correspond to an operating frequency of the inductive power transfer which can e.g. be 20 kHz or equal to a selected frequency within the interval of 20 kHz to 200 kHz.

[0106] Each phase further comprises one compensating arrangement CV1, CV2, CV3. An exemplary design of a compensating arrangement CV is shown in FIG. 3 in more detail.

[0107] In each phase, the respective elements of the field receiving arrangement 2 are connected in series to the respective static compensating element C1, C2, C3 and the respective variable compensating arrangement CV1, CV2, CV3.

[0108] Also shown is a rectifier 3, wherein AC terminals of the rectifier 3 are connected to output terminals T1, T2, T3 of the circuit arrangement 1. The rectifier 3 can e.g. be designed as a diode rectifier. An electrical network comprising a parallel connection of an intermediate circuit capacitor Cd and a load resistor RL is connected to DC terminals of the rectifier 3.

[0109] Further shown is the intermediate circuit capacitor Cd and the load resistor RL which represent a resistance of the electrical network connected to DC terminals of the rectifier 3.

[0110] Further indicated is a rectified phase current Id which is a DC current and a rectified voltage Ud which is a DC voltage.

[0111] Further shown is a control unit 6, a voltage sensor 7 for measuring the rectified voltage Ud and a current sensor 8 for measuring the rectified phase current Id.

[0112] At a point in time k, the control unit 6 evaluates a current-dependent cost function

J(k)=Ud(k)×Id(k)  formula 1.

[0113] The time variable k denotes the short of k×Ts, wherein Ts denotes a predetermined sampling time.

[0114] Alternatively, the current-dependent cost function could be given by

J(k)=|I1(k)|+|I2(k)|+|I3(k)|=∥Is(k)∥  formula 2,

wherein |I1(k)| denotes an amplitude of the respective phase current I1 at the point in time k and ∥Is(k)∥ the norm of Is(k). It is also possible to express the current Is as a column vector, wherein the entries of the column vector are the complex-valued phase currents I1, I2, I3. In this case, ∥Is(k)∥ can denote the 1-norm of the column vector.

[0115] The phase currents I1, I2, I3 can be measured by current sensors (not shown). The amplitude can denote the peak value or maximal absolute value during one period of the phase current I1, I2, I3 around the actual point in time k.

[0116] Alternatively, the current-dependent cost function could be given by

J(k)=|Id(k)|.sup.2×RL=(1/pi×∥Is(k)∥).sup.2×RL  formula 3.

[0117] Alternatively, the current-dependent cost function could be given by

J(k)=Id(k)  formula 4.

[0118] Further indicated are phase angle delays α1, α2, α3, wherein the phase angle delays α1, α2, α3 define switching times of the first and the second switching element S1, S2 (see FIG. 3). These phase angle delays α1, α2, α3 provide reference inputs for the compensating arrangements CV1, CV2, CV3 in each phase line, respectively. By varying the phase angle delays α1, α2, α3, the reactance of the respective compensating arrangement CV1, CV2, CV3 can be varied.

[0119] The control unit 6 can change the phase angle delays α1, α2, α3 and provide the phase angle delay α1, α2, α3 to another control unit for controlling the switching operation of the switching elements S1, S2. Alternatively, the control unit can also control the switching operation of the switching elements S1, S2 based on the phase angle delay α1, α2, α3.

[0120] However, the phase angle delays α1, α2, α3 are only exemplary reference inputs. The skilled person is aware of any alternative reference input of possible compensating arrangements by which a reactance of said arrangements can be varied.

[0121] For each phase, an overall or resulting impedance of the circuit arrangement 1 is given by the series connection of the respective inductance L1, L2, L3, the respective phase resistance R1, R2, R3, the respective static compensating element C1, C2, C3 and the respective variable compensating arrangement CV1, CV2, CV3. As a capacitance and thus a reactance of the variable compensating arrangements CV1, CV2, CV3 can be varied, the resulting or overall impedance of each phase of the circuit arrangement 1 can be varied, too. This, in turn, allows compensating a change of the impedances of the inductance L1, L2, L3, the phase resistance R1, R2, R3 and/or the static compensating element C1, C2, C3. By tuning the impedance of each phase of the circuit arrangement 1, an energy transfer during the aforementioned inductive power transfer using the proposed circuit arrangement 1 can be optimized.

[0122] In particular, the effect of a variation of the parameters of the circuit arrangement due to temperature changes and/or positional misalignment between a primary winding structure and a secondary winding structure on the inductive power transfer can be compensated for.

[0123] FIG. 2 shows a schematic flow diagram of a method according to the invention. Shown is a clock unit 9 which provides a clock signal. The clock signal is normalized by a division unit 10 such that a counter unit 11 increments a counter variable after a predetermined period of time has passed after the preceding increment.

[0124] The counter variable is provided to a switching unit 12, wherein the switching unit 12 connects an input signal path ISP to either a first output signal path OSP1, a second output signal path OSP2 or a third output signal path OSP3.

[0125] Within the input signal path ISP, a delay change Δα(k) is calculated.

[0126] If the input signal path ISP is connected to the first output signal path OSP1, a varied phase angle delay α1(k) for the switching elements S1, S2 of the compensating arrangement CV1 in the first phase line is calculated by a summing the actual phase angle delay α1(k−1) and the delay change Δα(k). The resulting value is held constant by a holding element 13.

[0127] If the input signal path ISP is connected to the second output signal path OSP2, a varied phase angle delay α2(k) for the switching elements S1, S2 of the compensating arrangement CV2 in the second phase line is calculated by a summing the actual phase angle delay α2(k−1) and the delay change Δα(k). The resulting value is held constant by a holding element 14.

[0128] If the input signal path ISP is connected to the third output signal path OSP3, a varied phase angle delay α3(k) for the switching elements S1, S2 of the compensating arrangement CV3 in the third phase line is calculated by a summing the actual phase angle delay α3(k−1) and the delay change Δα(k). The resulting value is held constant by a holding element 15.

[0129] The switching unit 12 switches sequentially between the output signal paths OSP1, OSP2, OSP3, wherein a switching operation is performed if the counter variable is equal to a predetermined number, e.g. equal to 10. If a switching operation is performed, the counter value is reset to zero.

[0130] The actual cost function value, in particular the rectified phase current Id(k), is provided to the input signal path ISP. An evaluation unit 16 which can be part of the control unit 6 or be provided by the control unit 6 (see FIG. 1) then calculates the delay change Δα(k) by a hill-climbing optimization approach. It is, for instance possible, that the evaluation unit 6 evaluates if the rectified phase current Id(k) at the actual point in time k is higher than the phase current Id(k−1) at the preceding point in time k−1. If the actual phase current Id(k) is higher, a weighting factor wf can be determined as +1 and the delay change Δα(k) can be determined as

Δα(k)=wf×Δα(k−1)  formula 5.

[0131] If the actual phase current Id(k) is lower, a weighting factor wf can be determined as −1. This means that if the delay change Δα(k−1) at the preceding point in time was positive and the actual value of the cost function, e.g. the actual value of the phase current, has increased, the delay change Δα(k) at the actual point in time will be increased again. Correspondingly, if the delay change Δα(k−1) at the preceding point in time was negative and the actual value of the cost function has increased, the delay change Δα(k) at the actual point in time will be decreased again. Correspondingly, if the delay change Δα(k−1) at the preceding point in time was negative and the actual value of the cost function has decreased, the delay change Δα(k) at the actual point in time will be increased. Correspondingly, if the delay change Δα(k−1) at the preceding point in time was negative and the actual value of the cost function has increased, the delay change Δα(k) at the actual point in time will be decreased.

[0132] FIG. 3 shows a schematic diagram of a variable compensating arrangement CV. The variable compensating arrangement CV comprises a capacitive element Cx, a first switching element S1 and a second switching element S2. Furthermore, the variable compensating arrangement CV comprises a first diode D1 and a second diode D2. The first diode D1 is connected anti-parallel to the first switching element S1. Correspondingly, the second diode D2 is connected anti-parallel to the second switching element S2. The switching elements S1, S2 can be semiconductor switches. The series connection of the first and the second switching element S1, S2 is connected in parallel to the capacitive element Cx of the variable compensating arrangement CV. It is shown that a conducting direction of the first switching element S1, which is symbolized by an arrow 4, is opposite to a conducting direction of the second switching element S2, which is symbolized by arrow 5. By controlling the switching operation of the switching elements S1, S2, in particular switching times, a reactance of the variable compensating arrangement CV can be varied, e.g. tuned to a desired reactance. This is described in WO 2014/067984 A2.

[0133] In FIG. 4 shows an exemplary time course of switching signals SS1, SS2 of the first and the second switching element S1, S2 (see FIG. 3), a phase current Ip, a voltage U.sub.Cx falling across a capacitive element Cx of the variable compensating arrangement CV (see FIG. 2), a current I.sub.Cx flowing through the capacitive element Cx and a phase voltage Up are shown. The switching signals SS1, SS2 can be high level signals H or low level signals L. If a high level signal H is applied, the switching element S1, S2 is operated in a second operating mode (closed state) and if a low level signal L is applied, the switching element S1, S2 is operated in a first operating mode (opened state). The switching signals SS1, SS2 can be gate signals of semiconductor switches which provide the first and the second switching element S1, S2. At an initial point in time t0, a high level signal H is applied to the second switching element S2. At the same time, a low level signal L is applied to the first switching element S1. At this initial point in time t0, the phase current Ip is negative. Referring to FIG. 3, the phase current Ip flows through the second switching element S2 and the first diode D1. The voltage U.sub.Cx falling across the capacitive element Cx is zero. At a first switching instant t1 the switching signal SS2 of the second switching element S2 is turned to a low level signal L. Thus, an operating mode of the second switching element is changed from a second operating mode (closed state) to a first operating mode (opened state). Now, the switch arrangement, i.e. the series connection of the first and the second switching element S1, S2, blocks the phase current Ip which consequently charges the capacitive element Cx. Thus, an absolute value of the voltage U.sub.Cx increases.

[0134] At a second switching instant t2, the first switching signal SS1 of the first switching element S1 is turned to a high level signal H. The second switching instant t2 corresponds to a zero crossing instant of the phase current Ip. The time axis in FIG. 3 shows a phase angle cot and the second switching instant t2 corresponds to a phase angle of −π/2 with reference to the phase angle of the phase voltage Up. A time difference between the first switching instant t1 and the second switching instant t2 is expressed in terms of a phase angle delay α. The phase angle delay αcan be chosen such that a predetermined maximum absolute value of the voltage U.sub.Cx during the charging of the capacitive element Cx is achieved. After the second switching instant t2, the capacitive element Cx is discharged and the absolute value of the voltage U.sub.Cx decreases, wherein the current I.sub.Cx resulting from the discharge provides the phase current Ip.

[0135] At a third point in time t3, the capacitive element Cx is completely discharged and the phase current Ip changes its current path and flows through the first switching element S1 and the second diode D2. At a third switching instant t4, the first switching signal SS1 is turned from a high level signal H to a low level signal L. Thus, the current flow through the series connection of the switching elements S1, S2 is blocked and the phase current consequently corresponds to the current I.sub.Cx charging the capacitive element Cx. At a fourth switching instant t5, the second switching signal SS2 of the second switching element S2 is turned from a low level signal L to a high level signal H. Again, the capacitive element Cx discharges, wherein the current I.sub.Cx resulting from the discharge provides the phase current Ip. A time difference between the third and the fourth switching instant t4, t5 can be expressed by the phase angle delay α. At a sixth point in time t6, the capacitive element Cx is completely discharged and the phase current Ip changes its current path and now flows through the second switching element S2 and the first diode D1.

[0136] A control unit 6 (see FIG. 1) can be used to synchronize the switching instances t1, t2, t4, t5 with the phase current Ip flowing through the circuit arrangement 1 (see FIG. 1). The control unit can e.g. generate gate pulses or gate signals which can be equal to the switching signals SS1, SS2 shown in FIG. 3. In an inactive operation of the variable compensating arrangement CV1, CV2, CV3, CV (see FIG. 1 or FIG. 3) the switching elements S1, S2 will be closed and the series connection of the switching elements S1, S2 acts as a bypass for the phase current Ip with respect to the capacitive element Cx. In a normal operation, the switching elements S1, S2 will be opened and closed periodically with a certain leading edge phase-delay (which corresponds to the phase angle delay α) to the zero crossing instants t2, t5 of the phase current Ip. The phase angle delay αwhich is proportional to a phase-delay time can be a control variable for controlling the resulting capacitance and thus the reactance provided by the variable compensating arrangement CV. After opening the switching element S1, S2, e.g. at the switching time instants t1, t4, the phase current Ip commutates from the series connection of the switching elements S1, S2 to the capacitive element Cx. The voltage U.sub.Cx falling across the capacitive element Cx starts to increase until the current zero crossing instant t2, t5 respectively. After the zero crossing instant t2, t5, the voltage U.sub.Cx falling across the capacitance Cx decreases until it reaches zero again. At this instant, the phase current Ip commutates from the capacitive element Cx back to the series connection of the switching elements S1, S2. The switch openings, e.g. at the first and the third switching time instant t1, t4, are triggered by a control logic. The switch closings e.g. at the second and the fourth switching instant t2, t5 occurs autonomously due to the diodes D1, D2 placed inside the bidirectional switch arrangement provided by the series connection of the first and the second switching element S1, S2.

[0137] FIG. 5 shows a schematic flow diagram of a hill-climbing approach in order to determine the optimal phase angle delay α(k) for one of the phases. The optimal phase angle delay α(k) is used in order to operate one of the variable compensating arrangements CV1, CV2, CV3, CV (see FIG. 1 or FIG. 3).

[0138] In a first step St1 of one cycle of the iteration procedure, the rectified phase current Id(k) is measured. Further, the rectified phase current Id(k) is saved. The rectified phase current Id(k) provides a cost function value at the point in time k. In a second step St2, the rectified phase current Id(k) of the actual cycle is compared to the rectified phase current Id(k−1) which was measured at the first step St1 of the preceding cycle of the iteration procedure. If it is larger than or equal to the rectified phase current Id(k−1) of the last cycle, the search direction remains unchanged. If it is smaller, the search direction is changed, in particular reversed, in a third step St3.

[0139] In a fourth step St4, the current search direction is evaluated. If the search direction is directed upwards, e.g. if the search direction is positive, the phase angle delay α(k) of the actual cycle is determined as α(k)=α(k−1)+Δα(k) in a fifth step St5. Alternatively, if the search direction is directed downwards, e.g. if the search direction is negative, the phase angle delay α(k) of the actual cycle is determined as α(k)=α(k−1)−Δα(k) in the fifth step St5.

[0140] The absolute value of the delay change Δα(k) of the actual cycle can be constant for all cycles of the iteration procedure.

[0141] In a sixth step St6, the value of the phase angle delay α(k) is evaluated and compared to an upper limit and a lower limit. If the phase angle delay α(k) is larger than the upper limit, it can be limited to said upper limit. If the phase angle delay α(k) is smaller than the lower limit, it can be limited to said lower limit.

[0142] Finally, the calculated phase angle delay α(k) can be provided to the respective variable compensating arrangement CV1, CV2, CV3, CV or a control unit for controlling the operation of the respective variable compensating arrangement CV1, CV2, CV3, CV.