Radio communications

Abstract

A radio receiver device is arranged to store samples of incoming data symbols in an indexed memory portion having a length of A+B+C. A first data buffer 20-1 has an initial address at index 0 and a final address at index A-1. A timing adjustment buffer 22 has an initial address at index A and a final address at index A+B−1. A second data buffer 20-2 has an initial address at an index A+B and a final address at an index A+B+C−1. A buffer switch pointer 24 has a trigger address between the index 0 and the index A+B−1, at which it triggers a switch 26 from the first to the second buffer. If the current address matches the trigger address, the current address is set to the index A+B. Otherwise, the current address is incremented. If there is a timing offset between local and network clocks, the trigger address is moved to reduce the offset.

Claims

1. A radio receiver device comprising: an indexed memory portion having a length of at least A+B+C memory units, wherein A, B, and C are positive, non-zero integers, and wherein the radio receiver device is arranged to receive a plurality of data symbols from an incoming bitstream and store a plurality of samples of each of the plurality of data symbols in the indexed memory portion, said indexed memory portion being logically arranged such that: a first data buffer has an initial address at an index 0 and a final address at an index A−1; a timing adjustment buffer has an initial address at an index A and a final address at an index A+B−1; a second data buffer has an initial address at an index A+B and a final address at an index A+B+C−1; and a buffer switch pointer having a trigger address and arranged to trigger a switch from the first data buffer to the second data buffer when a current address matches the trigger address, said trigger address being an address between the index 0 and the index A+B−1; wherein the radio receiver is arranged such that: on initialisation, the current address is set to the index 0; each of the plurality of samples is stored at the current address; if the current address does not match the trigger address, the current address is incremented, but if the current address does match the trigger address, the current address is set to an index A+B; and if the radio receiver device determines that there is a timing offset between a local reference clock and a network clock, the trigger address is moved in order to reduce the timing offset.

2. The radio receiver device of claim 1, further arranged such that if the radio receiver device determines that any remaining timing offset between the local reference clock and the network clock is below a threshold, the trigger address is moved to the index A−1.

3. The radio receiver device as claimed of claim 1, wherein the trigger address is set to index A−1 on initialisation.

4. The radio receiver device of claim 1, wherein a second data buffer switch pointer has a second trigger address at an index A+B+C−1.

5. The radio receiver device of claim 1, wherein the indexed memory portion has a length of at least A+B+C+D memory units, wherein D is a positive, non-zero integer, said indexed memory portion being further arranged such that: a second timing adjustment buffer has an initial address at an index A+B+C and a final address at an index A+B+C+D−1; and a second buffer switch pointer having a second trigger address and arranged to trigger a switch from the second data buffer to the first data buffer when the current address matches the second trigger address, said second trigger address being an address between the index A+B and the index A+B+C+D−1; wherein the radio receiver device is arranged such that: if the current address does not match the trigger address or the second trigger address, the current address is incremented; if the current address does match the trigger address, the current address is set to the index A+B; if the current address does match the second trigger address, the current address is set to the index 0; and if the radio receiver device determines that there is a timing offset between a local reference clock and a network clock, the trigger address and/or the second trigger address(es) are moved in order to reduce the timing offset.

6. The radio receiver device of claim 1,wherein a length A of the first data buffer is equal to a length C of the second data buffer.

7. The radio receiver device of claim 1, wherein the data symbols comprise orthogonal frequency division multiplexing data symbols.

8. The radio receiver device of claim 1, arranged to carry out LTE radio communications.

9. The radio receiver device of claim 1, wherein the first and/or second data buffers are a plurality of data symbols long.

10. The radio receiver device of claim 1, further comprising a processor arranged such that: the processor reads the samples from the first data buffer only when the radio receiver device is not writing to the first data buffer; and the processor reads the samples from the second data buffer only when the radio receiver device is not writing to the second data buffer.

11. The radio receiver device of claim 10, wherein the processor comprises a vector processor.

12. A non-transitory, computer readable medium comprising instructions that, when executed on a suitable processor, performs a method of operating a radio receiver device, the radio receiver device comprising: an indexed memory portion having a length of at least A+B+C memory units, wherein A, B, and C are positive, non-zero integers, and wherein the radio receiver device is arranged to receive a plurality of data symbols from an incoming bitstream and store a plurality of samples of each of the plurality of data symbols in the indexed memory portion, said indexed memory portion being logically arranged such that: a first data buffer has an initial address at an index 0 and a final address at an index A−1; a timing adjustment buffer has an initial address at an index A and a final address at an index A+B−1; a second data buffer has an initial address at index an A+B and a final address at an index A+B+C−1; and a buffer switch pointer having a trigger address and arranged to trigger a switch from the first data buffer to the second data buffer when a current address matches the trigger address, said trigger address being an address between the index 0 and the index A+B−1; wherein the method comprises: setting the current address to the index 0 on initialisation; storing each of the plurality of samples at the current address; incrementing the current address if the current address does not match the trigger address, but setting the current address to an index A+B if the current address does match the trigger address; and determining when there is a timing offset between a local reference clock and a network clock and moving the trigger address in order to reduce the timing offset.

13. A radio receiver device comprising: an indexed memory portion, wherein the radio receiver device is arranged to receive a plurality of data symbols from an incoming bitstream and store a plurality of samples of each of the plurality of data symbols in the indexed memory portion, said indexed memory portion being logically arranged such that the indexed memory portion comprises a plurality of pairs of data buffers and timing adjustment buffers, wherein each pair is of length A+B memory units, where A and B are non-zero, positive integers, each comprising: a data buffer having an initial address at an index 0 and a final address at an index A−1; a timing adjustment buffer having an initial address at an index A and a final address at an index A+B−1; and a buffer switch pointer having a trigger address and arranged to trigger when a current address matches the trigger address, said trigger address being an address between the index 0 and the index A+B−1; wherein the radio receiver device is arranged such that: on initialisation, the current address is set to the index 0; each of the plurality of samples is stored at the current address; if the current address does not match the trigger address, the current address is incremented, but if the current address does match the trigger address, the current address is set to the index 0 of a data buffer within a different pair; and if the radio receiver device determines that there is a timing offset between a local reference clock and a network clock, the trigger address is moved in order to reduce the timing offset.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) Certain embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

(2) FIG. 1 is a block diagram of a radio receiver device in accordance with an embodiment of the present invention;

(3) FIG. 2 is a block diagram of a memory arrangement comprising the buffers for use in the radio receiver device of FIG. 1;

(4) FIG. 3 is a timing diagram illustrating operation of the radio receiver device of FIG. 1 when no timing adjustment is needed;

(5) FIG. 4 is a timing diagram illustrating operation of the radio receiver device of FIG. 1 when the buffer switch timing is delayed; and

(6) FIG. 5 is a timing diagram illustrating operation of the radio receiver device of FIG. 1 when the buffer switch timing is advanced.

DETAILED DESCRIPTION

(7) FIG. 1 is a block diagram of a radio receiver device 2 in accordance with an embodiment of the present invention. The radio receiver device 2 comprises a hardware unit 4 and a processor subsystem 6. The processor subsystem 6 comprises a “tightly coupled memory” (TCM) 8 and a vector processor 10. Each of these components will be described in turn below.

(8) The hardware unit 4 is arranged to receive incoming data signals 12 which may, for example, be received via an upstream radio front end including an antenna (not shown) that is arranged to receive LTE signals over an LTE network. The hardware unit 4 is arranged to process the signals 12 before storing them in the buffers within the TCM 8.

(9) The hardware unit 4 produces samples 14 that are suitable for storing within two or more buffers within the TCM 8 as will be described in further detail below with reference to FIG. 2. The vector processor 10 can then retrieve the data 15 stored within the TCM 8 as a one dimensional array (i.e. a vector) and perform any processing steps that are required of it at a later time. The samples 14, 15 may be converted to the frequency domain by the processor 10 in a manner known in the art per se, for example using a fast Fourier transform (FFT).

(10) While in this embodiment, the memory in which the signals 14 are stored is within the processor subsystem 6, it will be appreciated that the memory may instead be located externally of the processor subsystem 6 in other embodiments.

(11) FIG. 2 is a block diagram illustrating how the buffers are arranged logically within the TCM 8. The TCM 8 is divided into a number of memory blocks 16.sub.0 to 16.sub.p, i.e. there are p+1 memory blocks. Each of these memory blocks 16.sub.0 to 16.sub.p have a width 18 such that all of the memory blocks 16.sub.0 to 16.sub.p are the same size, however it will be appreciated that this is optional and in general the memory blocks 16.sub.0 to 16.sub.p could be of different sizes.

(12) Each of the memory blocks 16.sub.0 to 16.sub.p are divided into a number of memory banks. For example, the memory block 16.sub.1 is divided into memory banks 16.sub.1-0 to 16.sub.1-q i.e. each memory block 16.sub.0 to 16.sub.p is divided into q+1 memory banks.

(13) In this particular embodiment, the TCM 8 is arranged to provide two buffers. The first data buffer 20.sub.1 comprises the memory banks 16.sub.1-0 to 16.sub.1-q of a first memory block 16.sub.1. Similarly, the second data buffer 20.sub.2 comprises the memory banks 16.sub.2-0 to 16.sub.2-q of a second memory block 16.sub.2. In order to facilitate LTE communications, each of these buffers 20.sub.1, 20.sub.2 are one sub-frame wide, i.e. they are each arranged to store fourteen OFDMA data symbols. The TCM 8 is arranged such that these memory blocks 16.sub.1, 16.sub.2 may be accessed simultaneously, in parallel. As will be described below, this allows one buffer to be filled while the other is read by the vector processor 10.

(14) It will of course be appreciate that the buffers 20.sub.1, 20.sub.2 may have other widths, for example they may be one slot (i.e. seven OFDMA symbols) wide or they may be a single OFDMA symbol wide. The number of memory indices (i.e. the number of samples) that are needed for each incoming OFDMA symbol depends on the sample rate being used which, in turn, depends on the LTE bandwidth being used. For example the bandwidth may be either 1.4, 3, 5, 10, or 20 MHz, where the corresponding sample rate is 1.92, 3.84, 7.68, 15.36, 23.04, or 30.72 MHz respectively.

(15) The TCM 8 is also arranged to store a timing adjustment buffer 22. The timing adjustment buffer 22 is stored in the memory banks 16.sub.3-0 to 16.sub.3-q of a third memory block 22. The operation of this timing adjustment buffer 22 is described in further detail with reference to FIG. 3 below.

(16) While in the arrangement of FIG. 2 there are two data buffers 20.sub.1, 20.sub.2 and one timing adjustment buffer 22, it will be appreciated that, in general, there may be more than two data buffers and more than one timing adjustment buffer, where these additional data and/or timing adjustment buffers may be stored in one or more of the other memory blocks 16.sub.0 to 16.sub.p. The timing adjustment buffer 22 could instead be located in the same block as one of the data buffers 20.sub.1, 20.sub.2.

(17) Operation of the radio receiver device 2 of FIG. 1 will now be described with reference to FIGS. 3 to 5, which illustrate how the device 2 may adjust the timing at which it swaps between storing the samples 14 in the first data buffer 20.sub.1 and the second data buffer 20.sub.2.

(18) FIG. 3 is a timing diagram illustrating operation of the radio receiver device 2 of FIG. 2 when no timing adjustment is needed. In general, the hardware unit 4 is arranged initially to store samples 14 of each incoming data symbol in the first data buffer 20.sub.1 which is indexed from 0 to A−1 (i.e. the first data buffer 20.sub.1 has a length of A, which, as discussed above, may be 14 data symbols in LTE applications). A timing adjustment buffer 22 is provided from index A to index A+B−1 (i.e. the timing adjustment buffer 22 has a length B). The second data buffer 20.sub.2 is provided from index A+B to index A+B+C−1.

(19) Initially, the hardware unit 4 directs the samples 14 into the first data buffer 20.sub.1. It stores each incoming sample 14 in the next subsequent memory address, starting from index 0 and filling up the first data buffer 20.sub.1 until it reaches the address A−1. A buffer switch pointer 24 has its trigger address (i.e. the ‘from’ address at which the buffer switch pointer 24 instructs the hardware unit 4 to jump to a different buffer or ‘to’ address) set to address A−1 which indicates to the hardware unit 4 that it should switch to storing sample data signals 14 in the second data buffer 20.sub.2. This results in the hardware unit 4 performing a “jump” 26 in the current address from A−1 to A+B, i.e. skipping over the timing adjustment buffer 22 when the current address matches the trigger address.

(20) The hardware unit 4 will then fill the second data buffer 20.sub.2 starting from the address indexed by A+B until the end of the second data buffer 20.sub.2 at the address indexed A+B+C−1. The final address of the second data buffer 20.sub.2 indexed by A+B+C−1 then matches the trigger address of a second data buffer switch pointer 25 which, when that trigger address is reached, indicates to the hardware unit 4 that it should jump back 27 to the first data buffer 20.sub.1.

(21) FIG. 4 is a timing diagram illustrating operation of the radio receiver device 2 of FIG. 1 when the buffer switch timing is delayed. As described before with reference to FIG. 3, the hardware unit 4 directs the samples 14 into the first data buffer 20.sub.1 and stores each incoming sample 14 in the next subsequent memory address, starting from index 0 and filling up the first data buffer 20.sub.1 until it reaches the address A−1.

(22) However, due to a mismatch between the local timing and the network timing, the radio receiver device 2 has not completely received the incoming data symbol and so switching once address A−1 is reached would cause the samples 14 corresponding to that OFDMA symbol to be stored across both data buffers 20.sub.1, 20.sub.2. In this particular example, switching buffers at the normal time as described above with reference to FIG. 3 would result in the switch happening three samples early, leading to the last three samples of the corresponding OFDMA symbol being stored in a different buffer to the other samples of that OFDMA symbol.

(23) In order to address this problem, the hardware unit 4 moves the trigger address of the buffer switch pointer 24 to address A+2, i.e. it delays it by three samples before jumping 28 the current address to A+B to begin filling the second data buffer 20.sub.2. This effectively extends the length of the first data buffer by making use of some of the extra storage space provided by the timing adjustment buffer 22.

(24) While this may still result in the samples corresponding to this particular OFDMA symbol being divided between different areas in memory, the next incoming OFDMA symbol and all subsequent OFDMA symbols will match the buffer length and normal operation (i.e. as described with reference to FIG. 3) can resume from that point forward, until any future timing issues arise. If the first data buffer, timing adjustment buffer, and second data buffer are arranged logically consecutively in that order, memory management may be made easier, though the timing adjustment benefits are still apparent even if the buffers are located in a different order and/or are not consecutive.

(25) FIG. 5 is a timing diagram illustrating operation of the radio receiver device 2 of FIG. 1 when the buffer switch timing is advanced. As described before with reference to FIG. 3, the hardware unit 4 directs the samples 14 into the first data buffer 20.sub.1 and stores each incoming sample 14 in the next subsequent memory address, starting from index 0 and filling up the first data buffer 20.sub.1 sequentially.

(26) However, due to a mismatch between the local timing and the network timing, the radio receiver device 2 has completely received a particular incoming data symbol prior to reaching the end of the first data buffer 20.sub.1 and so waiting to switch until address A−1 is reached would cause samples of the next OFDMA symbol to be stored across both data buffers 20.sub.1, 20.sub.2. In this particular example, switching buffers at the normal time as described above with reference to FIG. 3 would result in the switch happening two samples late, leading to the first two samples of the next incoming OFDMA symbol being stored in a different buffer to the remainder.

(27) In order to address this problem, the hardware unit 4 moves the trigger address of the buffer switch pointer 24 to address A−3, i.e. it advances it by two samples such that it jumps 30 the current address to A+B before even reaching A−1 and begins filling the second data buffer 20.sub.2. This effectively reduces the length of the first data buffer.

(28) As in the case described with reference to FIG. 4, once this timing adjustment is made, the next incoming OFDMA symbol and all subsequent OFDMA symbols will match the buffer length and normal operation (i.e. as described with reference to FIG. 3) can resume from that point forward, until any future timing issues arise.

(29) Thus it will be appreciated by those skilled in the art that embodiments of the present invention provide an improved radio receiver device that can dynamically adjust its local timing relative to the network timing so as to realign the buffer switching point in order to ensure that the samples of the data symbols are stored correctly (i.e. it can adjust the timing ‘on-the-fly’, during operation). It will be appreciated by those skilled in the art that the embodiments described above are merely exemplary and are not limiting on the scope of the invention.