OPTOELECTRONIC SEMICONDUCTOR CHIP

Abstract

In one embodiment, the invention relates to an optoelectronic semiconductor chip comprising a semiconductor layer sequence. The semiconductor layer sequence has an n-conducting first layer region, a p-conducting second layer region and an active zone lying therebetween for generating radiation. The second layer region comprises a first subregion directly adjacent to the active zone, the first subregion being composed of p-conducting InvAl1−vP. The second layer region also comprises a second subregion directly adjacent to the first subregion, the second subregion having p-conducting Iny(GaxAl1−x)1−yP. The second layer region also comprises a third subregion as a p-contact layer directly adjacent to the second subregion.

Claims

1. An optoelectronic semiconductor chip comprising a semiconductor layer sequence having: an n-conducting first layer region, a p-conducting second layer region, and an active zone for generating radiation between the first and second layer regions (21, 23), wherein the second layer region comprises: a first partial region directly at the active zone composed of p-conducting In.sub.vAl.sub.1-vP, a second partial region directly at the first partial region comprising p-conducting In.sub.y(Ga.sub.xAl.sub.1-x).sub.1-yP, and a third partial region as p-type contact layer directly at the second partial region, wherein a thickness of the third partial region is at most 0.7 μm.

2. The optoelectronic semiconductor chip as claimed in claim 1, wherein 0.4≤v≤0.6, 0.4≤x≤0.9 or 0.2≤x≤0.5, 0.4≤y≤0.6, a thickness of the first partial region is at least 0.2 μm and at most 1 μm, a thickness of the second partial region is at least 0.01 μm and at most 1.5 μm, and a thickness of the third partial region is at least 0.05 μm and at most 0.7 μm.

3. The optoelectronic semiconductor chip as claimed in claim 1, wherein the second partial region consists of a single layer composed of In.sub.y(Ga.sub.xAl.sub.1-x).sub.1-yP.

4. The optoelectronic semiconductor chip as claimed in claim 1, wherein the second partial region is formed by a superlattice comprising a plurality of partial layers composed of p-doped In.sub.y(Ga.sub.xAl.sub.1-x).sub.1-yP.

5. The optoelectronic semiconductor chip as claimed in claim 4, wherein the partial layers are lattice-matched to GaAs, such that a lattice constant of the partial layers deviates from the lattice constant of GaAs at room temperature by at most a factor of 1.002, wherein the partial layers each have a thickness of at least 10 nm.

6. The optoelectronic semiconductor chip as claimed in claim 5, wherein in the second partial region the partial layers and barrier layers composed of p-doped In.sub.wAl.sub.1-xP where 0.4≤w≤0.6 are arranged alternately with respect to one another, wherein a thickness of the barrier layers deviates from the thickness of the partial layers by at most a factor of 2.

7. The optoelectronic semiconductor chip as claimed in claim 4, wherein the partial layers are tensile-strained vis à vis GaAs, such that a lattice constant of the partial layers at room temperature is less than the lattice constant of GaAs by at least a factor of 1.005, wherein the partial layers each have a thickness of at most 10 nm.

8. The optoelectronic semiconductor chip as claimed in claim 7, wherein in the second partial region the partial layers and barrier layers composed of p-doped In.sub.wAl.sub.1-wP where 0.4≤w≤0.6 are arranged alternately with respect to one another, wherein a thickness of the barrier layers is greater than the thickness of the partial layers by at least a factor of 1.5 and by at most a factor of 5.

9. The optoelectronic semiconductor chip as claimed in claim 4, wherein the superlattice has a miniband structure, such that an effective band gap between a valence band and a conduction band lies between a band gap of the partial layers composed of p-doped In.sub.y(Ga.sub.xAl.sub.1-x).sub.1-yP and a band gap of barrier layers composed of p-doped In.sub.wAl.sub.1-wP where 0.4≤w≤0.6.

10. The optoelectronic semiconductor chip as claimed in claim 9, wherein the partial layers and the barrier layers each have a thickness of between 2 nm and 8 nm inclusive.

11. The optoelectronic semiconductor chip as claimed in claim 4, wherein the superlattice has between 20 and 100 periods inclusive.

12. The optoelectronic semiconductor chip as claimed in claim 1, wherein the third partial region fashioned as a p-contact layer is composed of GaP, composed GaAs and/or composed of AlGaP and is doped with C, Mg and/or Zn.

13. The optoelectronic semiconductor chip as claimed in claim 1, wherein in a direction away from the active zone the third partial region is directly followed by a second electrode layer, wherein the second electrode layer is composed of at least one transparent conductive oxide and/or metal, and wherein a first electrode layer is situated at the n-conducting first layer region.

14. The optoelectronic semiconductor chip as claimed in claim 1, wherein an average band gap of the second partial region is greater than an average band gap of the active zone by at least a factor of 1.05 and by at most a factor of 1.5.

15. The optoelectronic semiconductor chip as claimed in claim 1, which is a light emitting diode chip, wherein the active zone is configured for generating red light and the n-conducting first layer region comprises n-doped InAlP or is composed of n-doped InAlP.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In the figures:

[0051] FIG. 1 shows a schematic sectional illustration of one exemplary embodiment of an optoelectronic semiconductor chip described here,

[0052] FIGS. 2 to 4 show schematic illustrations of energy levels of the optoelectronic semiconductor chip from FIG. 1,

[0053] FIGS. 5 to 7 show schematic illustrations of energy levels of a modification of a semiconductor chip,

[0054] FIG. 8 shows a schematic sectional illustration of one exemplary embodiment of an optoelectronic semiconductor chip described here,

[0055] FIGS. 9 and 10 show schematic illustrations of energy levels of the semiconductor chip from FIG. 8,

[0056] FIG. 11 shows a schematic sectional illustration of one exemplary embodiment of an optoelectronic semiconductor chip described here, and

[0057] FIGS. 12 and 13 show schematic illustrations of energy levels of the semiconductor chip from FIG. 11.

DETAILED DESCRIPTION

[0058] FIG. 1 shows one exemplary embodiment of an optoelectronic semiconductor chip 1. The semiconductor chip 1 is a light emitting diode chip and comprises a semiconductor layer sequence 2 based on the material system InGaAlP or InGaAlPAs.

[0059] The semiconductor layer sequence 2 comprises an n-conducting first layer region 21, a p-conducting second layer region 23 and, therebetween, an active zone 22 for generating radiation, preferably for generating red light. In FIG. 1, the n-conducting first layer region 21 is formed by a single layer, but can alternatively also be composed of a plurality layers. The active zone 22 is a multi quantum well structure, MQW for short, which is composed alternately of barrier layers 25 and quantum well layers 24.

[0060] The p-conducting second layer region 23 is composed of a first partial region 31, a second partial region 32 and a third partial region 33. Along a growth direction G of the semiconductor layer sequence, these partial regions 31, 32, 33, in a direction away from the active zone 22, succeed one another directly and preferably over the whole area in each case.

[0061] The first partial region 31 is composed of InAlP and the second partial region is composed of a single layer composed of InGaAlP. Either the partial regions 31, 32 have an approximately identical thickness or the second partial region 32 is thicker than the first partial region 31. The third partial region 33 is fashioned as a semiconductor contact layer and consists either of exactly one layer or, as symbolized by a dashed line in FIG. 1, of two layers.

[0062] For the energization of the semiconductor layer sequence 2, a first electrode layer 51 is situated at the first layer region 21 and a second electrode layer 52 is situated at the second layer region 23. By way of example, the second electrode layer 52 is composed of a TCO layer 53 and of a metallization 54. TCO stands for transparent conductive oxide, for example ITO or ZnO. The first electrode layer 51 is fashioned for example as a mirror layer, in particular as a combination mirror with a layer composed of a low refractive index material, through which perforations of a metallization can extend, not depicted in FIG. 1.

[0063] As also in all the exemplary embodiments, it is optionally possible for a growth substrate to have been removed from the semiconductor layer sequence 2 and for the semiconductor layer sequence 2 to be fitted on a carrier 6. The carrier 6 is composed in particular of a semiconductor material such as Si, of a ceramic such as Al.sub.2O.sub.3 or of a metal such as Mo. Optionally present prismatic structures at the first electrode layer 51 and/or light output coupling structures at the second layer region 23 are not depicted in FIG. 1 for the sake of simplifying the illustration.

[0064] FIGS. 2 to 4 schematically show various illustrations concerning energy levels of the semiconductor chip 1 from FIG. 1. The second layer region 23 is illustrated in a simplified manner in FIG. 2, wherein an energy E is plotted against the growth direction G. The energy levels Ec1, Ec2 of the conduction band and Ev1, Ev2 of the valence band are shown. The activation energy levels Eat, Eat are additionally depicted, with the numbering 1 respectively for p-InAlP and with the numbering 2 respectively for p-InGaAlP. In FIG. 3, the energy E is plotted against a wave vector or a wave number k.

[0065] In FIG. 4 the energy E is plotted against the growth direction G for a larger region of the semiconductor layer sequence 2. As a result of the smaller band gap in the region of the p-InGaAlP layer 32, the series resistance is able to be reduced, on account of the better electrical conductivity of InGaAlP relative to InAlP.

[0066] By way of example, the following holds true for the semiconductor layer sequence 2: [0067] the n-conducting first layer region 21 is composed of In.sub.zAl.sub.1-zP where 0.49≤x≤0.51, doped with Te or Si, [0068] in the active zone 22 the quantum well layers 24 are composed of In.sub.a(Ga.sub.1-bAl.sub.b).sub.1-aP where 0.49≤a≤0.7 and 0≤b≤0.5 or 0<b≤0.50 and the barrier layers 25 are composed of In.sub.c(Ga.sub.1-dAl.sub.d).sub.1-cP where 0.49≤c≤0.51 and 0.2≤d≤0.7), [0069] the first layer region 31 is composed of p-In.sub.vAl.sub.1-vP where 0.49≤v≤0.51, doped with Mg or Zn, [0070] the second partial region 32 is composed of p-In.sub.y(Ga.sub.1-xAl.sub.x).sub.1-yP where 0.49≤y≤0.51 and for example where 0.2≤x≤0.5, doped with Te or Si, and [0071] the third partial region 33 is composed of the layer pair Al.sub.gGa.sub.1-gAs:C/GaAs:C where 0.45≤g≤0.9 or of a layer composed of Al.sub.hGa.sub.1-hP:C where 0≤h≤0.5 or 0<h≤0.5.

[0072] FIGS. 5 to 7 illustrate energy profiles for a modification 10 of the semiconductor chip. In this modification 10, see FIG. 7 in particular, no InGaAlP layer is present in the second layer region 23. As a result, see FIGS. 5 and 6 in comparison with FIGS. 2 and 3 concerning the semiconductor component 1 described here, the acceptor level Ea is further away from the energy level Ec of the conduction band. Overall this results in a lower charge carrier mobility in the second layer region 23, as a result of which an electrical series resistance increases and the electro-optical efficiency of the modification 10 is lower than in the case of the semiconductor chip 1, as illustrated in FIGS. 1 to 4.

[0073] FIG. 8 illustrates a further exemplary embodiment of the semiconductor chip 1, with only the second partial region 32 being depicted. In this case, the second partial region 32 is composed of a plurality of alternately arranged partial layers 41 composed of InGaAlP and barrier layers 42 composed of InAlP. That is to say that the second partial region 32 is fashioned as a superlattice. Only four of the partial layers 41 are illustrated by way of example in FIG. 8. Preferably approximately 70 of the partial layers 41 and thus approximately 70 layer pairs or periods of the superlattice are present.

[0074] The partial layers 41 are preferably tensile-strained, in particular relative to a GaAs lattice. A thickness of the partial layers 41 is preferably less than 10 nm. In this configuration, the barrier layers 42 of the superlattice are thicker than the partial layers 41. A quotient of a thickness of the barrier layers 42 and a thickness of the partial layers 41 is in particular between 3 and 5 inclusive.

[0075] As an alternative to relatively thin partial layers 41 and thick barrier layers 42, relatively thick InGaAlP partial layers 41 having a thickness of more than 10 nm can also be present in the construction in FIG. 8. In this case, the partial layers 41 are preferably not, or not significantly, lattice mismatched vis A vis GaAs. Furthermore, in this case, the barrier layers 42 are approximately as thick as the partial layers 41.

[0076] FIGS. 9 and 10 relate to the last-mentioned configuration, that is to say to relatively thick partial layers 41 having a thickness of more than 10 nm, which are unstrained vis àvis GaAs.

[0077] For the rest, the explanations concerning FIGS. 1 to 4 are applicable, mutatis mutandis, to FIGS. 8 to 9, that is to say to the configurations with a partial region 32 which is fashioned as a superlattice and which has thick partial layers 41 in combination with barrier layers 42 having an approximately identical thickness or which has thin partial layers 41 in combination with relatively thick barrier layers 42.

[0078] In the exemplary embodiment in FIG. 11, both the partial layers 41 and the barrier layers 42 are made thin in each case, only the second partial region 32 being illustrated in FIG. 11. With regard to the rest of components of the semiconductor chip 1 in FIG. 11, the explanations concerning FIGS. 1 to 4 are applicable, mutatis mutandis.

[0079] The partial layers 41 and the barrier layers 42 have for example in each case a thickness of between 3 nm and 6 nm inclusive and are thus relatively thin in each case. This results in a miniband with an effective energy level E.sub.mB for the holes; see also FIG. 12. An effective mass of holes in the miniband is less than in thick, bulk p-InGaAlP, and so a higher conductivity is attained. The superlattice having the thin partial layers 41 and barrier layers 42 preferably has between 50 and 200 layer pairs inclusive.

[0080] FIG. 13 illustrates once again the band structure of the layer regions 21, 23 and of the active zone 22, in particular for the case of FIG. 8. The second partial region 32 comprises in particular in the following layers 41, 42: [0081] the superlattice partial layers 41 are composed of In.sub.y(Ga.sub.1-xAl.sub.x).sub.1-yP, doped with Mg or Zn and where 0.49≤y≤0.51 for non-strained partial layers 41 and where 0.3≤y≤0.49 for tensile-strained partial layers, and also where 0.2≤x≤0.5, [0082] the superlattice barrier layers 42 are composed of In.sub.wAl.sub.1-wP, doped with Mg or Zn, wherein 0.49≤w≤0.51 holds true for non-strained barrier layers and 0.51≤x≤0.8 holds true for compressively strained barrier layers.

[0083] Unless indicated otherwise, the components shown in the figures succeed one another preferably in the specified order and in particular directly. Layers not touching one another in the figures are preferably spaced apart from one another. Insofar as lines are depicted parallel to one another, the corresponding areas are preferably likewise aligned parallel to one another. Likewise, unless indicated otherwise, the positions of the depicted components relative to one another are rendered correctly in the figures.

[0084] The invention described here is not restricted by the description on the basis of the exemplary embodiments. Rather, the invention encompasses any novel feature and also any combination of features, which in particular includes any combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.