SEMICONDUCTOR DEVICE HAVING ESD ELEMENT

Abstract

When an ESD element is operated, for the purpose of suppressing heat generation and causing uniform current to flow through all channels of all transistors included in the ESD element, various substrate potentials existing in the transistors and the channels of a multi finger type ESD element are electrically connected via a low resistance substrate, and further, are set to a potential that is different from a Vss potential. In this manner, the current is uniformized and heat generation is suppressed through low voltage operation to improve an ESD tolerance.

Claims

1. A semiconductor device having an ESD element, the ESD element comprising: a semiconductor substrate; a P-well formed on a surface of the semiconductor substrate and having an impurity concentration that is higher than an impurity concentration of the semiconductor substrate; an N-type source and an N-type drain formed on the surface of the semiconductor substrate in the P-well and having an impurity concentration that is higher than the impurity concentration of the semiconductor substrate; a P-type region formed on the surface of the semiconductor substrate so as to be in contact with the N-type source and having an impurity concentration that is higher than the impurity concentration of the semiconductor substrate; a gate insulating film formed on the surface of the semiconductor substrate between the N-type source and the N-type drain; and a gate electrode formed on the gate insulating film, the N-type drain being connected to a pad electrode, the N-type source being connected to a lower power supply potential, and the N-type source and the P-type region being not connected to each other via an electrode.

2. A semiconductor device having an ESD element according to claim 1, wherein the P-type region comprises a plurality of P-type regions, and wherein the plurality of P-type regions are electrically connected to each other via a substance having a resistivity that is equal to or lower than a resistivity of the plurality of P-type regions.

3. A semiconductor device having an ESD element according to claim 1, wherein the gate electrode is electrically connected to the N-type source.

4. A semiconductor device having an ESD element according to claim 1, wherein the gate electrode is electrically connected to the P-type region.

5. A semiconductor device having an ESD element, the ESD element comprising: a semiconductor substrate; a P-well formed on a surface of the semiconductor substrate and having an impurity concentration that is higher than an impurity concentration of the semiconductor substrate; an N-type source and an N-type drain formed on the surface of the semiconductor substrate in the P-well and having an impurity concentration that is higher than the impurity concentration of the semiconductor substrate; an embedded P-type region formed immediately below the N-type source and the N-type drain so as to be in contact with the N-type source and the N-type drain, respectively, and having an impurity concentration that is higher than the impurity concentration of the semiconductor substrate; a gate insulating film formed on the surface of the semiconductor substrate between the N-type source and the N-type drain; and a gate electrode formed on the gate insulating film, the N-type drain being connected to a pad electrode, the N-type source being connected to a lower power supply potential, and the N-type source and the embedded P-type region being not connected to each other via an electrode.

6. A semiconductor device having an ESD element according to claim 5, wherein the embedded P-type region is formed only immediately below the N-type drain.

7. A semiconductor device having an ESD element according to claim 5, wherein the embedded P-type region is formed only immediately below the N-type source.

8. A semiconductor device having an ESD element according to claim 5, wherein the embedded P-type region comprises a plurality of embedded P-type regions, and wherein the plurality of embedded P-type regions are electrically connected to each other via a substance having a resistivity that is lower than a resistance value of the semiconductor substrate.

9. A semiconductor device having an ESD element, the ESD element comprising: a semiconductor substrate; a P-well formed on a surface of the semiconductor substrate and having an impurity concentration that is higher than an impurity concentration of the semiconductor substrate; an N-type source and an N-type drain formed on the surface of the semiconductor substrate in the P-well and having an impurity concentration that is higher than the impurity concentration of the semiconductor substrate; a gate insulating film formed on the surface of the semiconductor substrate between the N-type source and the N-type drain; an integral embedded P-type region spatially continuously formed immediately below the N-type source and the N-type drain so as to be in contact with the N-type source and the N-type drain and having an impurity concentration that is higher than the impurity concentration of the semiconductor substrate; and a gate electrode formed on the gate insulating film, the N-type drain being connected to a pad electrode, the N-type source being connected to a lower power supply potential, and the N-type source and the integral embedded P-type region being not connected to each other via an electrode.

10. A semiconductor device having an ESD element according to claim 5, wherein the gate electrode is electrically connected to the N-type source.

11. A semiconductor device having an ESD element according to claim 5, wherein the gate electrode is electrically connected to the embedded P-type region.

12. A semiconductor device having an ESD element, the ESD element comprising: a semiconductor substrate; a P-well formed on a surface of the semiconductor substrate and having an impurity concentration that is higher than an impurity concentration of the semiconductor substrate; an N-type source and an N-type drain formed on the surface of the semiconductor substrate in the P-well and having an impurity concentration that is higher than the impurity concentration of the semiconductor substrate; and a P-type region formed on the surface of the semiconductor substrate so as to be in contact with the N-type source and having an impurity concentration that is higher than the impurity concentration of the semiconductor substrate, the N-type drain being connected to a pad electrode, the N-type source being connected to a lower power supply potential, and the N-type source and the P-type region being not connected to each other via an electrode.

13. A semiconductor device having an ESD element according to claim 12, wherein the P-type region comprises a plurality of P-type regions, and wherein the plurality of P-type regions are electrically connected to each other via a substance having a resistivity that is equal to or lower than a resistivity of the plurality of P-type regions.

14. A semiconductor device having an ESD element, the ESD element comprising: a semiconductor substrate; a P-well formed on a surface of the semiconductor substrate and having an impurity concentration that is higher than an impurity concentration of the semiconductor substrate; an N-type source and an N-type drain formed on the surface of the semiconductor substrate in the P-well and having an impurity concentration that is higher than the impurity concentration of the semiconductor substrate; and an embedded P-type region formed immediately below the N-type source and the N-type drain so as to be in contact with the N-type source and the N-type drain, respectively, and having an impurity concentration that is higher than the impurity concentration of the semiconductor substrate, the N-type drain being connected to a pad electrode, the N-type source being connected to a lower power supply potential, and the N-type source and the embedded P-type region being not connected to each other via an electrode.

15. A semiconductor device having an ESD element according to claim 14, wherein the embedded P-type region is formed only immediately below the N-type drain.

16. A semiconductor device having an ESD element according to claim 14, wherein the embedded P-type region is formed only immediately below the N-type source.

17. A semiconductor device having an ESD element according to claim 14, wherein the embedded P-type region comprises a plurality of embedded P-type regions, and wherein the plurality of embedded P-type regions are electrically connected to each other via a substance having a resistivity that is lower than a resistance value of the semiconductor substrate.

18. A semiconductor device having an ESD element, the ESD element comprising: a semiconductor substrate; a P-well formed on a surface of the semiconductor substrate and having an impurity concentration that is higher than an impurity concentration of the semiconductor substrate; an N-type source and an N-type drain formed on the surface of the semiconductor substrate in the P-well and having an impurity concentration that is higher than the impurity concentration of the semiconductor substrate; and an integral embedded P-type region spatially continuously formed immediately below the N-type source and the N-type drain so as to be in contact with the N-type source and the N-type drain and having an impurity concentration that is higher than the impurity concentration of the semiconductor substrate, the N-type drain being connected to a pad electrode, the N-type source being connected to a lower power supply potential, and the N-type source and the integral embedded P-type region being not connected to each other via an electrode.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0037] FIG. 1 are illustrations of Embodiment 1 of the present invention, and FIG. 1A is a plan view, FIG. 1B is a sectional view taken along the line D-D′, and FIG. 1C is an equivalent circuit.

[0038] FIG. 2 are illustrations of Embodiment 2 of the present invention, and FIG. 2A is a plan view, FIG. 2B is a sectional view taken along the line E-E′, and FIG. 2C is an equivalent circuit.

[0039] FIG. 3 are illustrations of Embodiment 3 of the present invention, and FIG. 3A is a plan view, FIG. 3B is a sectional view taken along the line F-F′, and FIG. 3C is a sectional view taken along the line G-G′.

[0040] FIG. 4 are illustrations of Embodiment 4 of the present invention, and FIG. 4A is a plan view, FIG. 4B is a sectional view taken along the line H-H′, and FIG. 4C is a sectional view taken along the line I-I′.

[0041] FIG. 5 are illustrations of Embodiment 5 of the present invention, and FIG. 5A is a plan view, FIG. 5B is a sectional view taken along the line J-J′, and FIG. 5C is a sectional view taken along the line K-K′.

[0042] FIG. 6 are illustrations of Embodiment 6 of the present invention, and FIG. 6A is a plan view and FIG. 6B is a sectional view taken along the line L-L′.

[0043] FIG. 7 are illustrations of Embodiment 7 of the present invention, and FIG. 7A is a plan view, FIG. 7B is a sectional view taken along the line M-M′, and FIG. 7C is an equivalent circuit.

[0044] FIG. 8 are illustrations of a related-art ESD element, and FIG. 8A is a plan view, FIG. 8B is a sectional view taken along the line A-A′, FIG. 8C is an equivalent circuit, and FIG. 8D is for showing current-voltage characteristics.

[0045] FIG. 9 are illustrations of a related-art ESD element of Patent Literature 1, and FIG. 9A is a plan view, FIG. 9B is a sectional view taken along the line B-B′, FIG. 9C is an equivalent circuit, and FIG. 9D is for showing current-voltage characteristics.

[0046] FIG. 10 is a plan view when a first P+ for fixing a P-well of the related-art ESD element of Patent Literature 1 is arranged so as to surround transistors.

[0047] FIG. 11 are illustrations of a related-art ESD element for the purpose of uniform current flowing through all transistors and all channels, and FIG. 11A is a plan view, FIG. 11B is a sectional view taken along the line C-C′, FIG. 11C is an equivalent circuit, and FIG. 11D is for showing current-voltage characteristics.

[0048] FIG. 12 are illustrations of Embodiment 8 of the present invention, and FIG. 12A is a plan view, FIG. 12B is a sectional view taken along the line N-N′, and FIG. 12C is a sectional view taken along the line O-O′.

[0049] FIG. 13 are illustrations of Embodiment 9 of the present invention, and FIG. 13A is a plan view, FIG. 13B is a sectional view taken along the line P-P′, and FIG. 13C is a sectional view taken along the line Q-Q′.

DESCRIPTION OF EMBODIMENTS

[0050] Now, embodiments of the present invention are described with reference to the drawings.

Embodiment 1

[0051] FIG. 1 are illustrations of an ESD element of Embodiment 1 of the present invention, and FIG. 1A is a plan view and FIG. 1B is a sectional view taken along the line D-D′. With reference to FIG. 1A, a pad electrode (or a drain electrode connected to the pad electrode) 18 is assumed to be not floating, but connected to a pad via an upper layer electrode.

[0052] NMOS transistors are in a P-well 14 formed in a semiconductor substrate 9. A first P+ region 23 for fixing a P-well for the purpose of fixing a potential is on a surface of the P-well 14 around the NMOS transistors, and is connected to wiring 17 having a Vss potential via contacts 16. Gate electrodes 1 to 6 and N+ sources 11 of the NMOS transistors are connected to a Vss terminal having a lower power supply potential via the wiring 17, and N+ drains 12 are connected to the pad electrode via wiring 18. Second P+ regions 24 for fixing a P-well are formed adjacent to and in contact with the N+ sources 11. A LOCOS oxide film 10 is arranged between an outermost second P+ region 24 for fixing a P-well and the first P+ region 23 for fixing a P-well. A gate insulating film 15 is arranged under each gate electrode. The indication of N+ or P+ is for showing not only a conductivity type of a semiconductor but is also for showing that an impurity concentration of a region indicated with N+ or P+ is higher than that of a region indicated with N or P and is a concentration with which an ohmic contact with metal wiring can be generally formed. A “heavily doped N-type drain” has the same meaning as an “N+ drain”.

[0053] The structure illustrated in FIG. 1 is similar to the related-art ESD element illustrated in FIG. 10 in that all the second P+ regions 24 for fixing a P-well are connected via a second P+ electrode 21 for fixing a P-well, but has a feature in that the second P+ electrode 21 for fixing a P-well is not connected to a Vss electrode 17 having a lower power supply potential via a low resistance metal electrode. With this structure, parasitic resistances of the P-well 14 immediately below all the transistors and channels are the same Rpw11 as illustrated in FIG. 1C, and uniform current flows through all the transistors and channels. This effect is the same as that of the related art illustrated in FIG. 10, and thus, the problem of the structures illustrated in FIG. 8 and FIG. 9 can be avoided. In this case, the second P+ electrode 21 for fixing a P-well is required to be formed of a substance having a resistivity that is equal to or lower than that of the second P+ regions 24 for fixing a P-well, for example, metal. The reason is that, if the second P+ regions 24 for fixing a P-well are connected to each other via a high resistance substance, there is a potential difference among the second P+ regions 24 for fixing a P-well, and current concentration may occur.

[0054] Further, as can be seen from FIG. 1B, Rpw11 depends on a distance from transistors having gate electrodes 1 and 6 to the first P+ region 23 for fixing a P-well. Thus, a relationship of Rpw10<Rpw11 holds, and a breakdown due to heat generation that is a problem of the related art illustrated in FIG. 10 is less liable to occur.

Embodiment 2

[0055] FIG. 2 are illustrations of Embodiment 2 of the present invention, and FIG. 2A is a plan view and FIG. 2B is a sectional view taken along the line E-E′. With reference to FIG. 2A, the pad electrode (or the drain electrode connected to the pad electrode) 18 is assumed to be not floating, but connected to the pad via the upper layer electrode. FIG. 2 are illustrations of an example in which the gate electrodes 1 to 6 of Embodiment 1 illustrated in FIG. 1 are not connected to the Vss electrode 17 but are connected to the second P+ regions 24 for fixing a P-well via an electrode 20 connecting the second P+ for fixing a P-well and the gate electrodes. This applies a potential to the gate electrodes 1 to 6 when static electricity injected from the pad electrode is dissipated, with the result that not only parasitic bipolar current but also channel current flows. Thus, in addition to the effect obtained by Embodiment 1, an ESD tolerance is improved compared with the case of Embodiment 1.

Embodiment 3

[0056] FIG. 3 are illustrations of Embodiment 3 of the present invention, and FIG. 3A is a plan view, FIG. 3B is a sectional view taken along the line F-F′, and FIG. 3C is a sectional view taken along the line G-G′. This structure realizes the function of fixing potentials of regions immediately below the channels of the second P+ region 24 for fixing a P-well adjacent to the N+ sources 11 illustrated in FIG. 1 and FIG. 2, with embedded P+ regions 22 being heavily doped P-type regions that are embedded immediately below the N+ sources 11 and N+ drains 12 so as to be in contact therewith. As illustrated in FIG. 3B and FIG. 3C, the embedded P+ regions 22 immediately below the respective N+ sources 11 and N+ drains 12 are independent of one another, and thus, are electrically connected via the second P+ region 24 for fixing a P-well that lies on an upper side in FIG. 3A and the embedded P+ regions 22 immediately below the second P+ region 24 for fixing a P-well. The second P+ region 24 for fixing a P-well is not connected to the Vss electrode 17 having a lower power supply potential via a low resistance metal electrode. The equivalent circuit is consequently the same as that illustrated in FIG. 10, and the same effect as that of Embodiment 1 can be obtained. Further, the second P+ regions 24 for fixing a P-well adjacent to the N+ sources 11 in Embodiment 1 are embedded in the semiconductor substrate as the embedded P+ regions 22, and thus, the area can be reduced compared with the case of Embodiment 1. Further, through adjustment of an impurity concentration and a depth of the embedded P+ regions 22 immediately below the N+ drains 12, Vhold and Vtrig can be easily adjusted, and thus Vtrig of the ESD element can be finely adjusted and prevented from being equal to or below a withstand voltage of the IC. Wiring and contacts on the N+ drains 12 are omitted in FIG. 3C.

Embodiment 4

[0057] FIG. 4 are illustrations of Embodiment 4 of the present invention, FIG. 4A is a plan view and FIG. 4B is a sectional view taken along the line H-H′, and FIG. 4C is a sectional view taken along the line I-I′. With reference to FIG. 4A, the pad electrode (or the drain electrode connected to the pad electrode) 18 is assumed to be not floating, but connected to the pad via the upper layer electrode. FIG. 4 are illustrations of an example in which the gate electrodes 1 to 6 of Embodiment 3 illustrated in FIG. 3 are not connected to the Vss electrode 17 but are connected to the second P+ regions 24 for fixing a P-well via the electrode 20 connecting the second P+ for fixing a P-well and the gate electrodes. This applies a potential to the gate electrodes 1 to 6 when static electricity injected from the pad electrode is dissipated, with the result that not only parasitic bipolar current but also channel current flows. Thus, in addition to the effect obtained by Embodiment 3, the ESD tolerance is improved compared with the case of Embodiment 3.

[0058] In this case, the electrode 20 connecting the second P+ for fixing a P-well and the gate electrodes is required to be formed of a substance having a resistivity that is equal to or lower than that of the second P+ regions 24 for fixing a P-well, for example, metal. The reason is that, if the second P+'s 24 for fixing a P-well are connected to each other via a high resistance substance, there is a potential difference among the second P+ regions 24 for fixing a P-well, and current concentration may occur.

[0059] Further, the same effect can be obtained even when the embedded P+ regions 22 immediately below the N+ sources 11 and the N+ drains 12 in Embodiments 3 and 4 are immediately below any one of the N+ sources 11 and the N+ drains 12. However, when the embedded P+ regions 22 are arranged immediately below only the N+ sources 11, Vhold and Vtrig cannot be adjusted using the impurity concentration and the depth of the embedded P+ regions 22.

Embodiment 5

[0060] FIG. 5 are illustrations of Embodiment 5 of the present invention, and FIG. 5A is a plan view, FIG. 5B is a sectional view taken along the line J-J′, and FIG. 5C is a sectional view taken along the line K-K′. In the plan view of FIG. 5A, the structure is substantially the same as that of the related art illustrated in FIG. 8, but, as can be seen from the sectional views of FIG. 5B and FIG. 5C, the embedded P+ region 22 exists. Embodiment 5 has a feature in that, differently from the embedded P+ regions 22 immediately below the N+ sources 11 and the N+ drains 12 in Embodiment 3 illustrated in FIG. 3 and Embodiment 4 illustrated in FIG. 4, the embedded P+ region 22 in contact with the N+ sources 11 and the N+ drains 12 exists on an entire surface immediately below the transistors. This structure can obtain the same effect as that of the structure illustrated in FIG. 3. Since the embedded P+ region 22 is not independent and it is not necessary to connect the embedded P+ regions 22 to each other in a different region as described in in the description of Embodiment 3 and Embodiment 4, there is an effect that the area can be further reduced compared with the structure illustrated in FIG. 3. In this embodiment, the embedded P+ region 22 does not have an outlet or the like formed therein, and thus, the embedded P+ region 22 is not connected to the Vss electrode 17 having a lower power supply potential via a low resistance metal electrode.

Embodiment 6

[0061] FIG. 6 are illustrations of Embodiment 6 of the present invention, and FIG. 6A is a plan view and FIG. 6B is a sectional view taken along the line L-L′. With reference to FIG. 6A, the pad electrode (or the drain electrode connected to the pad electrode) 18 is assumed to be not floating, but connected to the pad via the upper layer electrode. FIG. 6 are illustrations of a structure in which the second P+ regions 24 for fixing a P-well that lie on an upper side in FIG. 6A and the embedded P+ region 22 existing immediately therebelow are added to Embodiment 5 illustrated in FIG. 5. The gate electrodes 1 to 6 are not connected to the Vss electrode 17 but are connected to the second P+ regions 24 for fixing a P-well via the electrode 20 connecting the second P+ for fixing a P-well and the gate electrodes. This applies a potential to the gate electrodes 1 to 6 when static electricity injected from the pad electrode is dissipated, with the result that not only parasitic bipolar current but also channel current flows. Accordingly, the same effect as that of Embodiment 5 can be obtained. However, through addition of the second P+ regions 24 for fixing a P-well, the area is increased compared with the case of Embodiment 5.

[0062] In this case, the electrode 20 connecting the second P+ regions 24 for fixing a P-well and the gate electrodes is required to be formed of a substance having a resistivity that is equal to or lower than that of the second P+ regions 24 for fixing a P-well, for example, metal. The reason is that, if the second P+ regions 24 for fixing a P-well are connected to each other via a high resistance substance, there is a potential difference among the second P+ regions 24 for fixing a P-well, and current concentration may occur.

Embodiment 7

[0063] FIG. 7 are illustrations of an ESD element of Embodiment 7 of the present invention, and FIG. 7A is a plan view and FIG. 7B is a sectional view taken along the line M-M′. With reference to FIG. 7A, the pad electrode (or the drain electrode connected to the pad electrode) 18 is assumed to be not floating, but connected to the pad via the upper layer electrode. In this Embodiment 7, the MOS transistors in Embodiment 1 are changed to bipolar transistors, and an effect similar to that of Embodiment 1 can be obtained. In this case, the N+ sources 11 and the N+ drains 12 in FIG. 1 are N+ emitters 26 and N+ collectors 25, respectively, in FIG. 7, with the change from the MOS transistors to the bipolar transistors. Further, the second P+ regions 24 for fixing a P-well in FIG. 1 correspond to bases in FIG. 7, but, for the purpose of unifying terms, the word “base” is not used herein. Similarly to the case of Embodiment 1, the second P+ electrode 21 for fixing a P-well is not connected to the Vss electrode 17 having a lower power supply potential via a low resistance metal electrode.

[0064] This change from the MOS transistors to the bipolar transistors may be also applied to Embodiment 3 and Embodiment 5. Meanwhile, in Embodiment 2, Embodiment 4, and Embodiment 6, only the connection destinations of the gate electrodes in Embodiment 1, Embodiment 3, and Embodiment 5, respectively, are changed. Embodiment 1, Embodiment 3, and Embodiment 5 including the bipolar transistors having no gate electrodes instead of the MOS transistors and Embodiment 2, Embodiment 4, and Embodiment 6 including the bipolar transistors instead of the MOS transistors thereby have the same structure, respectively.

Embodiment 8

[0065] FIG. 12 are illustrations of an ESD protection element in which the MOS transistors in Embodiment 3 described above are changed to bipolar transistors. FIG. 12A is a plan view, FIG. 12B is a sectional view taken along the line N-N′, and FIG. 12C is a sectional view taken along the line O-O′. Similarly to the case of Embodiment 7, the N+ collectors 25 and the N+ emitters 26 are formed, and the embedded P+ regions 22 are formed independently of one another under the N+ collectors 25 and the N+ emitters 26 so as to be in contact therewith, respectively. As can be seen from FIG. 12C, the embedded P+ regions 22 are electrically connected to each other via the second P+ region 24 for fixing a P-well and the embedded P+ regions 22 immediately below the second P+ region 24 for fixing a P-well. The second P+ region 24 for fixing a P-well is not connected to the Vss electrode 17 having a lower power supply potential via a low resistance metal electrode. This ESD protection element is configured to perform protection operation through bipolar operation.

Embodiment 9

[0066] Similarly to the case of Embodiment 8, FIG. 13 are illustrations of an ESD protection element in which the MOS transistors in Embodiment 5 are changed to bipolar transistors. FIG. 13A is a plan view, FIG. 13B is a sectional view taken along the line P-P′, and FIG. 13C is a sectional view taken along the line Q-Q′. Similarly to the case of Embodiment 8, the N+ collectors 25 and the N+ emitters 26 are formed, and the embedded P+ regions 22, which are integral, are continuously formed under the N+ collectors 25 and the N+ emitters 26 so as to be in contact therewith, respectively. As can be seen from FIG. 13C, in this embodiment, the embedded P+ regions 22 do not have an outlet or the like formed therein, and thus, the embedded P+ regions 22 are not connected to the Vss electrode 17 having a lower power supply potential via a low resistance metal electrode. This ESD protection element is configured to perform protection operation through bipolar operation.

[0067] As described above, an essence common in the present invention is that, by electrically connecting, via a low resistance substance, various substrate potentials existing in the respective transistors and in the respective channels of the ESD element, and further, separating the connection from the Vss potential, uniformization of current and suppression of heat generation through low voltage operation are attained to improve the ESD tolerance. This can be applied not only to the MOS type ESD element with the gate electrodes described above but also bipolar type ESD elements without the gate electrodes.

[0068] Further, multi finger type ESD elements are described above, but the present invention can be applied also to single finger type ESD elements, and the same effect can be obtained.

[0069] Further, as a matter of course, it is assumed that the present invention is implemented on a semiconductor substrate. Throughout the embodiments, impurity concentrations of the N+ sources 11, the N+ drains, the P+ region for fixing a P-well, the embedded P+ region, the first P+ region for fixing a P-well, the second P+ region for fixing a P-well are higher than that of the P-well 14, and the impurity concentration of the P-well 14 is higher than that of the semiconductor substrate.

REFERENCE SIGNS LIST

[0070] 1-6 gate electrode [0071] 9 semiconductor substrate [0072] 10 LOCOS oxide film [0073] 11 N+ source [0074] 12 N+ drain [0075] 13 P+ region for fixing a P-well potential [0076] 14 P-well [0077] 15 gate insulating film [0078] 16 contact [0079] 17 Vss electrode [0080] 18 pad electrode [0081] 20 electrode connecting a second P+ region for fixing a P-well and a gate electrode [0082] 21 second P+ electrode for fixing a P-well [0083] 22 embedded P+ region [0084] 23 first P+ region for fixing a P-well [0085] 24 second P+ region for fixing a P-well [0086] 25 N+ collector [0087] 26 N+ emitter [0088] 50 I-V characteristic for transistors having gate electrodes 1 and 6 in FIG. 8 [0089] 51 I-V characteristic for transistors having gate electrodes 2 and 5 in FIG. 8 [0090] 52 I-V characteristic for transistors having gate electrodes 3 and 4 in FIG. 8 [0091] 53 I-V characteristic for a transistor having a gate electrode 1 in FIG. 9 [0092] 54 I-V characteristic for a transistor having a gate electrode 6 in FIG. 9 [0093] 55 I-V characteristic for transistors having gate electrodes 1 to 6 in FIG. 10