BARRIER LAYER REMOVAL METHOD AND SEMICONDUCTOR STRUCTURE FORMING METHOD

Abstract

The present invention provides a barrier layer removal method, wherein the barrier layer includes at least one layer of ruthenium or cobalt, the method comprising: removing the barrier layer including ruthenium or cobalt formed on non-recessed areas of a semiconductor structure by thermal flow etching. The present invention further provides a semiconductor structure forming method, comprising: providing a semiconductor structure which includes a dielectric layer, a hard mask layer formed on the dielectric layer, recessed areas formed on the hard mask layer and the dielectric layer, a barrier layer including at least one layer of ruthenium or cobalt formed on the hard mask layer, sidewalls of the recessed areas and bottoms of the recessed areas, a metal layer formed on the barrier layer and filling the recessed areas; removing the metal layer formed on the non-recessed areas and the metal in the recessed areas, and remaining a certain amount of metal in the recessed areas; removing the barrier layer including ruthenium or cobalt formed on the non-recessed areas, and the hard mask layer by thermal flow etching.

Claims

1. A barrier layer removal method, wherein the barrier layer includes at least one layer of ruthenium or cobalt, the method comprising: removing the barrier layer including ruthenium or cobalt formed on non-recessed areas of a semiconductor structure by thermal flow etching.

2. The method as claimed in claim 1, wherein a chemical gas for thermal flow etching is selected from one or a mixed gas including one of the following: XeF.sub.2, XeF.sub.4, XeF.sub.6.

3. The method as claimed in claim 1, wherein the temperature of thermal flow etching the barrier layer including Ru is 0° C. to 400° C.

4. The method as claimed in claim 3, wherein the temperature of thermal flow etching the barrier layer including Ru is 100° C. to 350° C.

5. The method as claimed in claim 3, wherein the temperature of thermal flow etching the barrier layer including Ru is 50° C. to 120° C.

6. The method as claimed in claim 1, wherein the pressure of thermal flow etching the barrier layer including Ru is 10 m to 20 Torr.

7. The method as claimed in claim 2, wherein the flow rate of chemical gas is 0 to 50 sccm.

8. The method as claimed in claim 1, wherein the temperature of thermal flow etching the barrier layer including Co is 120° C. to 600° C.

9. The method as claimed in claim 8, wherein the temperature of thermal flow etching the barrier layer including Co is 200° C. to 400° C.

10. The method as claimed in claim 1, wherein the barrier layer includes another layer of which material is titanium, titanium nitride, tantalum or tantalum nitride.

11. A semiconductor structure forming method, comprising: providing a semiconductor structure which includes a dielectric layer, a hard mask layer formed on the dielectric layer, recessed areas formed on the hard mask layer and the dielectric layer, a barrier layer including at least one layer of ruthenium or cobalt formed on the hard mask layer, sidewalls of the recessed areas and bottoms of the recessed areas, a metal layer formed on the barrier layer and filling the recessed areas; removing the metal layer formed on the non-recessed areas and the metal in the recessed areas, and remaining a certain amount of metal in the recessed areas; removing the barrier layer including ruthenium or cobalt formed on the non-recessed areas, and the hard mask layer by thermal flow etching.

12. The method as claimed in claim 11, wherein the metal surface in the recessed area is flush with the top surface of the dielectric layer.

13. The method as claimed in claim 11, wherein the metal surface in the recessed area is below the top surface of the dielectric layer.

14. The method as claimed in claim 13, further comprising a step of selectively plating a cap layer on the metal surface in the recessed area.

15. The method as claimed in claim 14, wherein the top surface of the cap layer in the recessed area is flush with the top surface of the dielectric layer.

16. The method as claimed in claim 14, wherein the cap layer chooses the material of cobalt.

17. The method as claimed in claim 14, wherein the step of selectively plating a cap layer on the metal surface in the recessed area is carried out before the step of removing the barrier layer including ruthenium or cobalt formed on the non-recessed areas, and the hard mask layer by thermal flow etching.

18. The method as claimed in claim 14, wherein the step of selectively plating a cap layer on the metal surface in the recessed area is carried out after the step of removing the barrier layer including ruthenium or cobalt formed on the non-recessed areas, and the hard mask layer by thermal flow etching.

19. The method as claimed in claim 11, wherein the barrier layer includes another layer of which material is titanium, titanium nitride, tantalum or tantalum nitride.

20. The method as claimed in claim 11, wherein the metal layer formed on the non-recessed areas and the metal in the recessed area is removed by CMP or electropolishing, or the combination of CMP and electropolishing.

21. The method as claimed in claim 11, wherein the metal layer is a copper layer.

22. The method as claimed in claim 11, wherein a chemical gas for thermal flow etching is selected from one or a mixed gas including one of the following: XeF.sub.2, XeF.sub.4, XeF.sub.6.

23. The method as claimed in claim 11, further comprising treating the surface of the substrate by solution containing HF or gas phase treatment containing HF vapor before removing the barrier layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1-1 to FIG. 1-3 are cross-sectional views illustrating a semiconductor structure forming process according to an exemplary embodiment of the present invention.

[0012] FIG. 2 is a flow chart illustrating a semiconductor structure forming method according to an exemplary embodiment of the present invention.

[0013] FIG. 3-1 to FIG. 3-4 are cross-sectional views illustrating a semiconductor structure forming process according to another exemplary embodiment of the present invention.

[0014] FIG. 4 is a flow chart illustrating a semiconductor structure forming method according to another exemplary embodiment of the present invention.

[0015] FIG. 5-1 to FIG. 5-4 are cross-sectional views illustrating a semiconductor structure forming process according to another exemplary embodiment of the present invention.

[0016] FIG. 6 is a flow chart illustrating a semiconductor structure forming method according to another exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

[0017] The present invention provides a barrier layer removal method, wherein the barrier layer includes at least a layer of ruthenium or cobalt. The barrier layer which includes ruthenium or cobalt and is formed on non-recessed areas of a semiconductor structure is removed by thermal flow etching. Examples that follow will illustrate the barrier layer removal method and a semiconductor structure forming method.

[0018] Please refer to FIG. 1-1 to FIG. 1-3, showing a process of forming a semiconductor structure according to an exemplary embodiment of the present invention. The semiconductor structure includes a substrate 101, such as a wafer. The substrate 101 may already contain IC devices and necessary contacting structures in it which are not shown in the figures. In some applications, an isolation layer 102 is formed on the substrate 101. The isolation layer 102 can be SiCN. A dielectric layer is formed on the isolation layer 102. If there is no isolation layer formed on the substrate, the dielectric layer can be formed on the substrate directly. The dielectric layer may include materials such as SiO.sub.2, SiOC, SiOF, SiLK, BD, BDII, BDIII, etc. Preferably, the dielectric layer selects low-k dielectric material for reducing capacitance between the semiconductor structures in a semiconductor device. According to different structure requirement, the dielectric layer can be composed of two layers or more than two layers. In the embodiment shown in the figures, the dielectric layer includes two layers, a first dielectric layer 103 formed on the isolation layer 102 and a second dielectric layer 104 formed on the first dielectric layer 103. The first dielectric layer 103 can be a low-k dielectric layer. The second dielectric layer 104 can be TEOS. A hard mask layer 105 is deposited on the second dielectric layer 104. The material of the hard mask layer 105 may include titanium nitride, tantalum nitride, tungsten or tungsten nitride. Recessed areas, for example, trenches, vias, etc., are formed on the hard mask layer 105, the second dielectric layer 104, the first dielectric layer 103 and the isolation layer 102 by using existing methods in prior art. A recessed area 108 is shown in the figures as an example.

[0019] Then a barrier layer 106 is deposited on the hard mask layer 105, sidewall of the recessed area 108 and bottom of the recessed area 108. The material of the barrier layer 106 at least includes ruthenium or cobalt for satisfying the requirement of 20 nm or below 20 nm node process. In order to improve the adhesivity between the barrier layer 106 and the hard mask layer 105, the second dielectric layer 104, the first dielectric layer 103, and the isolation layer 102, preferably, the barrier layer 106 includes two layers, a first barrier layer and a second barrier layer. The first barrier layer is formed on the hard mask layer 105, sidewall of the recessed area 108 and bottom of the recessed area 108. The material of the first barrier layer can choose titanium, titanium nitride, tantalum or tantalum nitride. The second barrier layer is formed on the first barrier layer, and the material of the second barrier layer is ruthenium or cobalt. Typically, if the second barrier layer is cobalt, the first barrier layer preferably chooses titanium nitride, and if the second barrier layer is ruthenium, the first barrier layer preferably chooses tantalum nitride.

[0020] A metal layer 107 is formed on the barrier layer 106 and fills the recessed area 108. In some applications, a metal seed layer can be deposited on the barrier layer 106 before depositing the metal layer 107. The metal seed layer may include the same material as the metal layer 107 in order to facilitate the deposition and bonding of the metal layer 107 onto the barrier layer 106. The metal layer 107 fills the recessed area 108 and covers non-recessed areas, as shown in FIG. 1-1. Preferably, the metal layer 107 is a copper layer.

[0021] Referring to FIG. 1-2, remove the metal layer 107 formed on the non-recessed areas and the metal in the recessed area 108, and remain a certain amount of metal in the recessed area 108. In the embodiment, the metal surface in the recessed area 108 is flush with the top surface of the second dielectric layer 104. The metal layer 107 formed on the non-recessed areas and the metal in the recessed area 108 can be removed by CMP or electropolishing, or the combination of CMP and electropolishing. Preferably, most of the metal layer 107 is removed by CMP and remain about 500 to 1000 angstrom of a continual metal layer 107 over the semiconductor structure, and then utilize electropolishing to remove the rest of the metal layer 107 on the non-recessed areas and the metal in the recessed area 108. The within die step height difference will be minimized during the CMP process. A method and apparatus for electropolishing is disclosed in patent application No. PCT/CN2012/075990 which can be cooperated herein by reference.

[0022] Referring to FIG. 1-3, remove the barrier layer 106 formed on the non-recessed areas and the hard mask layer 105 by thermal flow etching. A chemical gas for thermal flow etching can be selected from one or a mixed gas including one of the following: XeF.sub.2, XeF.sub.4, XeF.sub.6. Taking XeF.sub.2 for example, the chemical equation of XeF.sub.2 and ruthenium (Ru) or cobalt (Co) is:

Ru+3XeF.sub.2.fwdarw.RuF.sub.6(volatile)+3Xe(gas)

Co+2XeF.sub.2.fwdarw.CoF.sub.4(volatile)+2Xe(gas)

[0023] The temperature of thermal flow etching the barrier layer 106 including Ru is 0 to 400° C., and 100 to 350° C. is better. The pressure of thermal flow etching the barrier layer 106 including Ru is 10 m Torr to 20 Torr. The flow rate of XeF.sub.2 is 0 to 50 sccm and the flow rate can be controlled by a mass flow controller. Under these conditions, the etch rate of Ru is almost the same with the etch rate of Ta, TaN, Ti or TiN. At 110° C., the etch rate of Ru is about 250 Å/min while the flow rate is 9 sccm. For the condition of thermal flow etching the barrier layer 106 including Co, the temperature is 120 to 600° C., and 200 to 400° C. is preferred. After the barrier layer 106 and the hard mask layer 105 are removed, the metal lines are separated, as shown in FIG. 1-3.

[0024] Before the barrier layer 106 is removed by the thermal flow etching, the surface of the substrate 101 may need to treat by solution which contains HF or by gas phase treatment which contains HF vapor. Because during the metal removal process by electropolishing, a layer of oxide film may be formed on the top surface of the barrier layer 106, and the oxide film may lower the etching efficiency of the barrier layer underneath. Therefore, before the barrier layer 106 is removed by the thermal flow etching, preferably, the surface of the substrate 101 is treated to remove the oxide film.

[0025] Accordingly, referring to FIG. 2, a semiconductor structure forming method according to an exemplary embodiment of the present invention can be summarized as follow:

[0026] Step 201: providing a semiconductor structure which includes a dielectric layer, a hard mask layer formed on the dielectric layer, recessed areas formed on the hard mask layer and the dielectric layer, a barrier layer including at least one layer of ruthenium or cobalt formed on the hard mask layer, sidewalls of the recessed areas and bottoms of the recessed areas, a metal layer formed on the barrier layer and filling the recessed areas;

[0027] Step 203: removing the metal layer formed on the non-recessed areas and the metal in the recessed areas, and remaining a certain amount of metal in the recessed areas;

[0028] Step 205: removing the barrier layer including ruthenium or cobalt formed on the non-recessed areas, and the hard mask layer by thermal flow etching.

[0029] In the embodiment, the metal surface in the recessed area is flush with the top surface of the dielectric layer.

[0030] Please refer to FIG. 3-1 to FIG. 3-4, showing a process of forming a semiconductor structure according to another exemplary embodiment of the present invention. The semiconductor structure includes a substrate 301, such as a wafer. The substrate 301 may already contain IC devices and necessary contacting structures in it which are not shown in the figures. In some applications, an isolation layer 302 is formed on the substrate 301. The isolation layer 302 can be SiCN. A dielectric layer is formed on the isolation layer 302. If there is no isolation layer formed on the substrate, the dielectric layer can be formed on the substrate directly. The dielectric layer may include materials such as SiO.sub.2, SiOC, SiOF, SiLK, BD, BDII, BDIII, etc. Preferably, the dielectric layer selects low-k dielectric material for reducing capacitance between the semiconductor structures in a semiconductor device. According to different structure requirement, the dielectric layer can be composed of two layers or more than two layers. In the embodiment shown in the figures, the dielectric layer includes two layers, a first dielectric layer 303 formed on the isolation layer 302 and a second dielectric layer 304 formed on the first dielectric layer 303. The first dielectric layer 303 can be a low-k dielectric layer. The second dielectric layer 304 can be TEOS. A hard mask layer 305 is deposited on the second dielectric layer 304. The material of the hard mask layer 305 may include titanium nitride, tantalum nitride, tungsten or tungsten nitride. Recessed areas, for example, trenches, vias, etc., are formed on the hard mask layer 305, the second dielectric layer 304, the first dielectric layer 303 and the isolation layer 302 by using existing methods in prior art. A recessed area 308 is shown in the figures as an example.

[0031] Then a barrier layer 306 is deposited on the hard mask layer 305, sidewall of the recessed area 308 and bottom of the recessed area 308. The material of the barrier layer 306 at least includes ruthenium for satisfying the requirement of 20 nm or below 20 nm node process. In order to improve the adhesivity between the barrier layer 306 and the hard mask layer 305, the second dielectric layer 304, the first dielectric layer 303, and the isolation layer 302, preferably, the barrier layer 306 includes two layers, a first barrier layer and a second barrier layer. The first barrier layer is formed on the hard mask layer 305, sidewall of the recessed area 308 and bottom of the recessed area 308. The material of the first barrier layer can choose titanium, titanium nitride, tantalum or tantalum nitride. The second barrier layer is formed on the first barrier layer, and the material of the second barrier layer is ruthenium. Typically, if the second barrier layer is ruthenium, the first barrier layer preferably chooses tantalum nitride.

[0032] A metal layer 307 is formed on the barrier layer 306 and fills the recessed area 308. In some applications, a metal seed layer can be deposited on the barrier layer 306 before depositing the metal layer 307. The metal seed layer may include the same material as the metal layer 307 in order to facilitate the deposition and bonding of the metal layer 307 onto the barrier layer 306. The metal layer 307 fills the recessed area 308 and covers non-recessed areas, as shown in FIG. 3-1. Preferably, the metal layer 307 is a copper layer.

[0033] Referring to FIG. 3-2, remove the metal layer 307 formed on the non-recessed areas and the metal in the recessed area 308, and remain a certain amount of metal in the recessed area 308. In the embodiment, the metal surface in the recessed area 308 is below the top surface of the second dielectric layer 304. The metal layer 307 formed on the non-recessed areas and the metal in the recessed area 308 can be removed by CMP or electropolishing, or the combination of CMP and electropolishing. Preferably, most of the metal layer 307 is removed by CMP and remain about 500 to 1000 angstrom of a continual metal layer 307 over the semiconductor structure, and then utilize electropolishing to remove the rest of the metal layer 307 on the non-recessed areas and the metal in the recessed area 308. The within die step height difference will be minimized during the CMP process. A method and apparatus for electropolishing is disclosed in patent application No. PCT/CN2012/075990 which can be cooperated herein by reference.

[0034] Referring to FIG. 3-3, selectively plate a cap layer 309 on the metal surface in the recessed area 308. Here “selectively plate” means that the cap layer 309 is only plated onto the metal surface in the recessed area 308, but there is no cap layer 309 plated on the surface of the barrier layer 306 formed on the non-recessed area. The top surface of the cap layer 309 in the recessed area 308 is flush with the top surface of the second dielectric layer 304. The cap layer 309 normally chooses the material of cobalt, but other materials can also be used.

[0035] Referring to FIG. 3-4, remove the barrier layer 306 formed on the non-recessed areas and the hard mask layer 305 by thermal flow etching. A chemical gas for thermal flow etching can be selected from one or a mixed gas including one of the following: XeF.sub.2, XeF.sub.4, XeF.sub.6. Taking XeF.sub.2 for example, the temperature of thermal flow etching the barrier layer 306 including Ru is 0 to 400° C., and 50 to 120° C. is better. The pressure of thermal flow etching the barrier layer 306 including Ru is 10 m Torr to 20 Torr. The flow rate of XeF.sub.2 is 0 to 50 sccm and the flow rate can be controlled by a mass flow controller. Under these conditions, the etch rate of Ru is almost the same with the etch rate of Ta, TaN, Ti or TiN. At 110° C., the etch rate of Ru is about 250 Å/min. And when temperature is lower than 120° C., the action between XeF.sub.2 and Co can be neglected.

[0036] Before the barrier layer 306 is removed by the thermal flow etching, the surface of the substrate 301 may need to treat by solution which contains HF or by gas phase treatment which contains HF vapor. Because during the metal removal process by electropolishing, a layer of oxide film may be formed on the top surface of the barrier layer 306, and the oxide film may lower the etching efficiency of the barrier layer underneath. Therefore, before the barrier layer 306 is removed by the thermal flow etching, preferably, the surface of the substrate 301 is treated to remove the oxide film.

[0037] Accordingly, referring to FIG. 4, a semiconductor structure forming method according to another exemplary embodiment of the present invention can be summarized as follow:

[0038] Step 401: providing a semiconductor structure which includes a dielectric layer, a hard mask layer formed on the dielectric layer, recessed areas formed on the hard mask layer and the dielectric layer, a barrier layer including at least one layer of ruthenium formed on the hard mask layer, sidewalls of the recessed areas and bottoms of the recessed areas, a metal layer formed on the barrier layer and filling the recessed areas;

[0039] Step 403: removing the metal layer formed on the non-recessed areas and the metal in the recessed areas, and remaining a certain amount of metal in the recessed areas, wherein the metal surface in the recessed area is below the top surface of the dielectric layer;

[0040] Step 404: selectively plating a cap layer on the metal surface in the recessed area, wherein the top surface of the cap layer in the recessed area is flush with the top surface of the dielectric layer;

[0041] Step 405: removing the barrier layer including ruthenium formed on the non-recessed areas, and the hard mask layer by thermal flow etching.

[0042] Please refer to FIG. 5-1 to FIG. 5-4, showing a process of forming a semiconductor structure according to another exemplary embodiment of the present invention. The semiconductor structure includes a substrate 501, such as a wafer. In some applications, an isolation layer 502 is formed on the substrate 501. The isolation layer 502 can be SiCN. A dielectric layer is formed on the isolation layer 502. If there is no isolation layer formed on the substrate, the dielectric layer can be formed on the substrate directly. The dielectric layer may include materials such as SiO.sub.2, SiOC, SiOF, SiLK, BD, BDII, BDIII, etc. Preferably, the dielectric layer selects low-k dielectric material for reducing capacitance between the semiconductor structures in a semiconductor device. According to different structure requirement, the dielectric layer can be composed of two layers or more than two layers. In the embodiment shown in the figures, the dielectric layer includes two layers, a first dielectric layer 503 formed on the isolation layer 502 and a second dielectric layer 504 formed on the first dielectric layer 503. The first dielectric layer 503 can be a low-k dielectric layer. The second dielectric layer 504 can be TEOS. A hard mask layer 505 is deposited on the second dielectric layer 504. The material of the hard mask layer 505 may include titanium nitride, tantalum nitride, tungsten or tungsten nitride. Recessed areas, for example, trenches, vias, etc., are formed on the hard mask layer 505, the second dielectric layer 504, the first dielectric layer 503 and the isolation layer 502 by using existing methods in prior art. A recessed area 508 is shown in the figures as an example.

[0043] Then a barrier layer 506 is deposited on the hard mask layer 505, sidewall of the recessed area 508 and bottom of the recessed area 508. The material of the barrier layer 506 at least includes ruthenium or cobalt for satisfying the requirement of 20 nm or below 20 nm node process. In order to improve the adhesivity between the barrier layer 506 and the hard mask layer 505, the second dielectric layer 504, the first dielectric layer 503, and the isolation layer 502, preferably, the barrier layer 506 includes two layers, a first barrier layer and a second barrier layer. The first barrier layer is formed on the hard mask layer 505, sidewall of the recessed area 508 and bottom of the recessed area 508. The material of the first barrier layer can choose titanium, titanium nitride, tantalum or tantalum nitride. The second barrier layer is formed on the first barrier layer, and the material of the second barrier layer is ruthenium or cobalt. Typically, if the second barrier layer is cobalt, the first barrier layer preferably chooses titanium nitride, and if the second barrier layer is ruthenium, the first barrier layer preferably chooses tantalum nitride.

[0044] A metal layer 507 is formed on the barrier layer 506 and fills the recessed area 508. In some applications, a metal seed layer can be deposited on the barrier layer 506 before depositing the metal layer 507. The metal seed layer may include the same material as the metal layer 507 in order to facilitate the deposition and bonding of the metal layer 507 onto the barrier layer 506. The metal layer 507 fills the recessed area 508 and covers non-recessed areas, as shown in FIG. 5-1. Preferably, the metal layer 507 is a copper layer.

[0045] Referring to FIG. 5-2, remove the metal layer 507 formed on the non-recessed areas and the metal in the recessed area 508, and remain a certain amount of metal in the recessed area 508. In the embodiment, the metal surface in the recessed area 508 is below the top surface of the second dielectric layer 504. The metal layer 507 formed on the non-recessed areas and the metal in the recessed area 508 can be removed by CMP or electropolishing, or the combination of CMP and electropolishing. Preferably, most of the metal layer 507 is removed by CMP and remain about 500 to 1000 angstrom of a continual metal layer 507 over the semiconductor structure, and then utilize electropolishing to remove the rest of the metal layer 507 on the non-recessed areas and the metal in the recessed area 508. The within die step height difference will be minimized during the CMP process. A method and apparatus for electropolishing is disclosed in patent application No. PCT/CN2012/075990 which can be cooperated herein by reference.

[0046] Remove the barrier layer 506 formed on the non-recessed areas and the hard mask layer 505 by thermal flow etching. During the process of removing the barrier layer 506 and the hard mask layer 505, the barrier layer 506 formed on the sidewall of the recessed area 508 may be etched partially. FIG. 5-3A and FIG. 5-3B show two extremes after the barrier layer 506 formed on the non-recessed areas and the hard mask layer 505 are removed by thermal flow etching. The actual process result is normally between the two extremes.

[0047] Before the barrier layer 506 is removed by the thermal flow etching, the surface of the substrate 501 may need to treat by solution which contains HF or by gas phase treatment which contains HF vapor. Because during the metal removal process by electropolishing, a layer of oxide film may be formed on the top surface of the barrier layer 506, and the oxide film may lower the etching efficiency of the barrier layer underneath. Therefore, before the barrier layer 506 is removed by the thermal flow etching, preferably, the surface of the substrate 501 is treated to remove the oxide film.

[0048] Referring to FIG. 5-4, selectively plate a cap layer 509 on the metal surface in the recessed area 508. The top surface of the cap layer 509 in the recessed area 508 is flush with the top surface of the second dielectric layer 504. The cap layer 509 normally chooses the material of cobalt, but other materials can also be used. Because there is the cap layer 509 plated on the metal surface in the recessed area 508, so the barrier layer 506 can be over etched for ensuring there is no residue of the barrier layer 506 on the non-recessed area.

[0049] Accordingly, referring to FIG. 6, a semiconductor structure forming method according to another exemplary embodiment of the present invention can be summarized as follow:

[0050] Step 601: providing a semiconductor structure which includes a dielectric layer, a hard mask layer formed on the dielectric layer, recessed areas formed on the hard mask layer and the dielectric layer, a barrier layer including at least one layer of ruthenium or cobalt formed on the hard mask layer, sidewalls of the recessed areas and bottoms of the recessed areas, a metal layer formed on the barrier layer and filling the recessed areas;

[0051] Step 603: removing the metal layer formed on the non-recessed areas and the metal in the recessed areas, and remaining a certain amount of metal in the recessed areas, wherein the metal surface in the recessed area is below the top surface of the dielectric layer;

[0052] Step 605: removing the barrier layer including ruthenium or cobalt formed on the non-recessed areas, and the hard mask layer by thermal flow etching;

[0053] Step 606: selectively plating a cap layer on the metal surface in the recessed area, wherein the top surface of the cap layer in the recessed area is flush with the top surface of the dielectric layer.

[0054] The foregoing description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. Such modifications and variations that may be apparent to those skilled in the art are intended to be included within the scope of this invention as defined by the accompanying claims.