GERMANIUM MEDIATED DE-OXIDATION OF SILICON

Abstract

A method for removing a native oxide film from a semiconductor substrate includes repetitively depositing layers of germanium on the native oxide and heating the substrate causing the layer of germanium to form germanium oxide, desorbing a portion of the native oxide film. The process is repeated until the oxide film is removed. A subsequent layer of strontium titanate can be deposited on the semiconductor substrate, over either residual germanium or a deposited germanium layer. The germanium can be converted to silicon germanium oxide by exposing the strontium titanate to oxygen.

Claims

1. (canceled)

2. A method for processing a substrate, the method comprising: positioning the substrate in a deposition chamber, wherein the substrate comprises a top layer of silicon germanium oxide, a middle layer of silicon germanium and a bottom layer of silicon; depositing a layer of germanium on the top layer of silicon germanium oxide; and heating the substrate to a temperature below 850° C., thereby causing at least a portion of the top layer of silicon germanium oxide to react with the layer of germanium to form germanium oxide.

3. The method of claim 2 wherein the middle layer of silicon germanium is graded.

4. The method of claim 2 wherein the temperature is above 650° C.

5. The method of claim 2 wherein the germanium oxide is formed in accordance with the equation Ge+SiO.sub.2.fwdarw.Si+GeO.

6. The method of claim 2 further comprising repeating the depositing the layer of germanium and the heating the substrate until the top layer of silicon germanium oxide is removed from the middle layer of silicon germanium.

7. The method of claim 6 further comprising monitoring the top layer of silicon germanium oxide during removal of the top layer of silicon germanium oxide.

8. The method of claim 7 wherein the monitoring is performed in situ and real-time.

9. The method of claim 6 further comprising depositing an epitaxial layer of strontium titanate on the middle layer of silicon germanium.

10. The method of claim 9 wherein the epitaxial layer of strontium titanate is characterized by a thickness between 0.8 and 60 nanometers.

11. The method of claim 9 further comprising exposing the epitaxial layer of strontium titanate to oxygen, thereby causing the middle layer of silicon germanium to react with the oxygen to form a layer of silicon germanium oxide between the epitaxial layer of strontium titanate and the bottom layer of silicon.

12. The method of claim 11, wherein exposing the epitaxial layer of strontium titanate to oxygen is performed at an oxidizing temperature above 600° C.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1A-1F illustrates simplified cross-sectional views of steps for forming a SrTiO.sub.3 layer on a silicon wafer, according to embodiments of the disclosure;

[0015] FIG. 2 is a method for forming a SrTiO.sub.3 layer on a silicon wafer according to the steps illustrated in FIG. 1;

[0016] FIG. 3A-3D illustrates simplified cross-sectional views of steps for forming a SrTiO.sub.3 layer on a silicon wafer, according to embodiments of the disclosure;

[0017] FIG. 4 is a method for forming a SrTiO.sub.3 layer on a silicon wafer according to the steps illustrated in FIG. 3;

[0018] FIG. 5A-5F illustrates simplified cross-sectional views of steps for forming a SrTiO.sub.3 layer on a silicon wafer that includes a silicon germanium layer, according to embodiments of the disclosure; and

[0019] FIG. 6 is a method for forming a SrTiO.sub.3 layer on a silicon wafer according to the steps illustrated in FIG. 5.

DETAILED DESCRIPTION

[0020] Some embodiments of the present disclosure relate to methods for removal of the native oxide from a silicon wafer using Ge mediated de-oxidation and for the subsequent deposition of an epitaxial layer of SrTiO.sub.3. Some embodiments relate to the formation of an intermediate amorphous Si.sub.1-xGe.sub.xO.sub.2 layer between the silicon and the SrTiO.sub.3. While the present disclosure can be useful for a wide variety of configurations, some embodiments of the disclosure are particularly useful for forming silicon wafers for use in photonic circuits, as described in more detail below.

[0021] For example, in some embodiments a silicon wafer includes a layer of amorphous SiO.sub.2 that must be removed before forming an epitaxial SrTiO.sub.3 layer. A first layer of Ge can be deposited on the amorphous SiO.sub.2 and can react with the SiO.sub.2 when exposed to elevated temperatures in the range of 650-850° C. generating GeO that is volatile and desorbs from the Si wafer. This process can be repeated until the Si wafer is free from SiO.sub.2, however some residual Ge from the process remains on the silicon surface. An epitaxial layer of SrTiO.sub.3 can then be formed on the silicon surface. The wafer can then be exposed to an oxidizing atmosphere to convert the remaining Ge, now disposed between the Si and the SrTiO.sub.3 layer, to amorphous Si.sub.1-xGe.sub.xO.sub.2 which is transparent to certain wavelengths of laser light.

[0022] In another example, after removal of the amorphous SiO.sub.2 from the silicon surface, a graded layer of Si.sub.1-xGe.sub.x can be formed that changes concentration from a low concentration of Ge at the Si wafer interface to a higher concentration of Ge at the top of the graded layer. In some embodiments the graded layer can be formed by depositing a layer of Ge and diffusing the Ge into the surface of the Si wafer. In another embodiment, the graded layer can be formed by co-evaporating both Si and Ge with varying concentrations throughout the epitaxial growth process. A layer of epitaxial SrTiO.sub.3 can then be deposited on the graded layer.

[0023] The graded layer can reduce lattice strain between the Si and the SrTiO.sub.3, as the graded layer has a higher concentration of Si at the Si interface and as such has a relatively close match to the lattice of the Si. Further, the graded layer has a higher concentration of Ge at the SrTiO.sub.3 interface and as such has a relatively close lattice match to the SrTiO.sub.3 layer. Thus the graded layer provides an improved lattice match between the Si and the SrTiO.sub.3 than if the SrTiO.sub.3 were formed directly on the Si. The graded layer can be subsequently oxidized, converting it to amorphous Si.sub.1-xGe.sub.xO.sub.2 which is transparent to certain wavelengths of laser light.

[0024] In another example a Si wafer includes a pregrown epitaxial layer of Si.sub.1-xGe.sub.x that is terminated with a native oxide of SiGeO.sub.2. Ge mediated de-oxidation can be used as described above, where a layer of Ge can be deposited on the SiGeO.sub.2 and exposed to a high temperature to desorb the SiGeO.sub.2 layer. Epitaxial SrTiO.sub.3 can be deposited on the Si.sub.1-xGe.sub.x layer and the wafer can be exposed to an oxidizing atmosphere to transform the intermediate Si.sub.1-xGe.sub.x layer to Si.sub.1-xGe.sub.xO.sub.2.

[0025] In order to better appreciate the features and aspects of removing native oxide layers and forming epitaxial SrTiO.sub.3 layers on silicon wafers according to the present disclosure, further context for the disclosure is provided in the following section by discussing several methods of removing native oxide layers and forming epitaxial SrTiO.sub.3 layers on silicon wafers, according to embodiments of the present disclosure. These embodiments are for example only and other methods can be employed to form one or more layers of a ferroelectric oxide on a photonic wafer.

[0026] FIGS. 1A-1F illustrate simplified cross-sectional views of steps, according to a method 200 described in FIG. 2, for forming a SrTiO.sub.3 layer on a silicon wafer, according embodiments of the disclosure.

[0027] As illustrated in FIG. 1A (step 205 of FIG. 2) a silicon wafer 105 that includes a layer of amorphous SiO.sub.2 110 is provided. In some embodiments silicon wafer 105 can be between 500 microns and 1000 microns thick and can have a single crystal structure.

[0028] As illustrated in FIG. 1B (step 210 of FIG. 2) a layer of Ge 115 is deposited on layer of amorphous SiO.sub.2 110. In some embodiments layer of Ge 115 can be between 0.2 to 5 nanometers thick and can be deposited via evaporation in molecular-beam epitaxy (MBE) chamber or other deposition process.

[0029] As illustrated in FIG. 1C (step 215 of FIG. 2) silicon wafer 105 can be heated to a temperature of 650-850° C. causing layer of Ge 115 to react with layer of amorphous SiO.sub.2 110 according to the reaction, Ge+SiO.sub.2.fwdarw.Si+GeO. In one embodiment the temperature is between 700 and 750° C., and in another embodiment is below 850° C. In further embodiments the temperature is below 800° C., below 750° C., or below 700° C. In yet further embodiments the temperature is below 875° C., below 900° C. or below 925° C. The resulting GeO is volatile causing layer of SiO.sub.2 110 to be removed from the top surface of silicon wafer 105.

[0030] As illustrated in FIG. 1D (step 220 of FIG. 2) the Ge deposition and subsequent reaction with SiO.sub.2 and desorption of GeO can be repeated until there is no SiO.sub.2 remaining on the silicon. In some embodiments in situ real time monitoring of the SiO.sub.2 remaining on the silicon surface can be used to determine if all of the SiO.sub.2 has been removed and whether another Ge deposition and desorption process is needed. After the last desorption process is completed, in some embodiments residual Ge 120 remains on the surface of silicon wafer 105 and may be randomly distributed across the silicon surface.

[0031] As illustrated in FIG. 1E (step 225 of FIG. 2) a layer of epitaxial SrTiO.sub.3 125 is deposited on the surface of silicon wafer 105. In some embodiments layer of SrTiO.sub.3 125 is between 0.8 nanometers and 60 nanometers thick and can be deposited using MBE. In various embodiments other thicknesses can be used. In some embodiments a Ge effusion cell can be located in a MBE tool that combines the de-oxidation and SrTiO.sub.3 growth in the same tool to reduce cost and to reduce the likelihood of wafer contamination. In further embodiments, epitaxial BaTiO.sub.3 can be deposited instead of SrTiO.sub.3.

[0032] As illustrated in FIG. 1F (step 230 of FIG. 2) silicon wafer 105 is exposed to molecular oxygen, atomic oxygen, or ozone at a temperature above 600° C. such that the oxygen permeates SrTiO.sub.3 layer 125 and oxidizes residual Ge 120 that was randomly distributed across the silicon surface. This converts residual Ge 120 to amorphous Si.sub.1-xGe.sub.xO.sub.2130 which is non-uniformly distributed both horizontally across silicon wafer 105 and vertically within the amorphous Si.sub.1-xGe.sub.xO.sub.2 layer, based on the location and concentration of the residual Ge that was randomly distributed across the silicon surface. The composition of Si.sub.1-xGe.sub.xO.sub.2 layer 130 can also vary due to inter-diffusion of the Si.sub.1-xGe.sub.xO.sub.2 and the silicon. The resulting Si.sub.1-xGe.sub.xO.sub.2 layer 130 is transparent at certain wavelengths that may be suitable for use in lasers, including 1550 nanometers.

[0033] In other embodiments residual Ge 120 that is randomly distributed across the silicon surface as shown in FIG. 1E can be oxidized by other species such as, but not limited to, wet oxygen, oxygen plasma and ozone. In further embodiments one or more post oxidation treatments can be employed to improve the Si.sub.1-xGe.sub.xO.sub.2 quality and interfaces, as needed.

[0034] In some embodiments a ferroelectric oxide such as, but not limited to, BaTiO.sub.3, (Ba,Sr)TiO.sub.3 (BST), (Pb(Zr, Ti)O.sub.3 (PZT), (Pb, La)(Zr, Ti)O.sub.3 (PLZT), (Sr, Ba)Nb.sub.2O.sub.6 (SBN) or LiNbO.sub.3 can be grown on the SrTiO.sub.3 layer using myriad deposition techniques, including but not limited to, MBE, CVD, PVD, PLD or sol gel. The resulting stack, ferroelectric oxide/SrTiO.sub.3/Si.sub.1-xGe.sub.xO.sub.2/Si can be transparent to certain wavelengths of light, including 1550 nanometers, making the structure useful, for example, for optical switches and waveguides. In yet further embodiments, the aforementioned post oxidation process can be employed after a ferroelectric layer is grown on the SrTiO.sub.3/Si.sub.1-xGe.sub.xO.sub.2/Si stack.

[0035] It will be appreciated that process 200 is illustrative and that variations and modifications are possible. Steps described as sequential may be executed in parallel, order of steps may be varied, and steps may be modified, combined, added or omitted. As would be appreciated by one of skill in the art the term “oxide” as used herein can refer to any permutation of an oxide including but not limited to monoxide, dioxide or trixoide.

[0036] FIGS. 3A-3D illustrate simplified cross-sectional views of steps, according to a method 400 described in FIG. 4, for forming a SrTiO.sub.3 layer on a silicon wafer, according embodiments of the disclosure. As shown in FIG. 4, method 400 uses a similar process as method 200, however before step 225 in method 200 in which the layer of SrTiO.sub.3 is deposited, in method 400 a layer of Ge is deposited in step 405 to create a graded layer. The graded layer changes composition such that at the silicon surface the lattice has a higher percentage of silicon and has therefore closely matches the lattice of the silicon wafer and transitions to a higher percentage of Ge at the top of the layer and therefore closely matches the lattice of the subsequent SrTiO.sub.3 layer, as described in more detail below.

[0037] As shown in FIG. 4, method 400 uses the same steps 205-220 as described in FIG. 2 to form a wafer that is free from amorphous SiO.sub.2 and has residual Ge randomly scattered across silicon surface 300. Therefore, FIG. 3A shows a silicon wafer 105 that has residual Ge 120 randomly scattered across silicon surface 300 which results after performing steps 205-220 of FIG. 4.

[0038] As illustrated in FIG. 3B (step 405 of FIG. 4) an epitaxial layer of Ge 305 is grown on surface 300 of silicon wafer 105. In some embodiments layer of Ge 305 is between 5 to 30 nanometers thick. In some embodiments, layer of Ge 305 can be converted to a graded layer that changes from a low concentration of Ge at silicon surface 300 to a high concentration of Ge at top surface 310 of the Ge layer. In various embodiments the conversion to a graded layer is performed by diffusing Ge layer 305 and silicon wafer 105 together by exposing the wafer to a temperature between 600 and 900° C. After the diffusion process a graded Si.sub.1-xGe.sub.x layer is formed having a Ge concentration that varies from 0 atomic percent Ge within the bulk silicon to 100 atomic percent Ge at top surface 310 of the graded Si.sub.1-xGe.sub.x layer. In other embodiments, the graded layer can vary from 0 atomic percent Ge within the bulk silicon to between 30% to 40% (x from 0.3 to 0.4) atomic percent Ge at top surface 310 of the graded Si.sub.1-xGe.sub.x layer. One of skill in the art with the benefit of this disclosure would appreciate that other concentration gradients can be formed.

[0039] In further embodiments, instead of forming a graded Ge and Si layer by diffusing the Ge layer into the silicon, the graded Si.sub.1-xGe.sub.x layer can be formed on the silicon via co-evaporation of Ge and Si using Ge and Si effusion cells. During co-evaporation, the Si:Ge ratio can be adjusted as growth proceeds by changing the flux temperatures of each of the Si and Ge effusion cells.

[0040] In some embodiments the graded Si.sub.1-xGe.sub.x layer has a larger lattice constant than Si (40 percent Ge at Si.sub.1-xGe.sub.x surface resulting in approximately a 100 percent improvement in lattice match to the SrTiO.sub.3 layer), leading to a high quality SrTiO.sub.3 layer that is subsequently formed on the graded layer, as described below.

[0041] As illustrated in FIG. 3C (step 410 of FIG. 4) an epitaxial layer of SrTiO.sub.3 320 can be subsequently deposited on graded Ge layer 315. In some embodiments layer of SrTiO.sub.3 320 is between 0.8 to 60 nanometers thick and can be deposited using MBE. In other embodiments, epitaxial BaTiO.sub.3 can be grown directly on Si.sub.1-xGe.sub.x layer 315 using MBE.

[0042] As illustrated in FIG. 3D (step 415 of FIG. 4) the wafer is exposed to molecular oxygen, atomic oxygen, or ozone at a temperature above 600° C. such that the oxygen permeates SrTiO.sub.3 layer 320 and oxidizes graded Si.sub.1-xGe.sub.x layer 315 (see FIG. 3C), forming a Si.sub.1-xGe.sub.xO.sub.2 layer 325 that is transparent to certain wavelengths of light, including 1550 nanometers. Therefore the entire stack can be useful, for example, for optical switches and waveguides. As described above with regard to FIGS. 1A-1D and method 200 in FIG. 2, in some embodiments one or more alternative oxidation processes can be used, different ferroelectric oxides can be deposited on the graded layer and optional post oxidation processes can also be used.

[0043] It will be appreciated that process 400 is illustrative and that variations and modifications are possible. Steps described as sequential may be executed in parallel, order of steps may be varied, and steps may be modified, combined, added or omitted.

[0044] FIGS. 5A-5F illustrate simplified cross-sectional views of steps, according to a method 600 described in FIG. 6, for forming a SrTiO.sub.3 layer on a silicon wafer, according embodiments of the disclosure. As shown in FIG. 6, method 600 starts with a silicon wafer 505 having a SiGe layer 510 terminated with a SiGeO.sub.2 surface layer 515 that is removed before a layer of SrTiO.sub.3 is deposited, as described in more detail below.

[0045] As illustrated in FIG. 5A (step 605 of FIG. 6) a silicon wafer 505 includes an epitaxial Si.sub.1-xGe.sub.x layer 510 terminated with a native oxide layer of amorphous SiGeO.sub.2 515. In various embodiments Si.sub.1-xGe.sub.x layer 510 can be graded (e.g., can change concentration vertically within the layer as described in previous embodiments herein) while in other embodiments the Si.sub.1-xGe.sub.x layer can be of uniform concentration. In some embodiments silicon wafer 505 can be between 500 microns and 1000 microns thick and can have a single crystal structure.

[0046] As illustrated in FIG. 5B (step 610 of FIG. 6) a layer of Ge 520 is deposited on SiGeO.sub.2 layer 515. In some embodiments layer of Ge 520 can be between 0.2 to 5 nanometers thick and can be deposited via an evaporation or other deposition process.

[0047] As illustrated in FIG. 5C (step 615 of FIG. 6) the wafer can be heated to a temperature >650° C. causing layer of Ge 520 to react with layer of SiGeO.sub.2 515 according to the reaction, Ge+SiO.sub.2.fwdarw.Si+GeO. In some embodiments the temperature may be different as described in step 215 of FIG. 2. The resulting GeO is volatile causing at least a portion of layer of SiGeO.sub.2 515 to be desorbed from the surface of silicon wafer 505.

[0048] As illustrated in FIG. 5D (step 620 of FIG. 6) the Ge deposition, subsequent reaction with SiO.sub.2 and desorption of GeO can be repeated until there is no SiGeO.sub.2 remaining on the wafer. In some embodiments in situ real time monitoring of the SiGeO.sub.2 remaining on the wafer surface can be used to determine if all of the SiGeO.sub.2 has been removed and whether additional Ge deposition and desorption processes are needed. After the last desorption process is completed, the wafer has an oxide free top surface 520 of layer of Si.sub.1-xGe.sub.x 510.

[0049] As illustrated in FIG. 5E (step 625 of FIG. 6) a layer of epitaxial SrTiO.sub.3 525 is deposited on layer of Si.sub.1-xGe.sub.x 510. In some embodiments layer of SrTiO.sub.3 525 is between 0.8 and 60 nanometers thick and can be deposited using MBE or another suitable deposition process.

[0050] As illustrated in FIG. 5F (step 630 of FIG. 6) the wafer is exposed to molecular oxygen, atomic oxygen, or ozone at a temperature above 600° C. such that the oxygen permeates layer of SrTiO.sub.3 525 and oxidizes the underlying layer of Si.sub.1-xGe.sub.x 510. The oxygen converts layer of Si.sub.1-xGe.sub.x 510 to a layer of Si.sub.1-xGe.sub.xO.sub.2 530 which is transparent at certain wavelengths that may be suitable for use in lasers, including 1550 nanometers. As described above with regard to FIGS. 1A-D and method 200, in some embodiments one or more alternative oxidation processes can be used, different ferroelectric oxides can be deposited on layer of Si.sub.1-xGe.sub.x 510, and alternative post oxidation processes can also be used.

[0051] It will be appreciated that process 600 is illustrative and that variations and modifications are possible. Steps described as sequential may be executed in parallel, order of steps may be varied, and steps may be modified, combined, added or omitted.

[0052] In the foregoing specification, embodiments of the disclosure have been described with reference to numerous specific details that can vary from implementation to implementation. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. The sole and exclusive indicator of the scope of the disclosure, and what is intended by the applicants to be the scope of the disclosure, is the literal and equivalent scope of the set of claims that issue from this application, in the specific form in which such claims issue, including any subsequent correction. The specific details of particular embodiments can be combined in any suitable manner without departing from the spirit and scope of embodiments of the disclosure.

[0053] Additionally, spatially relative terms, such as “bottom or “top” and the like can be used to describe an element and/or feature's relationship to another element(s) and/or feature(s) as, for example, illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and/or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as a “bottom” surface can then be oriented “above” other elements or features. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.