IR DETECTOR ARRAY DEVICE

Abstract

We disclose herein a thermal IR detector array device comprising a dielectric membrane, supported by a substrate, the membrane having an array of IR detectors, where the array size is at least 3 by 3 or larger, and there are tracks embedded within the membrane layers to separate each element of the array, the tracks also acting as heatsinks and/or cold junction regions.

Claims

1. An infra-red (IR) detector array device comprising: a two dimensional array of a plurality of IR detectors; a dielectric region formed on a semiconductor substrate which comprises an etched portion; a dielectric membrane formed within the dielectric region, the dielectric membrane being on top of the etched portion of the substrate; and a plurality of separator regions formed within the dielectric membrane; wherein at least some of the plurality of IR detectors are formed on or within the dielectric membrane, and wherein said at least some of the plurality of IR detectors are separated from one another by at least some of said plurality of separator regions.

2. A device according to claim 1, wherein the separator regions comprise at least one layer which is thermally more conductive than said dielectric membrane.

3. A device according to claim 1, wherein the two dimensional array comprises at least a 3 by 3 array.

4. A device according to claim 1, wherein the separator regions are two dimensionally formed within the dielectric membrane.

5. A device according to claim 1, wherein the separator regions comprise at least two first separator regions extending in a first direction and at least two second separator regions extending in a second direction transverse to the first direction, the second separator regions intersecting the first separator regions.

6. A device according to claim 5, wherein said at least some of the plurality of IR detectors are thermally separated from one another by said at least two first separator regions and by said at least two second separator regions.

7. A device according to claim 5, wherein two adjacent IR detectors are separated from one another by the first and/or second separator regions.

8. A device according to claim 5, wherein some of said at least of some of the IR detectors are not separated from one another by the first and second separator regions.

9. A device according to claim 1, wherein the separator regions each comprise at least one separator layer.

10. A device according to claim 9, wherein said at least one separator layer comprises at least one layer of metal, polysilicon and/or single crystal silicon.

11. A device according to claim 9, wherein said at least one separator layer comprises at least one layer of interconnect material to connect the IR detectors within the array of the IR detectors.

12. A device according to claim 1, wherein each IR detector forms a pixel of the device.

13. A device according to claim 12, wherein the separator regions each provide thermal isolation between each pixel of the device.

14. A device according to claim 1, wherein each separator region is a heat sink region.

15. A device according to claim 1, wherein the IR detectors comprise any one or more of a thermopile, a resistor, transistor and a diode.

16. A device according to claim 1, wherein each IR detector comprises a thermopile.

17. A device according to claim 16, wherein each thermocouple within the thermopile comprises at least first and second dissimilar materials.

18. A device according to claim 16, wherein each thermocouple further comprises a first thermal junction, and a connection to an adjacent thermocouple forms a second thermal junction, the first thermal junction being a hot junction and the second thermal junction being a cold junction.

19. A device according to claim 18, wherein the hot junction is located inside the pixel and the cold junction is located on the separator region, or outside the dielectric membrane.

20. A device according to claim 17, wherein at least one of the first and second materials comprises metal comprising aluminium, copper, tungsten, titanium or combination of these materials.

21. A device according to claim 17, wherein at least one of the first and second materials comprises N+ or P+ doped polysilicon, or vanadium oxide or tungsten silicide, or N+ or P+ doped single crystal silicon.

22. A device according to claim 1, wherein each IR detector comprises at least one diode, wherein said at least one diode is located in the centre of the pixel, wherein said at least one diode comprises a material comprising polysilicon or single crystal silicon.

23. A device according to claim 22, wherein each detector further comprises a reference diode coupled within the separator regions.

24. A device according to claim 1, wherein each IR detector comprises at least one transistor, wherein said at least one transistor is located in the centre of the pixel, wherein said at least one transistor comprises a material comprising single crystal silicon.

25. A device according to claim 1, wherein each IR detector comprises at least one resistor, wherein said at least one resistor is located in the centre of the pixel.

26. A device according to claim 25, wherein said at least one resistor comprises a material comprising: metal comprising aluminium, copper, tungsten, titanium, and/or platinum; n or p type polysilicon; and/or n or p type single crystal silicon.

27. A device according to claim 25, wherein each detector further comprises a reference resistor located within the separator regions.

28. A device according to claim 1, wherein each IR detector comprises a thermopile in which Seeback effect and resistance change effect are used to determine IR radiation.

29. A device according to claim 1, wherein each IR detector comprises a thermopile coupled with a reference diode located at the separator regions to determine a cold junction temperature estimation which is used to determine an absolute hot junction temperature.

30. A device according to claim 1, wherein the dielectric membrane comprises: a membrane cavity comprising vertical side walls or sloping side walls; one or more dielectric layers comprising silicon dioxide and/or silicon nitride; one or more layers of spin on glass, and a passivation layer over the one or more dielectric layers.

31. A device according to claim 1, wherein the dielectric membrane is formed by any one of: back-etching using Deep Reactive Ion Etching (DRIE) of the substrate, and using anisotropic etching such as Potassium Hydroxide (KOH) or TetraMethyl Ammonium Hydroxide (TMAH).

32. A device according to claim 1, wherein the dielectric membrane is formed by a front-side etch to result in a suspended membrane structure, supported by at least two beams.

33. A device according to claim 1, wherein the substrate comprises any one of: silicon; silicon on insulator; silicon carbide; gallium arsenide; gallium nitride; and/or a combination of silicon carbide, gallium arsenide, gallium nitride with silicon.

34. A device according to claim 1, wherein the device is fabricated using a CMOS-usable metal selected from a group comprising tungsten, copper, aluminium, titanium, and molybdenum.

35. A device according to claim 1, wherein the IR detectors and the separator regions are formed using a CMOS-usable material selected from a group comprising Silicon, polysilicon and silicides.

36. A device according to claim 1, wherein the device is fabricated using a non-CMOS material.

37. A device according to claim 12, further comprising holes on each or some of the pixels.

38. A device according to claim 1, further comprising circuitry integrated on the same chip, wherein the circuitry comprise any one of switches, multiplexer, decoder, filter, amplifier, analogue to digital converter, and/or other circuitry.

39. A device according to claim 38, wherein the circuitry is placed outside the dielectric membrane area.

40. A device according to claim 1, further comprising pixel addressing circuitry on or within the dielectric membrane.

41. A device according to claim 40, where the pixel addressing circuitry comprises diodes made in polysilicon or single crystal silicon, and comprises a reference diode and/or a detector within the separator region.

42. A device according to claim 1, further comprising pixel circuitry integrated on the membrane using a silicon on insulator (SOI) technology, wherein the circuitry comprises any one of a MOSFET, a buffer and an amplifier for each IR detector of the device.

43. A device according to claim 1, wherein the separator regions within the dielectric membrane extend at least partly over the etched substrate.

44. A device according to claim 1, further comprising at least one plasmonic structure on at least some of the IR detectors.

45. A device according to claim 44, wherein said at least one plasmonic structure comprises metal comprising any one of tungsten, aluminium, copper, titanium, molybdenum, gold, platinum, or comprising silicides such as magnesium silicide or tungsten silicide, or polysilicon, single crystal silicon.

46. A device according to claim 44, wherein said at least one plasmonic structure comprises a structure repeated periodically in a lateral direction forming a repeat pattern, wherein the repeat pattern comprises a hexagonal or square shape.

47. A device according to claim 44, wherein said at least one plasmonic structure comprises a circle, ellipse, rectangular, trapezoid or a combination of different shapes, or as a pattern of holes of one or more shapes within a layer.

48. A device according to claim 44, wherein said at least one plasmonic structure on each IR detector comprises an identical shape or a different shape.

49. A device according to claim 1, wherein the device is packaged using one or more of: a metal transistor output (TO) type package; a ceramic, metal or plastic surface mount package; IR filters; a reflector; a flip-chip method; a chip or wafer level package; a lens; a printed circuity board (PCB).

50. A device according to claim 49, wherein the package is hermetically or semi-hermetically sealed with air, dry air, argon, nitrogen, xenon or any other noble gas; and/or the device is packaged in vacuum.

51. A device according to claim 1, further comprising an IR emitter formed on the same chip.

52. A device according to claim 1, further comprising a coating layer formed on top or back of the dielectric membrane, wherein the coating layer comprises carbon-black, polymer or metal black.

53. A device according to claim 11, wherein the size of each pixel is in a range from about 2 μm by 2 μm to about 600 μm by 600 μm.

54. A device according to claim 53, wherein the size of each pixel within the array is different from one another.

55. A device according to claim 2, further comprising further separator regions formed on top and/or below the dielectric membrane.

56. An infra-red (IR) detector array assembly comprising: a plurality of IR detector array devices according to claim 1, wherein said plurality of array devices are formed on the same chip.

57. A method of manufacturing an infra-red (IR) detector array device, the method comprising: forming a semiconductor substrate; depositing one or more layers of polysilicon and/or metals and dielectric layers to form a two dimensional array of IR detectors and to form a plurality of separator regions; bulk etching the semiconductor substrate to form a dielectric membrane, wherein at least some of the plurality of IR detectors are formed on or within the dielectric membrane, and wherein said at least some of the plurality of IR detectors are separated from one another by at least some of said plurality of separator regions.

58. A method according to claim 57, wherein the separator regions comprise at least one layer which is thermally more conductive than said dielectric membrane.

59. A method according to claim 57, wherein the semiconductor substrate comprises a plain substrate comprising silicon, or a layered substrate comprising silicon on insulator (SOI) layers.

Description

BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0071] Some preferred embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings, in which:

[0072] FIG. 1 shows a schematic top view of a dielectric membrane with separations;

[0073] FIG. 2 shows a schematic top-view a thermopile structure;

[0074] FIG. 3 shows the schematic top-view of an array of thermopile based IR detectors all on the same membrane with separations;

[0075] FIG. 4 shows the schematic top-view of an array of thermopile based IR detectors all on the same membrane with separations, and also having the separating material at the border of the membrane;

[0076] FIG. 5 shows the schematic top-view of an array of diode based IR detectors all on the same membrane with separations;

[0077] FIG. 6 shows the schematic cross-section of an array of thermopile based IR detectors, with metal embedded within the membrane acting as a separation;

[0078] FIG. 7 shows the schematic cross-section of an array of thermopile based IR detectors, with a metal embedded within the membrane acting as a separation, where the membrane trench has sloping side-walls;

[0079] FIG. 8 shows an example pattern arrangement of a plasmonic type structure that can be used to improve the absorption at certain wavelengths;

[0080] FIG. 9 shows the schematic top-view of an array of thermopile based IR detectors all on the same membrane with separations, and having a patterned layer on each detector to improve the absorbance;

[0081] FIG. 10 shows the schematic cross-section of an array of thermopile based IR detectors, with metal embedded within the membrane acting as a separation, and having a patterned layer above the detector to improve absorbance;

[0082] FIG. 11 shows the schematic cross-section of an array of thermopile based IR detectors, with metal embedded within the membrane acting as a separation, with circuitry on the same chip;

[0083] FIGS. 12-15 show different circuit diagrams for addressing the pixels within the array, and

[0084] FIG. 16 illustrates an exemplary flow diagram outlining the manufacturing method of the IR detector array device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0085] FIG. 1 shows a schematic top-view of a chip 1, with a membrane 2 having separations 3 within it. The separations or separator regions 3 are made from material embedded within the membrane layers and may comprise metal, silicon or polysilicon. The membrane is a dielectric membrane and may comprise one or more layers of silicon dioxide and/or silicon nitride. The separations can also act to define each pixel in the array.

[0086] FIG. 2 shows a schematic top-view of a thermopile comprising two different materials 4 and 5. The materials can be metal, or doped polysilicon or doped single crystal silicon.

[0087] FIG. 3 shows a schematic top-view of an IR detector array based on thermopiles, with the whole array on a single membrane 2. This combines structures from FIGS. 1 and 2. Each IR detector element is separated by a material 3 embedded within the membrane, which acts as a heat sink and cold junction area. The separation 3 allows isolation between each pixel. For the pixels on the edge of the membrane, some of the thermopile cold junctions are on the substrate. The two different materials 4 and 5 form two types of junctions: the hot junctions are formed within the pixel area, while the cold junctions are formed on the separator region, or on the substrate (for pixels on the edge of the membrane). The temperature difference between the hot and cold junctions allows the IR detection.

[0088] As can be seen, the middle four pixels use the separator region to form the cold junction, and the cold junction is formed on the membrane, not the substrate. This reduces the need for more membranes, and hence results in smaller chip area and lower cost. This is applicable for any two dimensional array of 3×3 or larger size where there is at least one pixel without direct contact to the substrate.

[0089] FIG. 4 shows a schematic top-view of an IR detector array based on thermopiles, with the whole array on a single membrane 2, each pixel separated by a material 3 embedded within the membrane. Additionally, this separation material is also at the edge of the substrate—to make the whole structure a bit more symmetrical.

[0090] FIG. 5 shows a schematic top-view of an IR detector array based on diodes, with the whole array on a single membrane 2. Each pixel comprises a diode 6, and tracks 7 which are used to electrically connect the diode. Each pixel is separated by use of a separator 3 embedded within the membrane. The diode can be made of polysilicon or single crystal silicon.

[0091] FIG. 6 shows the schematic cross-section of an IR detector array based on thermopile with the whole array on a single membrane. The membrane is supported on an etched substrate 8, and comprises dielectric layers 9 and may comprise one or more layers of silicon dioxide and/or silicon nitride. The thermopiles comprise p-doped silicon 4, and n-doped silicon 5, and a metal 10 is used to form a junction between them. Metal layers 3 are used to form a first separator region between the thermopiles and further metal layers 3′ are used to form a second separator region between further thermopiles. This separation area also acts as a heat sink and/or cold junction area.

[0092] The thermopiles materials can comprise many other configurations, for example, n-doped silicon and metal, or p-doped silicon and metal. The silicon for the thermopiles can be polysilicon or single crystal silicon. The separation 3, while made of metal in this figure, can also be made from single crystal silicon or polysilicon, or may comprise metal, polysilicon and/or single crystal silicon. The substrate in this example is etched by Deep Reactive Ion Etching (DRIE) which results in vertical sidewalls.

[0093] FIG. 7 shows a thermopile based IR detector array on a single membrane, where the substrate has been etched by anisotropic method such as KOH or TMAH resulting in sloping sidewalls.

[0094] FIG. 8 shows a plasmonic patterning on metal. The pattern comprises a shape repeated periodically in a hexagonal repeat pattern. Using this patterning within an IR detector can improve the absorbance of the detector. The pattern can alternately be a square repeat pattern. Alternately, the shape being repeated can be a rectangle, ellipse, trapezoid, star or any other shape.

[0095] FIG. 9 shows the schematic top-view of a thermopile based IR detector array with plasmonic structures 11 on each detector. The figure shows identical plasmonic structures on each array. However, the plasmonic structures can be different on each pixel as well. Additionally not all the pixels may have the plasmonic structures.

[0096] FIG. 10 shows the schematic cross-section on a thermopile based IR detector array, with all the detectors on the same membrane, where there are plasmonic structures 11 above the thermopiles.

[0097] FIG. 11 shows a thermopile based IR detector array where there is circuitry on the same chip, outside the membrane area. As an example, a MOSFET 13 is shown, which comprises implant regions 12, a polysilicon gate and interconnect metal.

[0098] FIG. 12 shows an example circuit diagram. Each pixel comprise a MOSFET switch 15 and a detector 14 which can be a thermopile or a resistor. A decoder circuit selects the columns by turning the MOSFET on, while the multiplexer selects between rows. Preferably, the design is made in an SOI process to fabricate the MOSFETs on the membrane.

[0099] FIG. 13 shows a circuit diagram, where diodes 16 are used to address each pixel. The column to be selected has to be set to a low voltage, and a multiplexing circuit can be used to select the row. The diodes can be made from either single crystal silicon or polysilicon.

[0100] FIG. 14 shows a circuit diagram where diodes are used to address each pixel, where each pixel also has a reference diode 18 and a reference thermopile/resistor 17. These can be placed within the cold junction area of the membrane. The reference elements help to improve the signal for each detector.

[0101] FIG. 15 shows a circuit diagram where the IR detector is based on diodes 19. In this embodiment, each pixel also has a reference diode 20 within the cold junction area, and these can also be addressed by a column decoder and a row multiplexer circuit.

[0102] FIG. 16 illustrates an exemplary flow diagram outlining the manufacturing method of the IR detector array device.

[0103] The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘above’, ‘overlap’, ‘under’, ‘lateral’, etc. are made with reference to conceptual illustrations of an apparatus, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a device when in an orientation as shown in the accompanying drawings.

[0104] It will be appreciated that all doping polarities mentioned above could be reversed, the resulting devices still being in accordance with embodiments of the present invention.

[0105] Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.