ILLUMINATION DEVICE AND METHOD FOR DECOUPLING POWER DELIVERED TO AN LED LOAD FROM A PHASE-CUT DIMMING ANGLE

Abstract

An illumination device and method are provided for controlling light emitting diodes (LEDs). The LEDs (specifically, the LED loads) are controlled, e.g., brightness and color of the LED loads, independent of a phase-cut dimmer applied to the AC mains feeding a DC power supply. The power supply is active dependent upon the duration of a conduction angle supplied from the dimmer. The power supply, however, produces drive currents that are independent from the conduction angle by using a two-stage power supply and a relatively slow and fast control loops that are controlled through a microprocessor based control circuit. Parameters stored in the control circuit are drawn by the microprocessor to control the two-stage power supply to produce the drive currents independent and decoupled from the conduction angle yet dependent on the controller parameters.

Claims

1. An illumination device, comprising: an AC main line configured to receive an AC main; an LED load coupled to receive a drive current; a dimmer coupled to the AC main line; a control circuit coupled to receive transitions of the AC main and to measure a conduction angle from the dimmer and produce a maximum duration at which a power supply can be active; a said power supply coupled between the dimmer and the control circuit, and operational up to and including the maximum power supply active duration, and configured to apply an updated DC power supply current independent of the conduction angle yet for a duration no greater than the maximum power supply active duration; and wherein the updated DC power supply current averaged over multiple cycles of the AC main is proportional to an updated drive current applied to the LED load.

2. The illumination device as recited in claim 1, further comprising a radio coupled to the control circuit for wirelessly setting the drive current independent of the conduction angle.

3. An illumination device, comprising: a dimmer coupled to an AC main line and configured to produce a conduction angle; a power supply coupled to the output of the dimmer and comprising a first control loop for producing a DC power supply current and DC power supply duration independent of the conduction angle and triggered from periodic transitions from the AC main line; and a light emitting diode (LED) load coupled to receive a drive current substantially proportional to the DC power supply current to produce illumination for the illumination device.

4. The illumination device as recited in claim 3, wherein the DC power supply current ranges upward from a predetermined minimum value if minimal power is drawn by the LED load from the AC main line.

5. The illumination device as recited in claim 3, wherein the DC power supply current is proportional to an average current drawn from the AC main line measured over more than one cycle of the AC main and inversely proportional to a maximum duration at which the power supply can be active.

6. The illumination device as recited in claim 4, wherein the predetermined minimum value is 100 mAmps.

7. The illumination device as recited in claim 5, wherein the DC power supply duration ranges downward from the maximum duration, and the power supply is on for the maximum duration if the DC power supply current surpasses a predetermined minimum value.

8. The illumination device as recited in claim 3, wherein the DC power supply duration is proportional to an average current drawn from the AC main line measured over more than one cycle of the AC main and inversely proportional to a predetermined minimum value.

9. The illumination device as recited in claim 8, wherein the predetermined minimum value is 100 mAmps.

10. The illumination device as recited in claim 3, wherein the power supply further comprising a second control loop clocked at a faster speed than the first control loop.

11. The illumination device as recited in claim 10, wherein the second control loop is configured to generate an actual DC power supply current sampled from the AC main line more frequently than the DC power supply current.

12. The illumination device as recited in claim 3, wherein the second control loop is configured to generate a series of pulses configured to be applied to a gate which controls current through a primary winding of a transformer, the secondary winding of which produces a DC voltage applied to generate the drive current.

13. The illumination device as recited in claim 3, further comprising: a control circuit coupled to detect the conduction angle by measuring the amount of time during each one half cycle of an AC main on the AC main line, between when the AC main is initially rectified positive to when the rectified positive AC main phase angle equals 180° degrees or 360° phase angle.

14. The illumination device as recited in claim 12, further comprising: a control circuit coupled to produce digital reference parameters converted to analog and used by comparators in the power supply to adjust the duty cycle of each of the series of pulses.

15. (canceled)

16. A method for supplying an AC main to a light emitting diode (LED) load, comprising: adjusting a dimmer coupled to the AC main; rectifying positive the output of the dimmer; measuring a conduction angle by measuring the amount of time between when the AC main is initially rectified positive to when the rectified positive AC main phase angle equals 180° degrees or 360° phase angle; and generating a series of pulses during a duration of the conduction angle, each having an active logic value dependent on an amount of drive current needed to be supplied to the LED load and independent of the conduction angle.

17. The method as recited in claim 16, wherein said generating a series of pulses comprises: generating a DC power supply current and a DC power supply duration during each of a duration of the conduction angle; and during the DC power supply duration, generating the series of pulses each of which includes the active logic value.

18. The method as recited in claim 16, further comprising: comparing a DC voltage upon the LED load to a reference voltage and setting an average current drawn from the AC main that is then proportionally supplied as said drive current to the LED load; increasing the average current if the LED load increases; mapping a DC power supply current and a DC power supply duration from the average current by maintaining DC power supply current above a minimum value and maintaining DC power supply duration below a maximum duration of the conduction angle; and setting the duration of the cumulative said series of pulses as well as the duration of the active logic value for each pulse corresponding to the respective DC power supply duration and the DC power supply current; and commuting the current drawn from the AC main proportional to the duration of the active logic value of each pulse.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings.

[0033] FIG. 1 is one example of a block diagram of a conventional dimmer-controlled, LED-based illumination device;

[0034] FIG. 2 is a timing diagram of the AC main applied to, for example, a trailing edge dimmer;

[0035] FIG. 3 is a timing diagram of the conduction angle from the leading edge dimmer having transients at the leading edge of the conduction angle and drift between conduction angles;

[0036] FIG. 4 is a timing diagram showing the variability of a 90 degree conduction angle as a result in changes made to, for example, a trailing edge dimmer;

[0037] FIG. 5 is a graph of conduction angle vs. brightness that is relatively linear but with variable ranges of conduction angle and brightness;

[0038] FIG. 6 is a block diagram of a dual stage power supply that controls an LED load decoupled and independent from a conduction angle produced by the dimmer;

[0039] FIG. 7 is a block diagram of the power supply having fast and slow control loops for measuring duration of the conduction angle by the slow control loop and actual instantaneous current drawn from AC main by the fast control loop to set the DC power supply current drawn from the AC main and supplied to the LED load during each conduction cycle;

[0040] FIG. 8 is a state diagram of the I.sub.AVE mapping sequential circuit of FIG. 7;

[0041] FIG. 9 is a state diagram of the I.sub.ACT calculation circuit of FIG. 7;

[0042] FIG. 10 is a timing diagram of the I.sub.ACT computation point taken from I.sub.PK value, and T.sub.GATE and T.sub.G2I timing values;

[0043] FIG. 11 is a circuit diagram of the AC/DC analog block diagram of FIG. 7;

[0044] FIG. 12 is a timing diagram showing signals sent to and from the fast timing circuit of FIG. 7;

[0045] FIG. 13 is a timing diagram showing signals sent to and from the slow timing circuit of FIG. 7 for when the power supply draws greater power from the AC main line and produces a corresponding greater current onto the LED load;

[0046] FIG. 14 is a timing diagram showing signals sent to and from the slow timing circuit of FIG. 7 for when the power supply draws smaller power from the AC main line and produces a corresponding smaller current onto the LED load; and

[0047] FIG. 15 is a block diagram of the control circuit and processor within the control circuit for measuring conduction angle and the maximum time in which the power supply is on.

[0048] While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] An illumination device and method are disclosed for luminance control of an LED load. Specifically, the illumination device includes a dimmer coupled to an AC main line and a power supply coupled between the dimmer and the LED load. Coupled to the power supply is a control circuit having a microprocessor. The control circuit measures the conduction angle output from the dimmer onto the input of the power supply. From that conduction angle, the control circuit can determine the maximum time duration at which the power supply can be active. The active power supply produces a drive current onto the LED load independent of the conduction angle, albeit relative to the maximum time it is active. Instead of being dependent on the conduction angle as in conventional power supplies, the improved power supply herein comprises two stages, wherein the first and second stages produce the drive current dependent upon the amount of brightness and color spectrum needed by the LED load, independent of the dimmer angle or conduction angle. The drive current is controlled by the controller and, specifically, by parameters stored and thereafter fetched from a memory of the microprocessor and therefore set within the control circuit. The drive current is not set by the conduction angle output from the dimmer, as would be the case in conventional designs. The controller parameters can be set in firmware during manufacture or can be periodically reset from a wired or wireless communication device coupled to the controller via the wired or wireless communication channel.

[0050] FIG. 6 illustrates one example of the improved illumination device. Specifically, FIG. 6 illustrates a dimmer 30 coupled to an AC main line, such as the well-known AC main lines used in residential or commercial applications and carrying, for example, a 120V RMS at 60 Hz or 220V RMS at 50 Hz. Dimmer 30 comprises any dimmer that can couple to an AC mains supply voltage to employ angle modulation of a switching device, such as triac. Such dimmers are relatively well known and are used to adjust the duty cycle of the AC dimmer output signal to provide either a leading edge phase-cut dimmer output or a trailing edge phase-cut dimmer output. Dimmer 30, whether leading or trailing edge, is manually controlled either through sliding or rotating actuators associated with a faceplate mounted in the residential or commercial structure.

[0051] Coupled to the output of dimmer 30 can be electromagnetic interference (EMI) circuit 32 to block any disturbance generated by an external source onto the AC main line and can include any of the well-known narrowband or broadband EMI filtering circuitry. Coupled to the output of EMI 32 is bridge circuit 34. Common examples of a bridge circuit include, for example, a diode bridge. Bridge 34 operates in conjunction with dimmer 30 to produce a rectified output (V.sub.HV) from the phase-cut AC mains. As noted above, however, V.sub.HV has transience at the leading edge, for example, of a leading edge rectified dimmer output. Moreover, due to the nature of the triac circuitry of dimmer 30, certain triacs may fail to turn on reliably with reactive loads if the current phase shift within the triac causes the main circuit currents to be below the holding current at the time in which the triac triggers. Thus, a triac can “reset” if the current through the triac drops below the holding current. The problems in conventional design of AC transience on the leading edge of the conduction angle, and shift due to improper triac reset are overcome using the architecture set forth in power supply circuitry 36.

[0052] Power supply 36 comprises first stage 38 and second stage 40. First stage 38 is an AC/DC converter that produces a DC voltage (V.sub.DC) from the AC main voltage (V.sub.HV). Second stage 40 is a DC/DC converter that produces the drive current to the LED load 42. Thus, while V.sub.HV is a filtered and rectified version of the AC mains voltage produced by dimmer 30, V.sub.DC is the DC-converted voltage from V.sub.HV. V.sub.DC feeds a relatively large output capacitor to provide the necessary drive current to achieve the desired brightness and color spectrum when multiple LED chains 44 are used. While FIG. 6 illustrates one LED chain, it is understood that power supply 36 can be replicated to produce drive currents to other LED chains having a different color spectrum, such as green, blue, red, or white, to achieve any desired brightness for each LED chain and, thus, the proper color mixing across the plurality of chains.

[0053] Differential amplifier 46 is coupled to the AC main line and produces a voltage (V.sub.IN) proportional to the AC line voltage V.sub.HV sent to power supply 36. V.sub.IN is at a sufficiently low voltage value so that it can be digitized by first stage 38, and thereafter used by the phase-locked loop (PLL) (FIG. 15) of control circuit 48. Referring to FIGS. 6 and 15, control circuit 48 can include a processor 50 along with PLL 52 containing a memory and a microprocessor that sets parameters used by the power supply 36 to change the drive current. The power supply changes the drive current through the LEDs by use of a first control loop (slow loop) feedback in response to changes in the DC voltage output (V.sub.DC) from the first stage AC/DC 38. The LED drive current, however, is related and proportional to DC power supply current averaged over multiple cycles of the AC main (I.sub.AVE) and drawn from the AC mains line, whereby any changes to the LED drive current via the microprocessor-based controller causes average current drawn from the AC main line (I.sub.AVE) to change. The controller also changes the power supply current drawn from the AC main line during each conduction cycle (I.sub.PS) as well as the time that the power supply 36 is on (T.sub.PON). Thus, instead of using dimmer 30 to set the drive current, control circuit 48 sets the drive current based upon the desired brightness needed for each LED chain 44 within LED load 42. Therefore, drive current is set independent from the conduction angle produced by dimmer 30, using the present dual-stage power supply 36 controlled by control circuit 48. One mechanism in which to set the parameters for controlling the drive current via control circuit 48 is through a wired or wireless user input. An example of a wireless user input includes a wireless communication protocol, such as IEEE 802.15, Bluetooth or Zigbee. Radio 54 is shown to interface with the processor of control circuit 48 in order to set the parameters used to establish any drive current independent of the conduction angle output from dimmer 30.

[0054] Turning now to FIG. 7, a block diagram of power supply 36 is shown having a fast control loop 58 and a slow control loop 60. In addition, power supply 36 comprises AC/DC analog portion 62, details of which are set forth in FIG. 11. AC/DC analog 62 receives V.sub.HV and V.sub.IN from the rectified dimmer and differential amplifier (FIG. 6). Moreover, AC/DC analog 62 receives certain signals from control circuit 48 (FIGS. 6, 15). Further details of how the AC/DC analog 62 derives the zero crossing detect (ZCD) signal and the current comparator (I.sub.CMP) signal are described with regard to FIG. 11. Signals ZCD and I.sub.CMP are used by fast control loop 58, whereas the slow control loop 60 uses a line sense (LSNS) signal derived from V.sub.IN, details of which are set forth in FIG. 11. LSNS represents the transitions that occur at the leading and trailing edges of the conduction angle duration computed by the determination of V.sub.IN at the output of differential amplifier 46 (FIG. 6). In addition to LSNS sent from AC/DC analog 62, a feedback voltage (V.sub.FB) is sent to slow control loop 60; specifically, to a comparator or adder 64. Comparator 64 compares a divided-down V.sub.DC digitized value (V.sub.FB) to a target value sent from control circuit 48; specifically, from a stored parameter within processor 50 (FIG. 15). The target value (V.sub.TAR) is a constant set by the control circuit software such that a divided voltage of V.sub.DC that is digitized is compared to that constant V.sub.TAR provided by processor 50 in control circuit 48. The difference is applied to integrator 66 which filters that difference to produce the DC power supply current averaged over multiple cycles of the AC main (I.sub.AVE) and drawn from the AC main line. Drive current is that which is applied to the LED load 42. Drive current is proportional to the amount of time that a series of pulses are applied to the analog portion 62 to affect the DC output voltage V.sub.DC. Slow control loop 60 is a well-known second order loop with a proportional/integral PI loop filter 66, shown to produce the average current (I.sub.AVE), since the current drawn from the line, I.sub.AVE, is represented as a number output from the proportional/integral loop filter 66. I.sub.AVE, when represented as a signal, is proportional to the drive current produced from the power supply 36, which flows into LED load 42. The slow loop preferably has a bandwidth of maybe a few Hz, but DC power supply current (Ips) can be calculated at any sample rate above maybe 10 times the slow loop bandwidth. Ips can be updated once per half AC main cycle, or 60 Hz, but update can occur at possibly 10 times per half cycle or once every two half cycles.

[0055] The I.sub.AVE is, in essence, used to generate a series of GATE pulses applied to a flyback converter 68 via an I.sub.SNS controlled through the primary winding 70 of flyback circuit 68, all of which are more fully described in FIG. 11. The I.sub.AVE signal is used to implement and regulate flyback converter 68 through transitions of the GATE pulses, wherein the GATE pulses are derived through a combination of T.sub.PON and I.sub.PS at the output of I.sub.AVE map circuit 74. Details of circuit 74 as a sequential state machine are more fully described in FIG. 8. Circuit 74 produces I.sub.PS and T.sub.PON depending on the magnitude of I.sub.AVE. Details of the mapping function needed to generate I.sub.PS and T.sub.PON are described in relation to FIG. 8. T.sub.PON is used by a slow timer circuit to generate a power supply enable signal (PSEN) having a duration of the T.sub.PON duration up to maximum time of the power supply being on (MAX T.sub.PON), whose value is used by circuit 74.

[0056] The value of when the DC power supply is on for a maximum duration (MAX T.sub.PON), more fully described in FIG. 8, is derived when control circuit 48 detects the LSNS value for determining the conduction angle and subtracting a predetermined offset parameter. The PSEN signal is used to trigger the fast timer circuit; specifically, to produce certain signals, such as T.sub.PER and T.sub.G2I used by I.sub.ACT calculation circuit 86 to produce the actual instantaneous current drawn from the AC main and applied to comparator 88 that determines the error between I.sub.PS and I.sub.ACT. That error from comparator 88 is filtered to determine the duration at which each pulse of of the GATE signal is in an active logic state, e.g., logic value high shown as T.sub.GATE. T.sub.GATE is used by fast timer circuit 82 to generate the signals necessary by I.sub.ACT calculation circuit 86 to readjust IACT so that the actual instantaneous draw resolves back to the DC power supply current (I.sub.PS) applied at each conduction angle per one half AC mains cycle to the LED load. Further details of the operation of fast control loop 58 are more fully described in the timing diagram of FIG. 12. The drive current applied to the LED load is therefore substantially proportional to the DC power supply current (I.sub.PS) averaged over multiple cycles of the AC main (I.sub.AVE), taking into account other current needed to operate all the other circuits DC circuits associated with the illumination device. For example, when the power supply is on for a maximum duration, the drive current is substantially proportional to the DC power supply current. However, when the power supply is on for less than the maximum duration, the drive current is substantially proportional to the DC power supply current minus a predetermined amount of current needed to operate the DC circuits. For example, the LED load can consume, for example, 17 W while the remaining DC circuits can consume, for example, 0.5 W.

[0057] Circuit 74 determines both the power supply current (I.sub.PS) and the length of time (T.sub.PON) per ½ AC mains cycle in which voltage is applied to the output capacitor coupled to V.sub.DC which, in turn, supplies power to the second stage which then applies power (i.e., drive current) to the LED load. PLL 52 and logic within control block 48 (FIG. 15) determine the maximum amount of time that the first stage 38 of power supply 36 is on and can run during each ½ cycle of the AC mains (MAX T.sub.PON).

[0058] Referring to FIGS. 7 and 8, circuit 74 is a sequential machine that compares the incoming I.sub.AVE against certain values, as shown by decision block 90. Block 90 determines if I.sub.AVE≦a predetermined minimum value (e.g., 100 mA)×120 Hz×MAX T.sub.PON. If the answer to block 90 is yes, then

[0059] I.sub.PS=a predetermined minimum value (e.g., 100 mA)

[0060] T.sub.PON=(I.sub.AVE/a predetermined minimum value)×(1/120 Hz).

If the answer to block 90 is no, then

I.sub.PS=I.sub.AVE×(1/MAXT.sub.PON×120 Hz)

T.sub.PON=MAX T.sub.PON

[0061] The above equations simply note that when determining the magnitude of the power supply current (I.sub.PS) and the actual time that the power supply operates (T.sub.PON), a comparison is needed of I.sub.AVE against certain parameters. The equations indicate that as I.sub.AVE increases, I.sub.PS remains at a predetermined minimum value, e.g., 100 mA, and T.sub.PON increases. When I.sub.PS and T.sub.PON increases and once I.sub.PON=MAX T.sub.PON, I.sub.PS increases from the predetermined minimum value, e.g., 100 mA. Block 90 merely indicates that a minimum power supply current is maintained, and does not increase until after the time that the power supply operates (T.sub.PON) and is equal to the maximum time in which the power supply can operation (MAX T.sub.PON). In this fashion, the power supply current is always maintained above a predetermined minimum value and the duration in which the power supply is on will never exceed MAX T.sub.PON derived as an offset from the conduction angle as computed by the control circuit. The minimum value is set to be greater than the hold current needed to keep the triac in the conducting state and prevent such from resetting.

[0062] Once the power supply current (I.sub.PS) and the actual time in which the power supply operates (T.sub.PON) is determined, the actual instantaneous current through first stage 38 (I.sub.ACT) is controlled by fast control loop 58. Fast control loop 58 has a much higher bandwidth than slow control loop 60. For example, fast control loop 58 may be in excess of 1 kHz, while slow control loop 60 may have a bandwidth of only a few Hz.

[0063] Fast control loop 58 is used to compare the actual instantaneous current through the AC/DC converter (I.sub.ACT) to the power supply current (I.sub.PS). The power supply current is that which exists through second stage 40 of power supply 36. The difference between the power supply current and the actual instantaneous AC/DC current is compared by comparator 88, and difference is low-pass filtered by filter 89, which is an integrator, to produce the time that the gate is at a logic active state or logic high (T.sub.GATE). The difference between the instantaneous current (I.sub.ACT) and the power supply current (I.sub.PS) is basically the difference between each instantaneous moment in time versus the current over the entire ½ cycle of the AC mains or the current of the AC mains. The actual instantaneous current (I.sub.ACT) is sampled at the fast timer rate of at least 50 kHz, which is the switching rate of signal GATE. The power supply current (I.sub.PS) is sampled at a much lower rate, e.g., less than ½ the AC mains cycle. Fast control loop 58 operates to hold the actual instantaneous current (I.sub.ACT) to the power supply current (I.sub.PS) over time.

[0064] Accordingly, slow control loop 60 controls V.sub.DC and fast control loop 58 controls the actual instantaneous current (I.sub.ACT) drawn from the AC mains. For relatively low average currents (I.sub.AVE), fast control loop 58 holds I.sub.ACT to a predetermined minimum value, e.g., 100 mA, and the amount of time (T.sub.PON) that the power supply 36 operates; T.sub.PON can vary, yet the I.sub.AVE is maintained to no less than the predetermined minimum value, e.g., 100 mA. As noted, once T.sub.PON reaches MAX T.sub.PON determined by control circuit 48, then I.sub.PS increases based on any needed increase effectuated by software within the controller or through direct user interaction via radio 54 or a wired link

[0065] As noted in FIG. 7, the I.sub.ACT calculation block 86 uses the gate timing (T.sub.GATE) and the current sense comparator output (I.sub.CMP) to determine I.sub.ACT. How that determination takes place is described in more detail with reference to FIGS. 9, 10, and 12. Turning to FIG. 11, AC/DC analog circuit 62 (FIG. 7) is shown in circuit form. AC/DC analog 62 comprises damper circuit 100, bleeder circuit 102, and flyback circuit 68. AC/DC analog 62 also includes control power supply 104 and circuitry needed to produce the line sense (LSNS) from V.sub.IN and a feedback voltage (V.sub.FB or V.sub.IN) multiplexed from a shared analog-to-digital converter (ADC) 106, that either inputs a divided-down V.sub.DC through resistor dividers 108 or the V.sub.IN from differential amplifier 46 (FIG. 6). The V.sub.IN voltage output from ADC 106 is at a lower voltage than the AC mains, but is proportional to the AC mains and is purposely used to detect the conduction angle output from the dimmer V.sub.SUPPLY provides voltage needed for the digital circuits, including the control circuit.

[0066] Damper circuit 100 is simply a transistor placed in parallel with a resistor. The resistor is one having a fairly small value such as, for example, 150 ohms. The resistor damps input transience when the /DMP signal output from slow timer circuit 18 transitions to an active low state. The purpose of damping circuit 100 is to ensure that dimmer circuit 30 operates properly. For example, when a triac is used for the dimmer and the triac transitions on, a large voltage is applied to the power supply. That voltage appears at the leading edge of, for example, the conduction angle (FIGS. 3, 4). That large voltage oscillates as a fairly large transient current. To minimize the oscillation and to prevent the triac from resetting, the AC/DC analog 62 includes damping circuit 100 to place a low impedance resistor onto the capacitive load of the rectified and filtered AC main line to damp the oscillations. Slow timer 80 sets the damp signal (/DMP) active during the transience to connect the passive load of the relative small resistor by turning the parallel-coupled transistor off. The /DMP signal is maintained at an active low between each of a pair of conduction angles, all set by slow timer 80. The active damp extends past the leading edge of the conduction angle to remove or damp the oscillations, and shortly thereafter is deactivated by transitioning on the parallel-coupled transistor so that the power supply begins operating with a large initial T.sub.GATE time of T.sub.INT. The initially large T.sub.GATE that consists of T.sub.INT is shown in FIG. 12. T.sub.INT is predetermined to produce an active input impedance roughly equal to the passive input impedance produced when /DMP is active. A larger T.sub.INT versus subsequent T.sub.GATE causes the GATE voltage to extend for a longer duration during initial power supply activity so input impedance upon the line voltage V.sub.HV (V.sub.HV/I.sub.ACT) is roughly equal to the passive impedance of the resistor within damping circuit 100 when /DMP is active. Referring to FIG. 12, T.sub.INT only exists for the first T.sub.GATE duration and, thereafter, subsumes back to the normal T.sub.GATE duration.

[0067] As noted, certain leading edge or trailing edge triac dimmers require current to be drawn through the AC main line throughout each cycle in order for the conduction angle to be measured properly. After firing, a triac will typically turn off once the current through that triac drops below a certain level. For example, the minimum I.sub.PS, e.g., 100 mA, is sufficient to hold the triac on. However, a triac may reset after power supply 36 turns off, but before the line voltage V.sub.HV drops to near 0. If the triac of dimmer 30 resets prior to the line voltage V.sub.HV dropping to near 0, controller 48 may measure incorrect dimmer angles, i.e., instead of producing the correct dimmer angle or conduction angle and, thus, the correct MAX T.sub.PON, the measured conduction angle and resulting MAX T.sub.PON may be incorrect. Therefore, slow timer 80 produces a bleed signal (BLEED) to instruct circuit 102 to draw a fixed current of a predetermined minimum value, e.g., 100 mA, during times when the power supply 36 is not active and the conduction angle is being measured. Absent an accurate conduction angle measurement, MAX T.sub.PON cannot be output from controller 48, which will dictate when the DC power supply current will be at 100 mA and will exceed, for example, 100 mA when the time the power supply is on reaches the measured MAX T.sub.PON.

[0068] Similar to holding on a triac of dimmer 30, the LED load must draw the drive current I.sub.AVE and the power supply current I.sub.PS from the trailing edge dimmer when measuring the conduction angle. A trailing edge dimmer turns on when the line voltage is near 0 and can turn off when the line voltage is high or at its peak. The line input capacitance must be discharged rapidly when the trailing edge dimmer turns off in order for controller 48 to determine the conduction angle. During cycles in which controller 48 measures the conduction angle, the BLEED signal goes active after the power supply turns off after T.sub.PON ends or when T.sub.PON=MAX T.sub.PON turns off. The falling edge of LSNS indicates the point at which the conduction angle turns off, which puts the power supply in what is known as a current pulse mode (CPM) and turns on the damper circuit with /DMP active low while the dimmer circuit is not conducting. However, the periodic pulses of the GATE signal that occurred during the conduction cycle are maintained in an active logic value, such as logic voltage high during CPM, shown in FIG. 13.

[0069] Turning to FIG. 11, control circuit 104 of power supply 62 comprises the start-up circuit 110 coupled to a V.sub.SUPPLY bypass capacitor 112 and auxiliary winding 114. When power is first applied to the LED lamp, V.sub.HV goes above the zener voltage of the zener diode within circuit 110. V.sub.SUPPLY bypass capacitor 112 charges up to the zener voltage minus the transistor gate source voltage, and minus the diode drop of circuit 110. When flyback converter 68 is operating, auxiliary winding 114 continually charges capacitor 112 through diode 120 to a slightly higher voltage than circuit 110 applied to capacitor 112, which then turns off circuit 110. Accordingly, circuit 110 is simply used to charge up to and past the zener voltage via auxiliary winding 114. Once the charge up has occurred, circuit 110 is deactivated and, thereafter, does not burn power from the AC mains through DC power supply 62.

[0070] Flyback converter 68 comprises a transformer with primary winding 70 and secondary winding 124. When the GATE signal is high, primary winding 70 conducts and current through increases linearly with time. The current sense resistor R.sub.SNS and comparator 126 produces a current comparator output I.sub.CMP. I.sub.CMP indicates when the primary current reaches a certain value set by the IDAC, where IDAC arrives from a parameter set within the control circuit processor. Fast timer 82 (FIG. 7) uses I.sub.CMP to determine when to turn GATE off. When GATE goes low, the primary current drops to 0 and the energy stored in the transformer core produces current in secondary winding 124. The secondary winding current flows through the diode and into the V.sub.DC bypass capacitor 130 and to the LED load 42 (FIG. 6). A small portion of the energy stored in the core produces current in the auxiliary winding 114 that passes through the diode and into capacitor 112. Once all the energy stored in the core is depleted, the current in both secondary winding 124 and auxiliary winding 114 stops flowing and the voltage across both windings collapses. Zero crossing detect (ZCD) comparator 134 and its corresponding DAC detect this collapse and sets ZCD to a logic high value. Shown in FIG. 12, fast timer 82 uses this rising edge of ZCD to set GATE high, starting another power supply computation cycle.

[0071] Turning now to FIGS. 7 and 12 in combination, FIG. 12 illustrates the timing of the signals in and out of fast timer 82 of FIG. 7. Power supply enable (PSEN) signal, GATE, I.sub.CMP, and ZCD are logic level signals, while T.sub.GATE, T.sub.PER, T.sub.G2I, and I.sub.INT are numbers. Slow timer 80 activates the PSEN signal by first detecting LSNS. LSNS is output from the comparator whose input is set by the LDAC parameter of the control circuit and V.sub.IN. LSNS determines when the rectified AC main is above or below a certain relatively low voltage, e.g., 20 volts. Slow timer 80 and controller 48 use the rising edge of LSNS to initiate the power supply start sequence and the conduction angle measurements, respectively. Referring to FIG. 13, it is from LSNS that PSEN is derived from slower timer 80 in response to LSNS going high and deactivating PSEN after the time specified by T.sub.PON. As shown in FIG. 12, first stage 38 of power supply 36 is active when PSEN is high, as shown by T.sub.PON. The AC/DC converter starts switching with a relatively long GATE high time T.sub.GATE of T.sub.INT, which produces an active load roughly equal to the damper passive load. The high bandwidth current control loop or fast control loop 58 then gradually adjusts T.sub.GATE and consequently I.sub.ACT until I.sub.ACT equals the current I.sub.PS, set by the low bandwidth or slow control loop 60. This reduction T.sub.GATE is illustrated in the GATE signal and the sequence of GATE pulses of FIG. 12.

[0072] While the time GATE is high is specified by T.sub.GATE, the time that GATE is low is determined by ZCD. ZCD goes high when all the energy in the transformer core of flyback converter 68 has been transferred and secondary winding 124 and auxiliary winding 114 current drops to 0. As such, a rising edge of ZCD will trigger the start of another AC/DC computation cycle with GATE again going high. Accordingly, the rising edge of ZCD turns GATE on.

[0073] When GATE goes high, the current flowing through primary winding 70 increases linearly with time. When the primary winding current reaches a certain value determined by IDAC and R.sub.SNS, I.sub.CMP goes high. The time from GATE going high to I.sub.CMP going high is shown as T.sub.G2I in FIG. 12; the period of GATE is shown as T.sub.PER. The I.sub.ACT calculation block 86 (FIG. 7) uses T.sub.G2I and T.sub.PER, along with T.sub.GATE, to determine the actual instantaneous current I.sub.ACT drawn from the AC main line. Accordingly, while the rising edge of ZCD turns GATE on, the expiration of time Tgate from the fast loop integrator that turns GATE off. It is duration T.sub.GATE and the series of pulses for T.sub.GATE that determine I.sub.PS and the drive current that flows into the LED load.

[0074] Turning now to FIG. 13, illustrated is a timing diagram of the signals in and out of slow timer 80 (FIG. 7) in relation to V.sub.HV, GATE, and the PLL ZCD signal from controller 48. In the example shown, dimmer 30 is adjusted to produce roughly 90° of conduction angle. The rectified V.sub.HV to first stage 38 of power supply 36 comprises rectified ¼-cycle sine waves. With LDAC sent from the control block configured to switch LSENS when V.sub.HV is about 15 volts, LSENS goes high when this leading edge dimmer turns on and then goes low very close to the end of each ¼-cycle. Damper circuit 100 turns on with /DMP going low, with LSENS going low which turns off a fixed delay after LSENS goes high. That fixed delay is necessary to remove the transience from V.sub.HV. Moreover, the fixed delay is predetermined to be sufficient for all major transience to subside. Shown in FIG. 11, while /DMP is low, the resistor placed in series with the lamp power input capacitance, is coupled to V.sub.HV.

[0075] Referring to FIGS. 13-14, two sets of GATE, PSEN, BLEED, and I.sub.HV are shown. The input current is the current drawn from the AC mains; specifically from V.sub.HV. The (A) group illustrates the timing when the AC/DC stage of the power supply is drawing a relatively large amount of power from the AC mains, wherein the power duration of T.sub.PON=MAX T.sub.PON. The (B) group illustrates the timing when the AC/DC stage of the power supply is drawing a relatively little power, where T.sub.PON<MAX T.sub.PON and I.sub.PS=predetermined minimum value, e.g., 100 mA. In both the (A) and (B) groups illustrated in FIGS. 13-14, the AC/DC converter first stage turns on when the damper circuit turns off with /DMP going high. PSEN goes high and GATE starts switching during T.sub.PON (FIG. 14) and during MAX T.sub.PON (FIG. 13). For example, PSEN (A) goes low and GATE (A) stops switching after the time specified by MAX T.sub.PON. The AC/DC converter can efficiently draw power from the AC main line only when V.sub.HV is above a certain voltage. MAX T.sub.PON is predetermined to ensure that V.sub.HV is sufficiently high whenever the AC/DC converter is on.

[0076] While LSEN is low, the first stage AC/DC converter operates in the current pulse mode (CPM). CPM provides a DC load for the dimmer and in CPM, the GATE commutes solely on I.sub.CMP and ZCD. GATE goes high with ZCD and low with I.sub.CMP. FIGS. 13-14 illustrate GATE (A) and (B) remaining high when LSEN is low since typically that is the case when V.sub.HV is nominally 0. However, CPM enables the LED load to discharge stray capacitances and sink any dimmer leakage currents or other parasitics.

[0077] BLEED (A) and (B) are active between PSEN going low and LSEN going high. When BLEED is high, a predetermined fixed current, e.g., 100 mA, is drawn from the AC main line keeping the triac conducting and enables the conduction angle to be accurately measured. BLEED is active when LSEN is low and the dimmer is not conducting for the same reason that the AC/DC converter first stage operates in CPM. The bleeder helps discharge any parasitics. Preferably, the bleeder need not be active between every pair of conduction angles and, possibly, need only be active between every eighth or twentieth pair of conduction angles, since the bleeder does draw significant current and may not be necessary to bleed after every conduction angle. Preferably, the conduction angle need only be measured at every half AC mains cycle, and when the conduction angle is measured, bleeder is active.

[0078] The I.sub.HV (A) and (B) curves illustrate the current drawn from the AC main line through V.sub.HV for the relatively high and low current conditions shown. In both cases, I.sub.HV quickly ramps to the same high level when the triac dimmer initially turns on. This current is determined by the damping resistor within the damping circuit, and is generally fairly small, e.g., 150 ohms. When the PSEN goes high, the AC/DC first stage draws roughly this same high current actively. The I.sub.HV current then decreases to I.sub.PS determined by the low bandwidth or slow control loop 60 over a period of time. In the (A) example, I.sub.PS is larger than 100 mA since T.sub.PON=MAX T.sub.PON; I.sub.HV drops to 100 mA drawn by the bleeder after PSEN goes low and BLEED (A) goes high. In the (B) example, I.sub.PS is equal to 100 mA since T.sub.PON<MAX T.sub.PON; I.sub.HV simply stays at 100 mA since both the bleeder and the AC/DC converter first stage are set to draw 100 mA. Of course, the predetermined minimum value can be set at any value, with 100 mA being one example. As noted, BLEED does not need to be active every cycle, but only during angle measurement cycles, possibly between every eighth, twentieth, or more pairs of conduction angles.

[0079] Turning now to FIGS. 9-10, the I.sub.ACT calculation 86 (FIG. 7) logic is shown. Specifically, a state diagram logic block and a timing diagram of I.sub.ACT computation point taken from I.sub.PK value, as well as T.sub.GATE and T.sub.G2I timing values. First, the I.sub.ACT calculation must determine a peak primary current (I.sub.PK) through the primary winding 70.

I.sub.PK=(T.sub.GATE/T.sub.G2I)×I.sub.SNS

I.sub.ACT=(I.sub.PK/2)×(T.sub.GATE/T.sub.PER)

Knowing the peak current through the primary winding, I.sub.ACT can be set near a midpoint and derived therefrom based on readings of T.sub.GATE and T.sub.PER. Thus, from the peak primary current, the actual primary current can be derived, with I.sub.ACT set to I.sub.PS within fast control loop 58 (FIG. 7). I.sub.SNS is shown to be the current through R.sub.SNS (FIG. 11). The average current through primary winding I.sub.ACT over one AC/DC computation cycle is ½ the peak current I.sub.PK scaled by the time GATE is high, T.sub.GATE/one computation cycle T.sub.PER.

[0080] Referring to FIG. 15, control circuit 48 is shown; specifically the AC/DC converter first stage functionality, comprising PLL 52 and microprocessor 50. Microprocessor 50 configures the parameters in the AC/DC first stage and DC/DC second stage converters of power supply 36, and also interfaces to radio 54 to communicate control and status messages. V.sub.IN being a scaled version of the line input voltage is digitized and forwarded to PLL 52. PLL 52 qualifies such samples with LSNS and uses successive samples to determine the phase error between the PLL output and the AC main line cycle. The phase error is filtered and then used to produce a digital sine wave in sync with the AC main line voltage. The output of PLL 52 is a number from 1-360 representing the AC mains phase as function of time. The PLL ZCD pulse is high when the phase equals 180° or 360°, indicating a zero crossing detection of the conduction angle phase.

[0081] The LSNS and PLL ZCD are forwarded to a set/reset latch 94 whose output enables a counter 96 and low pass filter 98. The count value is used to compute the conduction angle from the dimmer regardless of how that dimmer is set. An offset from processor 50 is compared with the conduction angle via comparator 100 to produce a maximum time in which the power supply is on (MAX T.sub.PON). MAX T.sub.PON and the conduction angle are used by slow control loop 60; specifically, I.sub.AVE map 74 (FIG. 7). Although the conduction angle and MAX T.sub.PON are computed, it is not the conduction angle or MAX T.sub.PON that determines the drive current supplied to the LED load. Thus, the drive current, I.sub.PS, and I.sub.AVE can be independent from the conduction angle output from the dimmer Radio 54 illustrates one way in which to input control and status messages into processor 50. However, processor 50 can generate the parameters shown to set comparator values (within, for example, the analog portion of the power supply) based on software derived commands within processor 50 using various fetch routines from associated memory within processor 50. Processor 50 merely executes those commands to apply the appropriate parameters at the appropriate times onto, for example, the analog portion of the power supply as well as upon the slow and fast control loops.

[0082] It will be appreciated that the various parameters and certain magnitudes described herein are given by way of example only. The parameters and magnitudes can be modified to any value for controlling the LED load (both brightness and/or color) independent of the dimmer angle setting, and over a range also independent of a range of the dimmer angle setting. The DC power supply can accommodate and scale to dimmers of differing conduction angle ranges, and those of relatively small maximum conduction angles such as, for example, 90°. By decoupling the LED loads from the dimmer angle, the DC power supply can utilize the full dimming range of 0-100% of the LED brightness by significantly reducing and eliminating the dead travel that may be experienced at the top and bottom of the dimming curve, where conventional dimmer settings produce no visible changes in LED light output. In fact, as long as there is sufficient power to be pulled from the AC mains, the present power supply can adjust the lamp brightness downward to, for example, 0.1% of the maximum lamp brightness. This minimum dimming achieved using the present power supply cannot be attained in conventional dimmer and AC/DC converter architecture. It will be readily appreciated that different parameters and values can be employed provided the above outcomes are achieved without departing from the inventive concepts as will be apparent to those skilled in art in view of this description. It is intended that the following claims be interpreted to embrace all such modifications. The specification and drawings are to be regarded in an illustrative, rather than a restrictive, sense.