Selectivity module with serial status signal

Abstract

A selectivity module for dividing a load current in an installation system includes a housing, a plurality of branches in the housing, a plurality of switching devices, and a control unit. Each of the plurality of switching devices is configured for switching a branch current on and off in a corresponding one of the plurality of branches. The plurality of switching devices serves to output information about corresponding switching states. The control unit is connected to the plurality of switching devices and configured to output a status signal as a function of the output information from the plurality of switching devices. The output information relating to the individual switching states of all of the plurality of switching devices is contained in the status signal in a serial encoded form.

Claims

1. A selectivity module for dividing a load current in an installation system, comprising: a housing; a plurality of branches in the housing of the selectivity module; a plurality of switching devices; and a control unit, wherein each of the plurality of switching devices in the housing of the selectivity module is configured to switch a branch current on and off in a corresponding one of the plurality of branches; wherein the plurality of switching devices serve to output information about corresponding switching states; wherein the control unit is directly connected to each of the plurality of switching devices and is configured to output a status signal via status lines as a function of the output information from the plurality of switching devices in the housing of the selectivity module; and wherein the output information relating to the individual switching states of all of the plurality of switching devices in the housing of the selectivity module is contained in the status signal in a serial encoded form.

2. The selectivity module of claim 1, wherein the status signal conforms to a protocol and the protocol is variable.

3. The selectivity module of claim 1, wherein the output information relating to the individual switching states is represented in the status signal in binary form.

4. The selectivity module of claim 3, wherein the status signal has a plurality of sequential information blocks in which one status bit for each of the switching devices characterizes the information relating to the switching state of the respective switching device.

5. The selectivity module of claim 4, wherein the information blocks in the status signal succeed one another periodically.

6. The selectivity module of claim 4, wherein each of the plurality of sequential information block has a start bit, which signals the start of the information block, and a stop bit, which signals the end of the information block.

7. The selectivity module of claim 4, wherein a predefined interval time exists between each two succeeding information blocks of the plurality of sequential information block.

8. The selectivity module of claim 4, wherein each of the plurality of sequential information block has a start bit, wherein the status bits of the information block each possess a predefined first temporal duration; and wherein the start bit has a second temporal duration that is different from the predefined first temporal duration.

9. The selectivity module of claim 8, wherein one of the plurality of sequential information blocks in the status signal is followed immediately in time by a second of the information blocks.

10. A method for providing a status signal of a selectivity module configured for dividing a load current in an installation system, wherein the selectivity module includes a housing, a plurality of branches in the housing, and a plurality of switching devices each configured for switching a branch current on and off in a corresponding branch, the method comprising the following steps: outputting, at each of the plurality of switching devices of the selectivity module, information that indicates the switching state of a corresponding branch; and providing a status signal as a function of the information from the switching devices of the selectivity module; wherein the information about the individual switching states of all of the plurality of switching devices of the selectivity module is contained in a serial encoded form in the status signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will now be explained in more detail with reference to the attached drawings, in which:

(2) FIG. 1 is a schematic block circuit diagram of a selectivity module with wiring configuration according to one embodiment of the invention;

(3) FIG. 2 shows a signal pattern of a status signal according to a first embodiment variant of the invention; and

(4) FIG. 3 shows a signal pattern of a status signal according to a second embodiment variant of the invention.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

(5) The exemplary embodiments described in more detail below represent presently preferred embodiments of the present invention.

(6) FIG. 1 depicts a selectivity module 1 having a housing 2. In the present example, four switching devices S1, S2, S3 and S4 are arranged in the housing 2. Each of the switching devices is assigned to a channel K1, K2, K3 and K4. A module input 3 is connected to all of the channels K1 to K4. Each of the switching devices S1 to S4 is therefore connected to the module input 3 on the input side. On the output side, each of the switching devices S1 to S4 possesses a separate output A1, A2, A3 and A4 which simultaneously represents a module output in each case and thus an electrical interface on the housing 2 of the selectivity module 1.

(7) Each of the switching devices S1 to S4 can assume a switched-on state and a switched-off state. If, for example, a defined overload current or a defined short-circuit current flows through a switching device, then the switching device switches off, i.e., the channel has tripped.

(8) Each switching device S1 to S4 supplies information relating to the respective switching state via a status signal line Z1, Z2, Z3 and Z4 to a control logic unit 4 which is likewise integrated into the housing 2. The control logic unit 4 processes the status information of the individual switching devices S1 to S4 into a serial encoded status signal. The serial encoded signal therefore contains information about all states of the switching devices S1 to S4. The status signal is provided at a module output 6 via an output line 5.

(9) In the wired state shown in FIG. 1, the selectivity module 1 is connected on the input side, i.e., by means of its module input 3, to for example the plus rail of a rectifier 7, which in one embodiment supplies a direct-current voltage of 24V. The minus rail of the rectifier 7 is connected to a further input 8 of the selectivity module 1, the further wiring of which in the interior of the housing 2 is not shown here for clarity of illustration reasons. Loads L1, L2, L3 and L4 are each connected individually to the outputs A1 to A4, respectively, of the selectivity module 1. The loads L1 to L4 are jointly connected on the other side to the minus rail of the rectifier 7. In this way a plurality of selectivity modules can be connected in parallel to the rectifier 7 or to a corresponding current source.

(10) For the purpose of evaluating the states of the channels K1 to K4 or, as the case may be, of the switching devices S1 to S4, the module output 6 is connected for example to a programmable logic controller (PLC) or a corresponding data processing device. For clarity of illustration reasons, such a PLC or data processing device is not shown in FIG. 1.

(11) Accordingly, it is therefore possible to describe the states of the individual channels K1 to K4 that are to be monitored by outputting a serial data word. The states of the individual channels are encoded in the data word and can thus be processed further in the PLC or the data processing device.

(12) The states of the individual channels K1 to K4 that are to be monitored or, as the case may be, of the switching devices S1 to S4 can be sensed individually, i.e., on a channel-specific basis, and processed further. Only a single digital input of a controller connected downstream of the selectivity module is required for this purpose. In this way it is possible to implement complex system parts very inexpensively and easily in automation solutions.

(13) This type of status communication is characterized in that it can employ a very simple protocol which is easy to generate. Further processing of these signals can be accomplished at low cost with modest investment of effort using simple digital inputs and a corresponding processing module in the processing program. In particular, this means, with reference to the example of FIG. 1, that there is no requirement for four separate digital inputs of a PLC for one module, as is the case with selectivity modules known in the art. This results in lower costs for the wiring and the requisite digital inputs of the PLC. The protocol is scalable, i.e., variable, and can therefore be adapted to many applications in the power supply equipment environment.

(14) In one embodiment, the output 6 of the selectivity module 1 can be realized using an optocoupler or switching transistor. Compared to mechanical relays, these are characterized by their resistance to wear and tear. In principle, however, annunciator relays can also be provided at the output 6, if necessary.

(15) The concrete form of a status signal, namely a serial pulse sequence, is shown in FIG. 2. Specifically, FIG. 2 shows a detail of a periodic status signal. A period corresponds to the duration of one information block IB. An information block 1B contains the information relating to all states of the channels or switching devices of the selectivity module. In one embodiment (as shown in FIG. 2), the information block IB is subdivided into an information time IZ and an interval time PZ. In one embodiment, both IZ and PZ can be 2200 milliseconds (ms) in length. The information time IZ begins with a start bit and ends with a stop bit. Located between the start and stop bits in this case are four bits having the significances 2.sup.3, 2.sup.2, 2.sup.1 and 2.sup.0. In this example, each bit has a temporal duration of T0.

(16) An interval equal to the duration of T0 is interposed in each case between two adjacent bits. Each bit possesses a signal value corresponding to the bit value. For example, the signal value in the case of the bit value one corresponds to a predefined level, and is similarly zero for the bit value zero. If all the status bits in the example of FIG. 2 are zero, then a maximum interval MP results between the start bit and the stop bit. The maximum interval MP in the information time IZ can amount for example to 1800 ms if the duration T0 is 200 ms. The interval time PZ (2200 ms) is, therefore, defined longer than the maximum interval MP within the information time 1Z when all information bits are zero. As a result, it is always possible to differentiate between interval time PZ and information time IZ.

(17) The times chosen in the example of FIG. 2 can also be processed by a “slow” PLC having a single digital input. The reason for this is that the level time is 200 ms long and, therefore, significantly longer than the typical cycle time of a PLC.

(18) The status signal of FIG. 2 conforms to a predetermined protocol. The predetermined protocol can, however, be varied for a different application. An example in this regard is shown in FIG. 3. According to the protocol there, use is once again made of periodically transmitted information blocks IB′. Each information block IB′ begins with a start bit. In this example, the width of a start bit is double that of the start bit of FIG. 2. The start bit, therefore, has a width of 2.Math.T0 (e.g. 400 ms). In other words, a start bit has from the outset a predefined non-zero signal value which is constant up to the end of the bit.

(19) In this case, there are once again four status bits between two start bits, the status bits representing the states of the four channels of the selectivity module of FIG. 1. Each status bit possesses the same structure as in the example of FIG. 2.

(20) The length of an information block IB′ therefore corresponds in this case to the length of an information time IZ′. An advantage, when compared with the variant shown in FIG. 2, therefore, includes the halving of the cycle (refresh) time. This is made possible here by the fact that a start bit and a status bit possess level (adjustment) times of different length. In the example, the non-zero level in the start bit is twice as long as in the status or information bit.

(21) The protocol for the status signal can be further varied. For example, the structure of an individual bit can be modified. Furthermore, the levels can also be inverted. In addition, a selectivity module can also possess a different number of channels, e.g., two, three, five, etc., as a result of which the information blocks become correspondingly shorter or longer compared to the illustrated example with four channels.

(22) The binary status signal can be used, for example, for a signal encoding scheme as shown in Table 1.

(23) TABLE-US-00001 TABLE 1 Signal encoding Bit 2.sup.3 Bit 2.sup.2 Bit 2.sup.1 Bit 2.sup.0 Value Channel A B C D 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15

(24) According to this signal encoding scheme, the status of the selectivity module having the four channels can be uniquely represented in a numeric value (0 to 15) from the status or information bits set in each case. Thus, the numeric value zero corresponds to the case when none of the four channels has tripped. The numeric value four corresponds to the case when only channel B has tripped. Furthermore, the numeric value 11 corresponds to the case when channels A, C and D have tripped, and the numeric value 15 corresponds to the case when all channels have tripped.

(25) The data word representing this decimal numeric value can be evaluated and processed further in any PLC. In the example of FIG. 2, the cyclic updating of the numeric value takes place every 4.4 seconds (s), and every 2.2 s in the example of FIG. 3.

(26) Advantageously, a direct assignment of the output status information to the channels is possible by virtue of the serial encoded status signal, thereby enabling possible downtimes of a system to be reduced. Furthermore, a wire break or an interruption to the connection between the selectivity module and a connected PLC can be more reliably detected if the signal transmission takes place cyclically. The PLC can therefore respond accordingly to the absence of the status signal.

(27) It should be emphasized once again as a further advantage over selectivity modules according to the prior art that only a single digital input of a PLC is necessary in order to evaluate the states of a selectivity module. The necessary wiring outlay is also correspondingly reduced, for which reason commensurate cost savings are expected.

(28) The series of detailed descriptions set forth above are only specific descriptions directed to the feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention; and all the equivalent embodiments or modifications made without departing from the technical spirit of the present invention shall be included in the scope of protection of the present invention.