Gate driver circuit

Abstract

In High Voltage CMOS technologies the supply voltage is typically higher than the maximum allowed gate voltage. In a switching output stage of amplifiers such class-D amplifiers and DC-DC converters the gates of the power field effect transistors need to be charged quickly. This requires a gate driver that is capable of delivering large currents without exceeding the maximum allowed voltage on the gate of the power field effect transistors.

Claims

1. A gate driver circuit for switching a power transistor having a gate terminal, the gate driver circuit comprising: a high side portion and a low side portion wherein at least one of said high side or low side portions comprises: a first switch and a second switch; a voltage sensor arranged to detect a voltage at the gate terminal of the power transistor; wherein said voltage sensor is further arranged to switchably operate said first and second switches in response to an input voltage exceeding a threshold voltage, wherein the input voltage is a gate source voltage of said power transistor, and such that said gate terminal is switched between a first voltage and a second voltage; wherein the said first and second switches are arranged such that they are prohibited from conducting simultaneously; wherein the first switch is switchably arranged to apply the first voltage directly to the gate terminal of the power transistor from a supply voltage when the first switch is closed and the second switch is open and the second switch is switchably arranged to apply the second voltage to the gate terminal of the power transistor when the first switch is open and the second switch is closed, wherein the second voltage is a high impedance reference voltage; and wherein the threshold voltage is lower than the supply voltage.

2. The gate driver circuit of claim 1, further comprising a third switch arranged to switchably operate said power transistor.

3. The gate driver circuit of claim 1, wherein said voltage sensor is arranged to generate a control signal to switchably operate said first and said second switches.

4. The gate driver circuit of claim 1, wherein said voltage sensor is a comparator.

5. The gate driver circuit of claim 1, wherein the threshold voltage is a maximum gate source voltage rating of the power transistor.

6. An audio amplifier comprising the gate driver circuit of claim 1.

7. An audio speaker driver comprising the audio amplifier of claim 6.

8. A portable electronic device comprising the audio speaker driver of claim 7.

9. A DC-DC converter comprising the gate driver circuit of claim 1.

10. A method of switching a power transistor, the method comprising: detecting a voltage at a gate terminal of the power transistor; and switching first and second switches in response to an input voltage exceeding a threshold voltage, wherein the input voltage is a gate source voltage of said power transistor, and such that said gate terminal is switched between a first voltage and a second voltage; further comprising stopping charging of the gate terminal when the input voltage reaches the threshold voltage; further comprising either connecting the gate terminal directly to a supply voltage to provide the first voltage by closing the first switch and opening the second switch or connecting the gate terminal to a high impedance reference voltage by opening the first switch and closing the second switch; and wherein the threshold voltage is lower than the supply voltage.

11. The method of claim 10, wherein the threshold voltage is a maximum gate source voltage rating of the power transistor.

12. A gate driver circuit for switching a power transistor having a gate terminal, the gate driver circuit comprising: a high side portion and a low side portion, wherein at least one of said high side or low side portions comprises: a first switch and a second switch; a comparator having inputs connected to the gate terminal and to the source of the power transistor and configured to compare a gate source voltage of the power transistor to a threshold voltage and to output a control signal to switchably operate said first and second switches in response to the gate source voltage exceeding the threshold voltage such that the gate terminal of the power transistor is switched between a first voltage and a second voltage; wherein charging of the gate terminal of the power transistor is stopped when the threshold voltage is reached; and wherein the gate terminal of the power transistor is connected directly to a supply voltage to provide the first voltage when the first switch is closed and the second switch is open and wherein the gate terminal of the power transistor is connected to a high impedance reference voltage when the first switch is open and the second switch is closed to stop charging of the gate terminal; wherein the threshold voltage is lower than the supply voltage.

13. The gate driver of claim 12, wherein the threshold voltage is a maximum gate source voltage rating of the power transistor.

Description

DESCRIPTION OF THE DRAWINGS

(1) In the figures and the following description like reference numerals refer to like features.

(2) The invention is described further hereinafter by way of example only with reference to the accompanying drawings in which:

(3) FIG. 1 shows a class-D amplifier output stage according to the prior art;

(4) FIG. 2 shows a CMOS class-D amplifier output stage according to the prior art;

(5) FIG. 3 show an auxiliary gate driver arrangement according to the prior art;

(6) FIG. 4 is an illustration of the low-side portion of gate driver for a power amplifier;

(7) FIG. 5 is a timing diagram of the gate driver signals during a switching sequence; and

(8) FIG. 6 is a circuit diagram of the low-side portion of gate driver arrangement for a power amplifier.

(9) Referring generally to FIGS. 4 and 6 it should be noted that for clarity purposes they illustrate a low-side portion of the gate driver only. An additional to or instead of, a complementary high-side portion may be included. Based on the teachings of the following disclosure implementing the high-side portion of the gate driver will be routine for the skilled person.

(10) In overview and referring to FIG. 4, the illustrated low side gate driver comprises a charge switch S.sub.CHN and a lock switch S.sub.LCKN. The low side gate driver also comprises an additional switch, illustrated here by way of example, as a pull down transistor M.sub.LN. The skilled person would recognise that the switches as described herein may be implemented, for example, using a current or voltage controlled switches or transistor switches.

(11) The low side gate driver also comprises a comparator COMP and is supplied by a reference voltage supply V.sub.REFN. The charge switch S.sub.CHN switchably connects a supply voltage terminal V.sub.SUP, via a current source I.sub.CHN to the gate of low side power transistor M.sub.L and the drain of pull down transistor M.sub.LN. The comparator is arranged as a voltage sensor, in that it ensures that a maximum predetermined voltage threshold, in the case the gate-source voltage of the power FET M.sub.L is not exceeded.

(12) The lock switch S.sub.LCKN switchably connects the reference voltage terminal V.sub.REFN to the gate of power FET M.sub.L and to the drain of the pull down transistor M.sub.LN. The reference voltage supply terminal V.sub.REFN and the supply voltage terminal V.sub.SUP are switchably connected to the gate of power FET M.sub.L and the drain of the pull down transistor M.sub.LN. It should be noted that the charge switch S.sub.CHN and a lock switch S.sub.LCKN are arranged such that the supply V.sub.REFN and the supply voltage V.sub.SUP are not simultaneously connected to the gate of power FET M.sub.L or to the drain of the pull down transistor M.sub.LN.

(13) The comparator COMP is connected to power FET M.sub.L and the pull down transistor M.sub.LN. The negative terminal of the comparator COMP is connected to the source of the power FET M.sub.L and the source of the pull down transistor M.sub.LN. The pull down transistor is arranged to switch between an on state and an off state, as determined by a control signal, discussed further below.

(14) The positive terminal of the comparator COMP is connected to the gate of the power FET M.sub.L and the drain of the pull down transistor M.sub.LN. The source of the pull down transistor M.sub.LN is connected to the source of the power FET M.sub.L, and the drain of the pull down transistor M.sub.LN is connected to the gate of the power FET M.sub.L.

(15) The charge switch S.sub.CHN and a lock switch S.sub.LCKN are connected such that they share a common node connected to the drain of the pull down transistor M.sub.LN and the gate of the power FET M.sub.L. The gate of the pull down transistor M.sub.LN is connected to a state machine (not illustrated) which provides the control signal “discharge” shown in FIGS. 4, 5 and 6.

(16) The pull down transistor M.sub.LN may be n-channel transistor to short circuit the gate-source of the power FET M.sub.L. Alternatively, a p-channel transistor may be used, however the gate of the pull down transistor M.sub.LN would have to be made negative with respect to ground to achieve the same functionality. Alternatively a current or voltage controlled switch may be used.

(17) As mentioned above, in embodiments the high side portion of the gate driver (not illustrated) with same layout to that of the low side gate driver shown in FIG. 4, can comprise the same circuit elements as the low side, namely: charge and lock switches; a comparator; a pull down transistor; a reference voltage supply, and a current source, each arranged in the same way as for the low-side portion discussed above. These circuit elements may be in addition to or alternative to those provided for the low side arrangement discussed. In the case of the high side driver the circuit elements would be connected to the high side power FET M.sub.H. The skilled person will appreciate therefore that the high side is complementary to the lowside, such that a p-type transistor would be exchanged for an n-type transistor. Circuit elements which are not transistors will be the same as those of the low side portion discussed herein.

(18) The operation of the gate driver can be understood with reference to FIG. 5. FIG. 5 is a timing diagram of a switch-on sequence of the power FET M.sub.L showing the above mentioned control signals and the voltage V.sub.GL applied to the gate of the power FET M.sub.L. In operation, the low side gate driver is arranged to switch the power FET M.sub.L on and off in accordance with control signals “charge”, “lock”, “discharge” and “ready” so that the power FET M.sub.L can drive the output V.sub.OUT of the amplifier.

(19) To switch the power FET M.sub.L on, such that an amplified signal is present at output terminal V.sub.OUT, the pull down transistor M.sub.LN is switched off by a logic “Low” control signal “discharge” at the gate of the pull down transistor M.sub.LN. As a result of the pull down transistor M.sub.LN being switched off any current flow will bypass the pull down transistor M.sub.LN flow to the gate of the power FET M.sub.L and the positive terminal of the Comparator COMP.

(20) At the same time as the “Low” control signal “discharge” is applied to the gate of the pull down transistor the charge switch S.sub.CHN is closed by a logic “High” control signal “charge”. The control signals “charge” and “discharge” can be generated by any appropriate means. For example they may be generated by a logic state machine (not illustrated), which are well known in the art which may be implemented in either hardware or software.

(21) Now the gate of the power FET M.sub.L is connected to the supply voltage V.sub.SUP and is charged by current I.sub.CHN and the power FET M.sub.L is switched on.

(22) When the gate voltage V.sub.GL of the power FET M.sub.L crosses a threshold voltage V.sub.GSMAX of the comparator COMP, the comparator COMP triggers and produces the control signal “ready”. The control signal “ready” causes the control signal “charge” to go “Low” and control signal “lock” to go “High”, thereby respectively opening the charge switch S.sub.CHN and closing the lock switch S.sub.LCKN.

(23) The pull down transistor M.sub.LN is switched off due to the “Low” “discharge” signal, charging of the gate of the power FET M.sub.L stops and reference voltage V.sub.REFN will be applied to the gate of the power FET M.sub.L. If reference voltage V.sub.REFN is equal to the threshold voltage V.sub.GSMAX of the comparator COMP then the current flow through lock switch S.sub.LCKN will be negligible because the gate voltage V.sub.GL of the power FET M.sub.L will be the same as the threshold voltage V.sub.GSMAX due to lock switch S.sub.LCKN being closed.

(24) In circuits of this type, the power FET M.sub.L will generally have a large gate capacitance, typically several hundreds of pico-Farads, due to the relatively large size of the device required to cope with the power requirements of the application. Due to the large gate capacitance the gate voltage of the power FET M.sub.L will remain stable after charge switch S.sub.CHN is opened and charging of the gate of the power FET M.sub.L has stopped. This is due to the switching time of the power FET M.sub.L being proportional it's gate capacitance. In other words, if all current flowing to and from the gate is stopped the charge on the gate capacitance does not change so the voltage on the gate capacitance remains the same. However, due to leakage currents (for example gate leakage currents) the gate voltage floats or drifts from the charged value and this drift is generally a slow (in electronic device operation terms this may be in the region of 1 to 5 seconds) process because leakage currents are generally small (typically for example nano amps).

(25) Therefore, the timing of the switching on of the “lock” signal can be relaxed, because when the charging of the gate of the power FET M.sub.L is stopped the gate floats, that is, it has an extremely high DC-impedance. However, because of the large capacitance it will only change (for example discharge) very slowly due to leakage currents mentioned. Therefore it is not necessary to set the gate voltage of the power FET M.sub.L with the “lock” signal immediately. So the time taken from when the charge switch is switched off to when the lock switch comes on is relaxed.

(26) In addition because the reference voltage supply V.sub.REFN does not need to supply a large peak current due to the gate of the power FET M.sub.L already being charged, the gate of the power FET M.sub.L can be a high impedance node such that there is no need for a low impedance buffer or voltage regulator.

(27) The threshold voltage V.sub.GSMAX of the comparator COMP is determined by the maximum gate source voltage rating of the power FET M.sub.L. The threshold voltage V.sub.GSMAX of the comparator COMP may be chosen such that it equals the maximum gate source voltage rating for the power FET. Alternatively, the threshold voltage V.sub.GSMAX may be chosen such that it less than the gate source voltage rating of the power FET M.sub.L. To switch the power FET M.sub.L off, such that an amplified signal is not present at output terminal V.sub.OUT, the pull down transistor M.sub.LN is switched on by the control signal “discharge” at the gate of the pull down transistor M.sub.LN and charge switch S.sub.CHN and lock switch S.sub.LCKN are opened by control signal “charge” and control signal “lock” respectively. As a result the gate of the power FET M.sub.L is discharged by switching on the pull down transistor M.sub.LN the gate-source of power FET M.sub.L is shorted and the gate capacitance is discharged completely.

(28) The skilled person will recognise that the control signals may be generated by any appropriate means such as for example a logic state-machine (not illustrated). The logic state-machine is arranged such that the signal transitions are produced in the correct sequence and timing. The skilled person will also appreciate that the control signals can be applied to the switches by means of level shifters (not illustrated).

(29) Where the charge switch S.sub.CHN and lock switch S.sub.LCKN are implemented by FETs, the level of the control signal, that is whether “High” or “Low”, required to switch them on or off will be determined by the threshold voltage of the particular FET. Similarly, this is also true for the choice of pull down transistor M.sub.LN and power FET M.sub.L.

(30) In an embodiment, illustrated in the circuit diagram of FIG. 6, the reference voltage supply V.sub.REFN may be implemented using a small reference current source I.sub.REFN and a high, ohmic resistor R.sub.REFN. Decoupling capacitor C.sub.REFN allows reference voltage supply V.sub.REFN to supply other logic circuits such as the level shifters, multiplexers, required to generate the correct control signals.

(31) Lock switch S.sub.LCKN may be implemented using a standard PMOS transistor M.sub.LCKN and charge switch may be implemented using a standard PMOS transistor M.sub.CHN. Similar to the pull-down transistor M.sub.LN the source, gate and drain terminal voltages will never be higher than the gate voltage of power FET M.sub.L such that a low voltage rating FET can be used which tend to be much smaller than FETs with a high voltage rating. Both charge switch S.sub.CHN and current source I.sub.CHN may be implemented by a single PMOS transistor M.sub.CHN, where the drain source voltage may be equal to the supply voltage V.sub.SUP such that it should be of the same drain-source voltage rating as power FET M.sub.L. By driving the gate of M.sub.CHN with an appropriate limited voltage, that is higher than the threshold voltage of the FET the drain current will saturate and therefore behave as a current source.

(32) The high impedance of voltage supply resistor R.sub.REFN relaxes the relationship between reference voltage supply V.sub.REFN and threshold voltage V.sub.GSMAX of the comparator COMP as such the reference voltage V.sub.REFN does not have to be exactly equal to V.sub.GSMAX. When lock switch S.sub.LCKN is closed the gate voltage V.sub.GL of the power FET M.sub.L will converge to reference voltage supply V.sub.REFN. Under normal operation of the gate driver, that is normal operation of the amplifier, power FET M.sub.L is switched on and off periodically in response to the input signal from the amplifier stage (not illustrated) so the effect of driving (or locking) the gate of power FET M.sub.L to reference voltage supply V.sub.REFN is negligible. When the power FET M.sub.L is switched on permanently, for example during testing, the reference voltage supply V.sub.REFN prevents the gate of power FET M.sub.L from floating because the voltage on a floating node can drift away due to leakage and can get a value that can cause damage in the circuit.

(33) The above described components and functionality can be implemented on a single integrated circuit.

(34) In the foregoing discussion the skilled person will recognise that the use of the terms “Low” and “High” may refer to logic low, that is 0, and logic high, that is 1. Also, High and Low indicates that the High control signal is higher than the Low control signal.

(35) Particular and preferred aspects of the invention are set out in the accompanying independent claims. Combinations of features from the dependent and/or independent claims may be combined as appropriate and not merely as set out in the claims.

(36) The scope of the present disclosure includes any novel feature or combination of features disclosed therein either explicitly or implicitly or any generalisation thereof irrespective of whether or not it relates to the claimed invention or mitigate against any or all of the problems addressed by the present invention. The applicant hereby gives notice that new claims may be formulated to such features during prosecution of this application or of any such further application derived there from. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in specific combinations enumerated in the claims.

(37) Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub combination.

(38) In the foregoing discussion, the terms connected or connection refers to electrical connection.

(39) For the sake of completeness it is also stated that the term “comprising” does not exclude other elements or steps, the term “a” or “an” does not exclude a plurality, a single processor or other unit may fulfill the functions of several means recited in the claims and reference signs in the claims shall not be construed as limiting the scope of the claims.