Computation circuit for performing vector-matrix multiplication and semiconductor device including the computation circuit

Abstract

A computation circuit includes a computing cell array configured to provide a plurality of physical values respectively corresponding to a plurality of elements of a matrix; a vector input circuit configured to provide a plurality of input voltages corresponding to an input vector to the computing cell array; and a vector output circuit configured to output a plurality of output voltages each corresponding to a dot product between the input vector and a column vector of the matrix according to the plurality of input voltages and the plurality of effective capacitances.

Claims

1. A computation circuit comprising: a computing cell array configured to provide a plurality of effective capacitances respectively corresponding to a plurality of elements of a matrix; a vector input circuit configured to provide a plurality of input voltages corresponding to an input vector to the computing cell array; and a vector output circuit configured to output a plurality of output voltages each corresponding to a dot product between the input vector and a column vector of the matrix according to the plurality of input voltages and the plurality of effective capacitances, wherein the computing cell array comprises: a plurality of computing cells; a plurality of plate lines; and a plurality of bit lines, wherein each of the plurality of computing cells is located where a respective one of the plurality of plate lines and a respective one of the plurality of the bit lines cross, wherein each of the plurality of computing cells includes a plurality of capacitors selectively coupled between the respective one of the plurality of plate lines and the respective one of the plurality of bit lines; and wherein an effective capacitance between the respective one of the plurality of plate lines and the respective one of the plurality of bit lines respectively corresponds to a value of an element included in the matrix.

2. The computation circuit of claim 1, wherein each of the plurality of computing cells includes: a plurality of MOS transistors configured to selectively couple the plurality of capacitors with the respective one of the plurality of plate lines; and a plurality of nonvolatile transistors configured to respectively determine on or off states of the plurality of MOS transistors.

3. The computation circuit of claim 2, wherein the computing cell array further comprises a plurality of first word lines corresponding to a number of rows of the matrix, and wherein each of the plurality of first word lines is coupled to a gate of a corresponding one of the plurality of MOS transistors through a corresponding one of the plurality of nonvolatile transistors.

4. The computation circuit of claim 3, wherein the computing cell array further comprises a plurality of second word lines, and wherein a gate of each of the plurality of nonvolatile transistors is coupled to one of the plurality of second word lines, and wherein the computing cell array is configured to program each of the plurality of nonvolatile transistors according to a voltage of one of the plurality of second word lines.

5. The computation circuit of claim 4, wherein the computing cell array further comprises a plurality of control lines, and wherein each of the plurality of computing cells further includes: a transistor configured to selectively couple one of the plurality of first word lines to the plurality of nonvolatile transistors of the computing cell according to one of the plurality of control lines, and a plurality transistors respectively selectively coupling gates of the plurality of nonvolatile transistors of the computing cell to respective ones of the plurality of second word lines according to the one of the plurality of control lines.

6. The computation circuit of claim 1, wherein the vector output circuit includes a plurality of element output circuits each configured to generate a respective output voltage among the plurality of output voltages according to a signal provided from a respective one of the plurality of bit lines.

7. The computation circuit of claim 6, wherein each of the plurality of element output circuits includes: a sampling capacitor coupled to the respective one of the plurality of bit lines; and a conversion circuit configured to generate the respective output voltage according to charges charged in the sampling capacitor.

8. The computation circuit of claim 7, wherein each of the plurality of element output circuits further includes: a sampling switch configured to selectively couple the respective one of the plurality of bit lines and the sampling capacitor; and a conversion switch configured to selectively provide charges charged in the sampling capacitor to the conversion circuit.

9. The computation circuit of claim 1, wherein the vector input circuits includes: a plurality of input buffers configured to respectively buffer the plurality of input voltages; and a plurality of input switches configured to selectively provide output voltages of the plurality of input buffers to the computing cell array.

10. The computation circuit of claim 1, further comprising a matrix control circuit configured to set effective capacitances corresponding to each element of the matrix in the computing cell array.

11. A semiconductor device comprising: a command decoder configured to receive a command and an address; a data input/output (IO) buffer configured to input or output data according to a control of the command decoder; and a computation circuit configured to generate a plurality of output voltages corresponding to product of an input vector provided from the data IO buffer and a matrix according to a control of the command decoder, wherein the computation circuit comprises: a computing cell array configured to set and store a plurality of effective capacitances respectively corresponding to the elements of the matrix; a vector input circuit configured to provide a plurality of input voltages corresponding to an input vector to the computing cell array; and a vector output circuit configured to output a plurality of output voltages each corresponding to a dot product between the input vector and a column vector of the matrix according to the plurality of input voltages and the plurality of effective capacitances, wherein the computing cell array comprises: a plurality of computing cells; a plurality of plate lines; and a plurality of bit lines, wherein each of the plurality of computing cells is located where one of the plurality of plate lines and one of the plurality of the bit lines cross, wherein each of the plurality of computing cells includes a plurality of capacitors selectively coupled between one of the plurality of plate lines and one of the plurality of bit lines; and wherein an effective capacitance between one of the plurality of plate lines and one of the plurality of bit lines corresponds to a value of an element included in the matrix.

12. The semiconductor device of claim 11, further comprising a digital to analog converter (DAC) configured to convert a data of the data IO buffer into an input voltage corresponding to an element of the input vector and to provide the input voltage with the computation circuit according to a control of the command decoder.

13. The semiconductor device of claim 11, further comprising an analog to digital converter (ADC) configured to convert the plurality of output voltages into a plurality of output data and provide the output data with the data IO buffer according to a control of the command decoder.

14. The semiconductor device of claim 11, further comprising an element buffer configured to receive element data corresponding to an element of the matrix from the data IO buffer and to buffer the element data according to a control of the command decoder.

15. The semiconductor device of claim 11, wherein each of the plurality of computing cells includes: a plurality of MOS transistors configured to selectively couple, respectively, the plurality of capacitors with the one of the plurality of plate lines; and a plurality of nonvolatile transistors configured to respectively determine an on or off state of the plurality of MOS transistors.

16. The semiconductor device of claim 11, wherein the vector output circuit comprises a plurality of element output circuits, each of the plurality of element output circuits including: a sampling switch configured to selectively couple a respective one of the plurality of bit lines and a sampling capacitor; and a conversion switch configured to selectively provide charges charged in the sampling capacitor to a conversion circuit.

17. The semiconductor device of claim 11, wherein the vector input circuits includes: a plurality of input buffers configured to respectively buffer the plurality of input voltages; and a plurality of input switches configured to selectively provide voltages of the plurality of input buffers, respectively, to the computing cell array.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views, together with the detailed description below, are incorporated in and form part of the specification, and serve to further illustrate embodiments of concepts that include the claimed novelty, and explain various principles and advantages of those embodiments.

(2) FIG. 1 is a block diagram illustrating a neural network.

(3) FIG. 2 is a block diagram illustrating an operation performed in the neural network.

(4) FIG. 3 is a block diagram illustrating a computation circuit according to an embodiment of the present disclosure.

(5) FIG. 4 is a block diagram illustrating a vector input circuit according to an embodiment of the present disclosure.

(6) FIG. 5 is a block diagram illustrating a computing cell array according to an embodiment of the present disclosure.

(7) FIG. 6 is a circuit diagram illustrating a computing cell according to an embodiment of the present disclosure.

(8) FIG. 7 is a block diagram illustrating a matrix control circuit according to an embodiment of the present disclosure.

(9) FIG. 8 is a block diagram illustrating a vector output circuit according to an embodiment of the present disclosure.

(10) FIG. 9 is a circuit diagram illustrating an element output circuit according to an embodiment of the present disclosure.

(11) FIG. 10 is a block diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

(12) The following detailed description references the accompanying figures in describing illustrative embodiments consistent with this disclosure. The embodiments are provided for illustrative purposes and are not exhaustive. Additional embodiments not explicitly illustrated or described are possible. Further, modifications can be made to presented embodiments within the scope of the present teachings. The detailed description is not meant to limit this disclosure. Rather, the scope of the present disclosure is defined in accordance with the presented claims and equivalents thereof.

(13) FIG. 3 is a block diagram illustrating a computation circuit 1 according to an embodiment of the present disclosure.

(14) The computation circuit 1 includes a vector input circuit 100, a computing cell array 200, a matrix control circuit 300, a vector output circuit 400, and a computing control circuit 500.

(15) The computing control circuit 500 controls each component of the computation circuit 1 to perform a program operation or a computation operation.

(16) For example, the computing control circuit 500 may provide an input switch control signal S.sub.1m (1≤m≤i) to the vector input circuit 100 to control a vector input.

(17) In addition, the computing control circuit 500 provides an operation mode signal MODE to the matrix control circuit 300, and provides element data DC.sub.mn and index signals m and n of the matrix so that data corresponding to each element of the matrix may be stored.

(18) In addition, the computing control circuit 500 may provide the vector output circuit 400 with a sampling switch control signal S.sub.2n (1≤n≤j) and a conversion switch control signal S.sub.3n (1≤n≤j) to output the computation result.

(19) Hereinafter, the detailed configuration and operation of the computation circuit 1 will be described with reference to FIGS. 4 to 9.

(20) FIG. 4 is a block diagram illustrating a vector input circuit 100 according to an embodiment of the present disclosure.

(21) The vector input circuit 100 provides a computing cell array 200 with input voltages V.sub.x1, V.sub.x2, . . . , V.sub.xi, where i is a natural number equal to or greater than 2, corresponding to a plurality of elements included in the input vector.

(22) The vector input circuit 100 according to an embodiment of the present disclosure includes input switches 110.sub.1, 110.sub.2, . . . 110.sub.i corresponding to the number of elements of the input vector.

(23) The input switches 110.sub.1, 110.sub.2, . . . 110.sub.i respectively provide analog input voltages V.sub.x1, V.sub.x2, . . . V.sub.xi to the computing cell array 200 in accordance with respective input switch control signals S.sub.11, S.sub.12, . . . S.sub.1i.

(24) The vector input circuit 100 may further include a plurality of input buffers 120.sub.1, 120.sub.2, . . . 120.sub.i which may respectively buffer the analog input voltages V.sub.x1, V.sub.x2, . . . V.sub.xi.

(25) In FIG. 4, an embodiment in which an output signal of the input buffer 120.sub.m is provided to the input switch 110.sub.m is illustrated, where 1≤m≤i, but in another embodiment, the connection order may be changed so that the input switch 110.sub.m may be coupled to the input terminal of the input buffer 120.sub.m.

(26) FIG. 5 is a block diagram illustrating a computing cell array 200 according to an embodiment of the present disclosure.

(27) The computing cell array 200 includes a plurality of computing cells 210.sub.11, 210.sub.12, . . . 210.sub.ij, 210.sub.21, 210.sub.22, . . . 210.sub.2j, . . . , 210.sub.i1, 210.sub.i2, . . . 210.sub.ij, (collectively referred to herein as the plurality of computing cells 210) where i and j are natural numbers greater than 1.

(28) The plurality of computing cells 210 may be arranged in i rows and j columns so that they may correspond to the elements of the matrix which the input vector will be multiplied by to produce the output vector.

(29) The computing cell array 200 includes a plurality of plate lines 220.sub.1, 220.sub.2, . . . 220.sub.i (collectively, plate lines 220), a plurality of first word lines 230.sub.1, 230.sub.2, . . . 230.sub.i (collectively, first word lines 230), a plurality of bit lines 240.sub.1, 240.sub.2, . . . 240.sub.j (collectively, bit lines 240), and a plurality of control lines 250.sub.1, 250.sub.2, . . . 250.sub.j (collectively, control lines 250).

(30) In the present embodiment, the plate lines 220 and the first word lines 230 are arranged in parallel to each other in the row direction, the bit lines 240 and the control lines 250 are arranged in parallel to each other in the column direction, and the plates line 220 and the bit lines 240 are arranged to be perpendicular to each other.

(31) Each computing cell 210.sub.mn intersects with the plate line 220.sub.m, the first word line 230.sub.m, the bit line 240.sub.n, and the control line 250.sub.n, for n in 1 . . . j and m in 1 . . . i.

(32) Although FIG. 5 illustrates one first word line per row, a plurality of second word lines may be further comprised in each row. This will be described in detail with reference to FIG. 6.

(33) The input voltage V.sub.xm corresponding to an element of the input vector is input to each plate line 220.sub.m.

(34) The bit line 240.sub.n is commonly coupled to computing cells of the n-th column, for n in 1 . . . j.

(35) The computing cell 210.sub.mn outputs a signal corresponding to the product of m-th element of the input vector (V.sub.xm, which is input on the plate line 220.sub.m) and (m,n)-th element of the matrix (which value is stored in computing cell 210.sub.mn) to the bit line 240.sub.n, for n in 1 . . . j and m in 1 . . . i.

(36) The signal Q.sub.n output from the bit line 240.sub.n corresponds to the dot product of the input vector and n-th column vector of the matrix; that is, to the sum of the products output to the bit line 240.sub.n by computing cells 210.sub.1n, 210.sub.2n, . . . 210.sub.in, where 1≤n≤j.

(37) The column selection signal V.sub.sn is input to the control line 250.sub.n.

(38) The column selection signal V.sub.sn may be used to program the corresponding elements of the matrix into computing cells of the n-th column of the computing cell array 200, where 1≤n≤j.

(39) A first word line voltage V.sub.wm is applied to the first word line 230.sub.m to program the (m, n)-th element of the matrix to the computing cell 210.sub.mn.

(40) A detailed structure of the computing cell 210.sub.mn and an operation related thereto will be described in detail with reference to FIG. 6.

(41) FIG. 6 is a circuit diagram illustrating a computing cell 210.sub.mn according to an embodiment of the present disclosure.

(42) The computing cell 210.sub.mn includes one or more capacitors C.sub.mn,1, C.sub.mn,2, . . . C.sub.mn,k and one or more NMOS transistors N.sub.mn,1, N.sub.mn,2, . . . N.sub.mn,k, where k is a natural numbers corresponding to a number of bits used to store a value in the computing cell 210.sub.mn.

(43) The capacitor C.sub.mn,p and the NMOS transistor N.sub.mn,p, p in 1 . . . k, are coupled in a form similar to a Dynamic Random Access Memory (DRAM) cell (except that the terminal of the capacitor C.sub.mn,p not coupled to the NMOS transistor N.sub.mn,p is coupled to the plate line 220.sub.m instead of to ground).

(44) That is, one node of the capacitor C.sub.mn,p is coupled to the plate line 220.sub.m, and the source and drain of the NMOS transistor N.sub.mn,p are coupled between the other node of the capacitor C.sub.mn,p and the bit line 240.sub.n.

(45) The gate of the NMOS transistor N.sub.mn,p is coupled to the drain of the floating gate transistor F.sub.mn,p among one or more floating gate transistors F.sub.mn,1, F.sub.mn,2, . . . F.sub.mn,k.

(46) The sources of the floating gate transistors F.sub.mn,1, F.sub.mn,2, . . . F.sub.mn,k are commonly coupled to the source of the switching transistor M.sub.mn.

(47) The drain of the switching transistor M.sub.mn is coupled to the first word line 230.sub.m and the gate of the switching transistor M.sub.mn is coupled to the control line 250.sub.n.

(48) The control gate of the floating gate transistor F.sub.mn,p is coupled to the drain of the switching transistor M.sub.mn,p of the one or more switching transistors M.sub.mn,1, M.sub.mn,2, . . . M.sub.mn,k.

(49) The gate of the switching transistor M.sub.mn,p is coupled to the control line 250.sub.n and the source is coupled to the second word line 232.sub.m,p of the one or more second word lines 232.sub.m,1, . . . 232.sub.m,1, . . . 232.sub.m,k.

(50) As such, the first word line 230.sub.m and the plurality of second word lines 232.sub.m,1, . . . , 232.sub.m,k are coupled to a computing cell 210.sub.mn.

(51) In the present embodiment, the value of the (m, n)-th element of the matrix corresponds to a physical value of the computing cell 210.sub.mn such as the effective capacitance between the plate line 220.sub.m and the bit line 240.sub.n in the computing cell 210.sub.mn.

(52) In this embodiment, the effective capacitance between the plate line 220.sub.m and the bit line 240.sub.n is determined by which capacitors are coupled between the plate line 220.sub.m and the bit line 240.sub.n among the plurality of capacitors C.sub.mn,1 . . . C.sub.mn,k.

(53) The floating gate transistor F.sub.mn,p is configured to control the gate voltage of the NMOS transistor N.sub.mn,p by injecting charges into the floating gate during a program operation or removing charges from the floating gate using an erase operation.

(54) The program operation and the erase operation performed on the computing cell 210.sub.mn may be controlled by the matrix control circuit 300.

(55) During the program operation, a high level signal is applied to the control line 250.sub.n to turn on the switching transistors M.sub.mn, M.sub.mn,1, . . . , M.sub.mn,k.

(56) Accordingly, the first word line 230.sub.m is coupled to the source of the floating gate transistors F.sub.mn,p, and the second word line 232.sub.m,p is coupled to the control gate of the floating gate transistor F.sub.mn,p.

(57) An operation for injecting or removing charges into the floating gate of the floating gate transistor F.sub.mn,p (that is, for programming or erasing the floating gate transistor F.sub.mn,p) is well known in the art.

(58) That is, electrons are injected into the floating gate of the floating gate transistor F.sub.mn,p by applying a positive high voltage to the second word line 232.sub.m,p while the first word line 230.sub.m is grounded. Electrons may be removed from the floating gate of the floating gate transistor F.sub.mn,p by applying a negative high voltage to the second word line 232.sub.m,p.

(59) When electrons are injected into the floating gate, the threshold voltage of the floating gate transistor is increased. Accordingly, a voltage may be applied to the control gate of the floating gate transistor that will turn the floating gate transistor on if electrons have not been injected into the floating gate, but will not turn the floating gate transistor on if a sufficient number of electrons have been injected into the floating gate.

(60) Computing operations may also be controlled by the matrix control circuit 300.

(61) The computing operation determines whether the NMOS transistor N.sub.mn,p is on or off by adjusting the gate voltage of the NMOS transistor N.sub.mn,p according to the result of programming the floating gate transistor F.sub.mn,p, and accordingly determines whether one or more of the capacitors C.sub.mn,1 . . . C.sub.mn,k are conductively coupled between the plate line 220.sub.m and the bit line 240.sub.n.

(62) In computing operation, a high level signal is applied to the control line 250.sub.n to turn on the switching transistors M.sub.mn, M.sub.mn,1, . . . , M.sub.mn,k.

(63) The power supply voltage VDD is applied to the first word line 230.sub.m and second word lines 232.sub.m,1, . . . , 232.sub.m,k during the computing operation.

(64) Accordingly, the floating gate transistor in which electrons are injected into the floating gate thereof is not turned on, which results in the corresponding NMOS transistor being not turned on, and the floating gate transistor in which electrons are not injected into the floating gate thereof is turned on, which results in the corresponding NMOS transistor being turned on to conductively couple the corresponding capacitor between a corresponding plate line and a corresponding bit line.

(65) The sum of capacitances of the capacitors corresponding to the floating gate transistors in which no electrons are injected into the floating gates thereof in the computing cell 210.sub.mn, that is, the effective capacitance C.sub.mn of the computing cell 210.sub.mn, corresponds to the value of (m, n)-th element of the matrix.

(66) The effective capacitance may be variously determined by increasing the number of capacitors included in the computing cell 210.sub.mn. The capacitors included in the computing cell 210.sub.mn may be set to have an identical capacitance or different capacitances. These can be changed according to embodiments. For example, in an embodiment each capacitor C.sub.mn,p has a capacitance equal to c*2.sup.(p-1) for p in 1 . . . k, where c is a constant, so that the effective capacitance C.sub.mn may be determined by programming a binary number into the floating gate transistors F.sub.mn,1 . . . F.sub.mn,k. In another embodiment, some of the floating gate transistors F.sub.mn,1 . . . F.sub.mn,k may be coupled to more than one transistor-capacitor chain, such that some of the floating gate transistors F.sub.mn,1 . . . F.sub.mn,k respectively control whether more than one capacitor is conductively coupled between a corresponding plate line and a corresponding bit line. For example, each floating gate transistors F.sub.mn,p, for p in 1 . . . k, may control 2.sup.(p-1) capacitors through associated transistors, so that the effective capacitance C.sub.mn may be determined by programming a binary number into the floating gate transistors F.sub.mn,1 . . . F.sub.mn,k.

(67) The computing result in each computing cell 210.sub.mn corresponds to the product of the input voltage V.sub.xm input to the plate line 220.sub.m and the effective capacitance C.sub.mn, which corresponds to the amount of charge charged in the capacitor.

(68) Since the bit line 240.sub.n and the control line 250.sub.n are common to a plurality of computing cells in the same column, the program operation and the computing operation may be performed on a per-column basis. In an embodiment performing a matrix multiplication operation, the computing operation for each column may be performed simultaneously with the computing operation of the other columns.

(69) In addition, since the operation is performed on a column basis, a positive charge corresponding to the dot product of the input vector and the n-th column vector of the matrix may be output from the n-th bit line 240.sub.n. That is, each computing cell 210.sub.mn, for m in 1 . . . i, coupled to the n-th bit line 240.sub.n and programmed to have an effective capacitance corresponding to the matrix value W.sub.mn contributes a charge corresponding to a voltage value of the plate line 220.sub.m to which it is coupled multiplied by its effective capacitance. The contributed charge of the computing cell 210.sub.mn therefor corresponding to x.sub.m.Math.W.sub.mn. The total contribution of charge to the bit line 240.sub.n corresponds to the sum of the charges produced by the computing cells coupled thereto: x.sub.1.Math.W.sub.1n+x.sub.2.Math.W.sub.2n+ . . . x.sub.i.Math.W.sub.in.

(70) FIG. 7 is a block diagram illustrating a matrix control circuit 300 according to an embodiment of the present disclosure.

(71) The matrix control circuit 300 programs the floating gate transistors as described above with respect to the plurality of computing cells included in the computing cell array 200 to determine an effective capacitance corresponding to each computing cell.

(72) The matrix control circuit 300 provides a plurality of column selection signals V.sub.sn to select columns for performing program operations and computing operations, and provides first word line voltages V.sub.wm and second word line voltages V.sub.wm,p to provide values for programming the floating gate transistors of the computing cells.

(73) The matrix control circuit 300 may perform a program operation or a computing operation by receiving an operation mode signal MODE. The matrix control circuit 300 may receive element data DC.sub.mn corresponding to each computing cell and determine a first word line voltage V.sub.wm and the second word line voltages V.sub.wm,p during a program operation.

(74) Determining which of the NMOS transistor N.sub.mn,p are to be turned on according to the value of the element data DC.sub.mn may be performed in variously ways by those skilled in the art, and correspondingly, the values of the first word line voltage V.sub.wm and second word line voltages V.sub.wm,p to be provided in the program operation may be easily determined by a person skilled in the art from the above-described disclosure, and thus a detailed description thereof will be omitted.

(75) Whether an n.sup.th column performs a program operation or a computing operation may be determined by adjusting the level of the column selection signal V.sub.sn.

(76) The computing control circuit 500 may control the matrix control circuit 300 to perform a program operation or a computing operation.

(77) FIG. 8 is a block diagram illustrating a vector output circuit 400 according to an embodiment of the present disclosure.

(78) The vector output circuit 400 includes a plurality of element output circuits 410.sub.1, 410.sub.2, . . . 410.sub.j.

(79) As described above, the charge amount Q.sub.n output from the bit line 240.sub.n corresponds to the dot product of the input vector and the n-th column vector of the matrix.

(80) The element output circuits 410.sub.n, n in 1 . . . j, converts the charge amount Q.sub.n into an output voltage V.sub.hn corresponding to the dot product of the input vector and the n-th column vector of the matrix and outputs the output voltage V.sub.hn.

(81) FIG. 9 is a circuit diagram illustrating an element output circuit 410.sub.n according to an embodiment of the present disclosure.

(82) The element output circuit 410.sub.n includes a sampling capacitor C.sub.sn, a sampling switch 411.sub.n, a conversion switch 412.sub.n, and a conversion circuit 413.sub.n.

(83) In this embodiment, the sampling switch 411.sub.n is controlled according to the sampling switch control signal S.sub.2n, and the conversion switch 412.sub.n is controlled according to the conversion switch control signal S.sub.3n.

(84) In the present embodiment, the sampling switch 411.sub.n is turned off and then turned on after the input switch 110.sub.m of FIG. 4 is turned on to charge the capacitors C.sub.mn, 1, . . . , C.sub.mn, k of FIG. 6.

(85) Accordingly, the charge Q.sub.n transferred through the bit line 240.sub.n is transferred to the sampling capacitor C.sub.sn.

(86) After the sampling switch 411.sub.n is turned off and the conversion switch 412.sub.n is turned on, the conversion circuit 413.sub.n generates an output voltage V.sub.hn corresponding to the charge charged in the sampling capacitor C.sub.sn.

(87) In the present embodiment, the conversion circuit 413.sub.n is an amplifier circuit including an operational amplifier 414.sub.n and a feedback capacitor C.sub.fn and generates an output voltage V.sub.hn corresponding to the capacitance of the sampling capacitor C.sub.sn and the feedback capacitor C.sub.fn and buffers the output voltage V.sub.hn.

(88) As described above, the element output circuit 410.sub.n including the conversion circuit 413.sub.n adjusts the signal such that the output voltage V.sub.hn has a value corresponding to the dot product of the input vector and the n-th column vector of the matrix.

(89) FIG. 10 is a block diagram illustrating a semiconductor device 1000 according to an embodiment of the present disclosure.

(90) The semiconductor device 1000 according to the embodiment of the present disclosure includes a structure similar to that of a semiconductor memory device such as a DRAM.

(91) The semiconductor device 1000 includes a command decoder 2 and a data input/output (IO) buffer 3.

(92) The semiconductor device 1000 according to an embodiment of the present disclosure may further include a computation circuit 1, a digital to analog converter (DAC) 4, an element buffer 5, and an analog to digital converter (ADC) 6.

(93) Since the configuration and operation of the computation circuit 1 are as described above, detailed description thereof is omitted.

(94) The command decoder 2 controls the computation circuit 1, the data IO buffer 3, the DAC 4, the element buffer 5, and the ADC 6 according to the command and the address.

(95) The command decoder 2 receives a command and an address from the memory controller.

(96) In this case, the command may include a read command, a write command (a program command), a computation command, and etc.

(97) Write commands include a vector write command for writing an input vector and a matrix write command for writing a matrix.

(98) Input data D.sub.xm, for m in 1 . . . i, corresponding to elements included in the input vector may be provided to the data IO buffer 3 by executing vector write commands.

(99) In this case, the address corresponding to the vector write command may include information on the element number m of the input vector.

(100) In the present embodiment, the input data D.sub.xm is a digital signal and the command decoder 2 controls the DAC 4 to generate an input voltage V.sub.xm corresponding to the input data D.sub.xm and to provide the input voltage V.sub.xm to the computation circuit 1 when a vector write command is provided. In an embodiment, the DAC 4 produces a plurality of input voltages V.sub.xm each corresponding to a respective input data D.sub.xm, for m in 1 . . . i.

(101) The vector input circuit 100 may maintain the input voltages V.sub.xm using the buffer 120.sub.m.

(102) By executing a matrix write command, element data DC.sub.mn corresponding to an element included in the matrix may be provided to the element buffer 5.

(103) In this case, the address corresponding to the matrix write command may include a row number and a column number corresponding to the element of the matrix.

(104) The computation circuit 1 programs a plurality of floating gate transistors of a computing cell 210.sub.mn included in the computing cell array 200 according to the element data DC.sub.mn provided from the element buffer 5 and the commands and addresses provided from the command decoder 2.

(105) The computing command indicates that a multiplication of the matrix and the input vector currently input is to be performed.

(106) Accordingly, the command decoder 2 controls the computation circuit 1 to perform computing operations.

(107) In the computing operation, when the column select signal V.sub.sn and the first and second word line voltages V.sub.wm and V.sub.wm, p are applied, depending on whether charge has been injected into the respective floating gates of the floating gate transistors of the computing cell 210.sub.mn, effective capacitance C.sub.mn of the computing cell 210.sub.mn is determined.

(108) For the computing operation, the input switch 110.sub.m of FIG. 4 is turned on while the sampling switch 411.sub.n of FIG. 9 is turned off to charge the capacitor C.sub.mn,p of the computing cell 210.sub.mn according to the input voltage V.sub.xm.

(109) Thereafter, the sampling switch 411.sub.n is turned on to charge the sampling capacitor C.sub.sn according to the charge Q.sub.n provided from the bit line 240.sub.n.

(110) Thereafter, the sampling switch 411n is turned off and the conversion switch 412.sub.n is turned on to generate the output voltage V.sub.hn.

(111) The read command corresponds to an operation of outputting an output voltage V.sub.hn corresponding to each element of the output vector.

(112) In the read command, the corresponding address may indicate an element number of the output vector to be read.

(113) When a read command is provided, the output voltage V.sub.hn corresponding to the element number is provided by the computation circuit 1 and converted into the output data D.sub.hn by the ADC 6, and the converted data is output through the data IO buffer 3.

(114) Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made to the described embodiments without departing from the spirit and scope of the disclosure as defined by the following claims.