Method for fabricating magnetic tunneling junction element with a composite capping layer

Abstract

A method for fabricating a magnetic tunneling junction (MTJ) element is disclosed. A substrate is provided. A reference layer is formed on the substrate. A tunnel barrier layer is formed on the reference layer. A free layer is formed on the tunnel barrier layer. A composite capping layer is formed on the free layer. The composite capping layer comprises an amorphous layer, a light-element sink layer, and/or a diffusion-stop layer. The reference layer, the tunnel barrier layer, the free layer, and the composite capping layer constitute an MTJ stack.

Claims

1. A method for fabricating a magnetic tunneling junction (MTJ) element, comprising: providing a substrate; forming a reference layer on the substrate; forming a tunnel barrier layer on the reference layer; forming a free layer on the tunnel barrier layer; and forming a composite capping layer on the free layer, wherein the composite capping layer comprises an amorphous layer, a light-element sink layer, and a diffusion-stop layer; wherein the light-element sink layer is provided on the amorphous layer and the diffusion-stop layer is provided on the light-element sink layer, wherein the composite capping layer is in direct contact with the free layer and forms a first interface with the free layer, wherein the composite capping layer is in direct contact with a top electrode and forms a second interface with the top electrode, and wherein the top electrode is a ruthenium top electrode having a hexagonal close packed (hcp) crystalline structure, wherein the reference layer, the tunnel barrier layer, the free layer, and the composite capping layer constitute an MTJ stack, wherein the amorphous layer comprises a magnetic metal comprising CoFeB, FeB or CoB, and the light-element sink layer comprises Fe based alloy, and wherein the diffusion-stop layer comprises Mo, W or alloys thereof.

2. The method according to claim 1, wherein the composite capping layer is in direct contact with a non-magnetic layer of the free layer.

3. The method according to claim 1, wherein the composite capping layer is in direct contact with a cap layer of the free layer.

4. The method according to claim 3, wherein the cap layer of the free layer comprises MgO.

5. The method according to claim 1, wherein the amorphous layer is made of metals having amorphous structure and has a thickness of about 0.1 nm to 5.0 nm.

6. The method according to claim 1, wherein the tunnel barrier layer comprises an insulator comprising MgO, AlO.sub.x, MgAlO, MgZnO, HfO, or any combination thereof.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:

(2) FIG. 1 is a schematic, cross-sectional diagram showing an exemplary 1T1MTJ structure of a MRAM device according to a non-limiting embodiment of the present invention;

(3) FIG. 2 and FIG. 3 illustrate two exemplary configuration of the free layer of the MTJ element in FIG. 1;

(4) FIG. 4 is an enlarged, cross-sectional diagram showing the MTJ element with the composite capping layer according to one embodiment of the invention; and

(5) FIG. 5 to FIG. 13 are schematic, cross-sectional diagrams showing an exemplary method for fabricating the MTJ element with the composite capping layer according to one embodiment of the invention.

(6) It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings are exaggerated or reduced in size, for the sake of clarity and convenience. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.

DETAILED DESCRIPTION

(7) Advantages and features of embodiments may be understood more readily by reference to the following detailed description of preferred embodiments and the accompanying drawings. Embodiments may, however, be embodied in many different forms and should not be construed as being limited to those set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey exemplary implementations of embodiments to those skilled in the art, so embodiments will only be defined by the appended claims. Like reference numerals refer to like elements throughout the specification.

(8) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(9) It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on”, “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

(10) Embodiments are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, these embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the embodiments.

(11) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(12) The present disclosure pertains to an improved magnetic tunneling junction (MTJ) element of a magnetoresistive random access memory (MRAM) device such as a spin-transfer torque magnetoresistive random access memory (STT-MRAM) device. STT-MRAM is a non-volatile memory, which has several advantages over the conventional magnetoresistive random access memory. For example, these advantages include higher scalability, lower-power consumption, and faster operating speed. Spin transfer torque is an effect in which the orientation of a magnetic layer in a magnetic tunnel junction or spin valve can be modified using a spin-polarized current. STT-MRAM uses electrons that become spin-polarized as the electrons pass through a thin film (spin filter). During a write operation, the spin-polarized electrons exert torque on a free layer, which switches a polarity of the free layer. During a read operation, a current detects the resistance/logic state of the MTJ storage element.

(13) The present disclosure is characterized in that the MTJ element comprises a composite capping layer interposed between a free layer of the MTJ element and a top electrode/via disposed on the MTJ element. The top electrode/via may be composed of ruthenium (Ru) and may have a hexagonal close packed (hcp) crystalline structure. For example, the top electrode/via electrically connects the MTJ element to an overlying bit line.

(14) For example, an MRAM device may include memory cells composed of synthetic anti-ferromagnet (SAF). The SAF denotes a layered ferromagnetic structure in which adjacent ferromagnetic layers are antiferromagnetically coupled. For example, an MTJ element may be provided at an intersection of a word line and a bit line. Generally, the MTJ element may be composed of an antiferromagnetic layer, a fixed magnetic layer (or a reference layer), a tunnel barrier layer and a free magnetic layer (or a free layer).

(15) Materials used to form MTJ stacks of a MRAM device generally exhibit high tunneling magneto resistance (TMR), high perpendicular magnetic anisotropy (PMA) and good data retention. MTJ structures may be made in a perpendicular orientation, referred to as perpendicular magnetic tunnel junction (pMTJ) devices. A stack of materials (e.g., cobalt-iron-boron (CoFeB) materials) with a dielectric barrier layer (e.g., magnesium oxide (MgO)) may be used in a pMTJ structure. For example, a pMTJ structure including a stack of materials (e.g., CoFeB/MgO/CoFeB) may be considered for use in MRAM structures.

(16) FIG. 1 is a schematic, cross-sectional diagram showing an exemplary one-transistor-one-MTJ (1T1MTJ) structure of a MRAM device 1 according to a non-limiting embodiment of the present invention. As shown in FIG. 1, the MRAM device 1 comprises a substrate 10 having a top surface 10a. For example, the substrate 10 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, or any suitable semiconductor substrates known in the art.

(17) According to one embodiment, an access transistor 100 may be formed on the top surface 10a of the substrate 10. The access transistor 100 may comprise a drain doping region 102 and a source doping region 104 spaced apart from the drain doping region 104. The drain doping region 102 and the source doping region 104 may be formed by ion implantation process and may be formed in the substrate 10. A channel region 103 may be formed between the drain doping region 102 and the source doping region 104. A gate 106 may be formed over the channel region 103. A gate dielectric layer 108 such as a silicon oxide layer may be formed between the gate 106 and the channel region 103.

(18) It is to be understood that the MRAM device 1 may comprise peripheral circuits for supporting the MRAM memory array. The peripheral circuits may be formed in a logic circuit area, which is not shown for the sake of simplicity.

(19) An inter-layer dielectric (ILD) layer 110 such as an ultra-low k (ULK) dielectric layer may be deposited over the substrate 10. The ILD layer 110 covers the gate 106, the drain doping region 102, and the source doping region 104 of the transistor 100. A contact plug 112 and a contact plug 114 may be formed directly on the drain doping region 102 and the source doping region 104, respectively, in the ILD layer 110. For example, the contact plug 112 and the contact plug 114 may comprise Cu, Ti, TiN, Ta, TaN, W, alloys or combinations thereof, but is not limited thereto. An inter-layer dielectric (ILD) layer 120 may be deposited over the ILD layer 110.

(20) According to one embodiment, a cylindrical memory stack 20 may be formed on the contact plug 112 in the ILD layer 120. The cylindrical memory stack 20 may comprise a magnetic tunneling junction (MTJ) element 200 sandwiched by a bottom electrode 122 and a top electrode 322. The MTJ element 200 is electrically coupled to the drain doping region 102 through the bottom electrode 122 and the contact plug 112. For example, the bottom electrode 122 may comprise NiCr, Ru, Cu, Ta, TaN, Ti, TiN, or any combination thereof.

(21) According to one embodiment, the MTJ element 200 may comprise layered structure including, but not limited to, a reference layer (or pinned layer) 210, a tunnel barrier layer 220 stacked directly on the reference layer 210, and a free layer 230 stacked directly on the tunnel barrier layer 220. According to one embodiment, the reference layer 210 may comprise a pinned layer, an anti-ferromagnetic (AFM) layer, and a polarization enhancement layer (PEL), but is not limited thereto.

(22) For example, the reference layer 210 may be formed of a magnetic material comprising Co and Fe, including but not limited to CoFeB, CoFeBTi, CoFeBZr, CoFeBHf, CoFeBV, CoFeBTa, CoFeBCr, CoFeNi, CoFeTi, CoFeZr, CoFeHf, CoFeV, CoFeNb, CoFeTa, CoFeCr, CoFeMo, CoFeW, CoFeAl, CoFeSi, CoFeGe, CoFeP, or any combination thereof. Moreover, the reference layer 210 may also have a magnetic superlattice structure comprising repeated alternating layers of two or more materials, such as but not limited to (Co/Pt).sub.n, (Co/Pd).sub.n, (Co/Ni).sub.n, (CoFe/Pt).sub.n, (Co/Pt(Pd)).sub.n, or any combination thereof. Alternatively, the reference layer 210 may be formed of a magnetic material comprising Co and Cr, including but not limited to CoCr, CoCrB, CoCrPt, CoCrPtB, CoCrPd, CoCrTi, CoCrZr, CoCrHf, CoCrV, CoCrNb, CoCrTa, or any combination thereof.

(23) According to one embodiment, the tunnel barrier layer 220 may comprise an insulator, including but not limited to MgO, AlO.sub.x, MgAlO, MgZnO, HfO, or any combination thereof. According to one embodiment, the tunnel barrier layer 220 may have a thickness of about 0.5 nm-3.0 nm.

(24) According to one embodiment, the free layer 230 may comprise ferromagnetic materials. For example, the free layer 230 may be a single layer or multi-layer structure. For example, the free layer 230 may comprise Fe, Co, B, Ni, or any combination thereof. For example, the free layer 230 may be formed of a magnetic material including but not limited to CoFeB, CoFeBTi, CoFeBZr, CoFeBHf, CoFeBV, CoFeBTa, CoFeBCr, CoFeNi, CoFeTi, CoFeZr, CoFeHf, CoFeV, CoFeNb, CoFeTa, CoFeCr, CoFeMo, CoFeW, CoFeAl, CoFeSi, CoFeGe, CoFeP, or any combination thereof.

(25) FIG. 2 and FIG. 3 illustrate two exemplary configuration of the free layer 230 of the MTJ element in FIG. 1. In FIG. 2, the free layer 230 comprises a ferromagnetic layer FM disposed directly on the tunnel barrier layer 220. For example, the tunnel barrier layer 220 may be made of MgO. A non-magnetic layer NM may be disposed directly on the ferromagnetic layer FM. This type of free layer has advantages of small damping compared with other PMA materials and high TMR in MgO-based MTJ. However, the free layer in FIG. 2 has limited thickness (˜15 angstroms), thus low PMA. In FIG. 3, the free layer 230 comprises a non-magnetic spacer layer SP is sandwiched by two ferromagnetic layers FM1 and FM2. The spacer layer SP may comprise Ta, Mo, W, Ir, Rh, Zr, Nb, Hf, Cr, V, Bi, any combination thereof, or an alloy with one or more of CFe, Co, Ni, Mn, or other magnetic elements. For example, the spacer layer SP may have a thickness of about 0.1 nm to 2.0 nm. A cap layer CA may be disposed on top of the ferromagnetic layer FM2. For example, the cap layer CA may be composed of MgO, AlOx, TiOx, HfOx, MgAlOx, MgZnOx, SiOx, TaOx, VOx, or any combination thereof. The interface between the ferromagnetic layer FM2 and the cap layer CA enhances PMA. The cap layer CA may have a resistance-area product (RA) less than that of the tunnel barrier layer 220. The cap layer CA may have a thickness of about 0.1 nm to 2.0 nm.

(26) According to one embodiment, the MTJ element 200 may further comprise a composite capping layer 240 interposed between the top electrode 322 and the free layer 230. According to one embodiment, the top electrode 322 may be made of ruthenium (Ru) having a hexagonal close packed (hcp) crystalline structure. The top electrode 322 also acts as an etching stopper, for example, during an ion beam etching process. The MTJ element 200 is electrically connected to an overlying bit line 420 through the top electrode 322. As previously described, the hcp crystalline structure of the Ru top electrode 322 adversely affects the underlying free layer and may cause magneto-resistance (MR) drop and increase of the distribution of coercivity (Hc) of the free layer. The present disclosure addresses these issues by providing the composite capping layer 240 between the top electrode 322 and the free layer 230.

(27) The composite capping layer 240 between the top electrode 322 and the free layer 230 can provide the following advantages. First, the high Hk of the free layer 230 and high TMR ratio of the MTJ element 200 can be maintained. Second, the composite capping layer 240 also acts as a diffusion barrier layer that can block element diffusion from the top electrode/via. Third, the composite capping layer 240 also acts as a crystalline barrier that can avoid the hcp crystalline structure of the top electrode from affecting the free layer.

(28) FIG. 4 is an enlarged, cross-sectional diagram showing the MTJ element 200 with the composite capping layer 240 according to one embodiment of the invention, wherein like numeral numbers designate like regions, elements or layers. As shown in FIG. 4, the composite capping layer 240 may comprise a combination of at least two of different functional layers including an amorphous layer 241, a light-element sink layer 242, and a diffusion-stop layer 243. For illustration purposes, the three layers 241˜243 are all shown in FIG. 4. The order of these layers 241, 242, and 243 can be arranged differently based on the required functions, and of the composite capping layer 240 may have more than one of each of these layers 241, 242, and 243 if certain property needs be enhanced. The composite capping layer 240 is in direct contact with the free layer 230 and forms an interface 240a with the free layer 230. The composite capping layer 240 is in direct contact with the top electrode 322 and forms an interface 240b with the top electrode 322.

(29) In a case that the free layer 230 has a structure as depicted in FIG. 2, the composite capping layer 240 is in direct contact with the non-magnetic layer NM. In a case that the free layer 230 has a structure as depicted in FIG. 3, the composite capping layer 240 is in direct contact with the capping layer CA such as MgO.

(30) According to one embodiment, the amorphous layer 241 is made of metals having amorphous structure and may have a thickness of about 0.1 nm to 5.0 nm. For example, the amorphous layer 241 may comprise a non-magnetic metal such as Ta, Ti or Al, a magnetic metal such as CoFeB, FeB or CoB, or an oxide such as AlO, MgO, TaO.sub.2 or RuO, but is not limited thereto.

(31) According to one embodiment, the light-element sink layer 242 is made of metals having ability of absorbing light elements such as B diffused from the free layer 230. For example, the light-element sink layer 242 may comprise a non-magnetic metal such as Ta, Ti or Zr or a magnetic material such as Fe or its alloys, but is not limited thereto. According to one embodiment, the light-element sink layer 242 may have a thickness of about 0.1 nm to 5.0 nm.

(32) According to one embodiment, the diffusion-stop layer 243 is made of materials that is capable of preventing elements from diffusing into the free layer at high temperature of above 400° C. For example, the diffusion-stop layer 243 may comprise non-magnetic metals such as Ru, Mo, W or their alloys or oxides such as MgO, TaO, AlO, but is not limited thereto. According to one embodiment, the diffusion-stop layer 243 may have a thickness of about 0.1 nm to 5.0 nm.

(33) It is advantageous to use the present disclosure because the composite capping layer 240 between the top electrode 322 and the free layer 230 can maintain high Hk of the free layer. Besides, the crystalline of the Ru top electrode can be effectively suppressed by the amorphous layer 241, thus the distribution of Hc and TMR ratio of the MRAM device 1 can be significantly improved. Furthermore, by using the light-element sink layer 242 in the composite capping layer 240, the MR ratio can be improved.

(34) FIG. 5 to FIG. 13 are schematic, cross-sectional diagrams showing an exemplary method for fabricating the MTJ element with the composite capping layer, which is compatible with current MRAM fabrication processes, according to one embodiment of the invention. As shown in FIG. 5, a substrate 10 having a top surface 10a is provided. For example, the substrate 10 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, or any suitable semiconductor substrates known in the art. For the sake of simplicity, only the region for forming the MTJ element is shown in FIG. 5 to FIG. 13. It is understood that peripheral circuits for supporting the MRAM memory array may be formed on the substrate 10. The peripheral circuits may be formed in a logic circuit area, which is not shown in FIG. 5 to FIG. 13. The access transistor as depicted in FIG. 1 is also omitted through FIG. 5 to FIG. 13.

(35) According to one embodiment, a metal interconnect 12 such as a copper meta line may be formed in an interlayer dielectric (ILD) layer 11 on the substrate 10. The metal interconnect 12 may be electrically connected to a terminal of a transistor (not shown) that is fabricated on the substrate 10. Another ILD layer 13 may be deposited on the metal interconnect 12. The ILD layers 11 and 13 may comprise ultra-low k dielectric materials that have a dielectric constant (k) lower than 2.5. For example, the ILD layers 11 and 13 may comprise carbon-doped oxide (CDO) or SiCOH, but is not limited thereto.

(36) A lithographic process and an etching process may be carried out to form a via hole 14a in the ILD layer 13. The via hole 14a is situated directly above the metal interconnect 12. Subsequently, a metal fill process is performed to fill the via hole 14a with meal such as W, Cu, Ta, or TaN, which is then polished by chemical mechanical polishing (CMP) to thereby form a via 14 in the via hole 14a. The via 14 may function as a bottom electrode.

(37) As shown in FIG. 6, subsequently, a spacer layer SP is deposited on the ILD layer 13 and the via 14. For example, the spacer layer SP may comprise a non-magnetic material including but not limited to one of TiN, TaN, Ta, or Ti. After the deposition of the spacer layer, a CMP process may be performed to polish the top surface of the spacer layer SP.

(38) As shown in FIG. 7, subsequently, the MTJ stack MS is fabricated on the spacer layer SP by sequentially forming a seed layer SE, a reference layer 210, a tunnel barrier layer 220, a free layer 230, and a composite cap layer 240. The seed layer SE may be a layer of NiCr, NiFe, Pt, Ru, or NiFeCr, for example. In one embodiment, the seed layer may be grown on a bottom conductor with an amorphous Ta capping layer, but is not limited thereto. The reference layer 210 may comprise a pinned layer, an anti-ferromagnetic (AFM) layer, and a polarization enhancement layer (PEL), but is not limited thereto. After forming the composite capping layer 240, a hard mask layer HM such as Ru is deposited on the composite capping layer 240. The hard mask layer HM also functions as a top electrode.

(39) For example, the reference layer 210 may be formed of a magnetic material comprising Co and Fe, including but not limited to CoFeB, CoFeBTi, CoFeBZr, CoFeBHf, CoFeBV, CoFeBTa, CoFeBCr, CoFeNi, CoFeTi, CoFeZr, CoFeHf, CoFeV, CoFeNb, CoFeTa, CoFeCr, CoFeMo, CoFeW, CoFeAl, CoFeSi, CoFeGe, CoFeP, or any combination thereof. Moreover, the reference layer 210 may also have a magnetic superlattice structure comprising repeated alternating layers of two or more materials, such as but not limited to (Co/Pt).sub.n, (Co/Pd).sub.n, (Co/Ni).sub.n, (CoFe/Pt).sub.n, (Co/Pt(Pd)).sub.n, or any combination thereof. Alternatively, the reference layer 210 may be formed of a magnetic material comprising Co and Cr, including but not limited to CoCr, CoCrB, CoCrPt, CoCrPtB, CoCrPd, CoCrTi, CoCrZr, CoCrHf, CoCrV, CoCrNb, CoCrTa, or any combination thereof.

(40) According to one embodiment, the tunnel barrier layer 220 may comprise an insulator, including but not limited to MgO, AlO.sub.x, MgAlO, MgZnO, HfO, or any combination thereof. According to one embodiment, the tunnel barrier layer 220 may have a thickness of about 0.5 nm-3.0 nm.

(41) According to one embodiment, the free layer 230 may comprise ferromagnetic materials. For example, the free layer 230 may be a single layer or multi-layer structure. For example, the free layer 230 may comprise Fe, Co, B, Ni, or any combination thereof. For example, the free layer 230 may be formed of a magnetic material including but not limited to CoFeB, CoFeBTi, CoFeBZr, CoFeBHf, CoFeBV, CoFeBTa, CoFeBCr, CoFeNi, CoFeTi, CoFeZr, CoFeHf, CoFeV, CoFeNb, CoFeTa, CoFeCr, CoFeMo, CoFeW, CoFeAl, CoFeSi, CoFeGe, CoFeP, or any combination thereof.

(42) The composite cap layer 240 may comprise a combination of at least two of different functional layers including an amorphous layer 241, a light-element sink layer 242, and a diffusion-stop layer 243. For example, the tri-layer structure of the composite cap layer 240 is shown in FIG. 4. The order of these layers 241, 242, and 243 can be arranged differently based on the required functions, and of the composite capping layer 240 may have more than one of each of these layers 241, 242, and 243 if certain property needs be enhanced. The composite capping layer 240 is in direct contact with the free layer 230.

(43) According to one embodiment, the amorphous layer 241 is made of metals having amorphous structure and may have a thickness of about 0.1 nm to 5.0 nm. For example, the amorphous layer 241 may comprise a non-magnetic metal such as Ta, Ti or Al, a magnetic metal such as CoFeB, FeB or CoB, or an oxide such as AlO, MgO, TaO.sub.2 or RuO, but is not limited thereto.

(44) According to one embodiment, the light-element sink layer 242 is made of metals having ability of absorbing light elements such as B diffused from the free layer 230. For example, the light-element sink layer 242 may comprise a non-magnetic metal such as Ta, Ti or Zr or a magnetic material such as Fe or its alloys, but is not limited thereto. According to one embodiment, the light-element sink layer 242 may have a thickness of about 0.1 nm to 5.0 nm.

(45) According to one embodiment, the diffusion-stop layer 243 is made of materials that is capable of preventing elements from diffusing into the free layer at high temperature of above 400° C. For example, the diffusion-stop layer 243 may comprise non-magnetic metals such as Ru, Mo, W or their alloys or oxides such as MgO, TaO, AlO, but is not limited thereto. According to one embodiment, the diffusion-stop layer 243 may have a thickness of about 0.1 nm to 5.0 nm.

(46) As shown in FIG. 8, a lithographic process and an etching process may be performed to pattern the hard mask layer HM. The patterned hard mask HM acts as an etch stopper in the subsequent etching process such as ion beam etching (IBE) or reactive ion etching (ME).

(47) As shown in FIG. 9, an ion beam etching (IBE) or reactive ion etching (ME) process is carried out to etch the composite cap layer 240, the free layer 230, the tunnel barrier layer 220, the reference layer 210, the seed layer SE, and the spacer layer SP, thereby forming a cylindrical memory structure C. According to some embodiments, an upper portion of the ILD layer 13 may be etched away, thereby forming a tapered top surface profile.

(48) As shown in FIG. 10, an encapsulation layer 260 is conformally deposited on the cylindrical memory structure C and on the ILD layer 13. According to one embodiment, the encapsulation layer 260 may be a silicon nitride (SiN) layer, but is not limited thereto. The encapsulation layer 260, which protects the sidewalls of the cylindrical memory structure C, may be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD) methods, but is not limited thereto. Subsequently, an ILD layer 310 is deposited on the encapsulation layer 260. According to one embodiment, the ILD layer 310 may comprise SiN, SiCN, SiCNO or ULK materials known in the art.

(49) As shown in FIG. 11, according to one embodiment, the ILD layer 310 and the encapsulation layer 260 may be subjected to a CMP process to form a planarized surface. An etching back process is then performed to etch the remaining ILD layer 310 and the encapsulation layer 260 until the hard mask layer HM is exposed for further connection to a top copper interconnect.

(50) As shown in FIG. 12, an ILD layer 312 is deposited on the encapsulation layer 260, the ILD layer 310 and the hard mask layer HM. According to one embodiment, the ILD layer 310 may comprise SiN, SiCN, SiCNO or ULK materials known in the art.

(51) As shown in FIG. 13, a copper damascene process may be performed to form a damascened copper interconnect 15 directly on the hard mask layer HM. According to one embodiment, the damascened copper interconnect 15 is in direct contact with the hard mask layer HM. According to one embodiment, the damascened copper interconnect 15 is in direct contact with the encapsulation layer 260. According to one embodiment, the damascened copper interconnect 15 is in direct contact with the ILD layer 310. According to one embodiment, the damascened copper interconnect 15 may be electrically connected to a bit line (not shown).

(52) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.