Integrated security device and signal processing method used for an integrated security device

Abstract

An integrated security device, including: an encryption/decoding processing unit for executing processing necessary for authentication by using a logic circuit that forms an encryption/decoding function; a selector for selecting signals whose number corresponds to a specific number of lines from among signals from a plurality of intermediate nodes of the logic circuit in accordance with a selection signal; and a signal processing unit having a function of detecting a glitch caused by the signals corresponding to the specific number of lines, for implementing both a function of generating a physical random number and a function of generating a device identifier by a physical characteristic based on the glitch detected by switch-selecting the signals corresponding to the specific number of lines.

Claims

1. An integrated security device, comprising: an encryption/decoding processing circuit configured to execute processing necessary for authentication by using a logic circuit that forms an encryption/decoding function; a selection circuit configured to select signals whose number corresponds to a specific number of lines from among signals from a plurality of intermediate nodes of the logic circuit in accordance with a selection signal; and a signal processing circuit configured to supply the selection circuit with the selection signal for selectively executing a function of generating a physical random number or a function of generating a physical unclonable function (PUF) response, detect a glitch caused by the signals corresponding to the specific number of lines selected by the selection circuit in accordance with the selection signal, and execute the function of generating the physical random number and the function of generating the PUF response based on the glitch detected in accordance with the signals corresponding to the specific number of lines selected based on the selection signal.

2. The integrated security device according to claim 1, wherein: the encryption/decoding function is formed of iterative processing of sub-functions; and the signal processing circuit is configured to acquire input information necessary for the function of generating the PUF response by selecting the signals corresponding to the specific number of lines from among signals updated by the iterative processing by supplying the selection circuit with the selection signal.

3. The integrated security device according to claim 1, further comprising a key generator configured to protect a key necessary for the authentication by the PUF response generated by the signal processing circuit, and to generate challenge data necessary for the authentication by the generated physical random number, wherein the encryption/decoding processing circuit is further configured to acquire the key and the challenge data from the key generator, and to process an authentication protocol by performing encryption/decoding processing necessary for the authentication.

4. The integrated security device according to claim 2, further comprising a key generator configured to protect a key necessary for the authentication by the PUF response generated by the signal processing circuit, and to generate challenge data necessary for the authentication by the generated physical random number, wherein the encryption/decoding processing circuit is further configured to acquire the key and the challenge data from the key generator, and to process an authentication protocol by performing encryption/decoding processing necessary for the authentication.

5. The integrated security device according to claim 1, wherein: the encryption/decoding processing circuit comprises a divided sub-function for executing processing in units divided by N, where N represents an integer equal to or greater than two, as one given sub-function that forms the encryption/decoding function; the selection circuit comprises a switching circuit configured to feed back an output from an n-th division of the divided sub-function to an input to (n+1)th division of the divided sub-function, where n represents an integer equal to or greater than one and equal to or smaller than (N−1), in accordance with the selection signal; and the signal processing circuit is configured to output the selection signal that corresponds to forming the switching circuit for feeding back when implementing the function of generating the physical random number, and to output the selection signal that corresponds to avoiding forming the switching circuit for feeding back when implementing the function of generating the PUF response.

6. The integrated security device according to claim 2, wherein: the encryption/decoding processing circuit comprises a divided sub-function for executing processing in units divided by N, where N represents an integer equal to or greater than two, as one given sub-function that forms the encryption/decoding function; the selection circuit comprises a switching circuit configured to feed back an output from an n-th division of the divided sub-function to an input to (n+1)th division of the divided sub-function, where n represents an integer equal to or greater than one and equal to or smaller than (N−1), in accordance with the selection signal; and the signal processing circuit is configured to output the selection signal that corresponds to forming the switching circuit for feeding back when implementing the function of generating the physical random number, and to output the selection signal that corresponds to avoiding forming the switching circuit for feeding back when implementing the function of generating the PUF response.

7. The integrated security device according to claim 3, wherein: the encryption/decoding processing circuit comprises a divided sub-function for executing processing in units divided by N, where N represents an integer equal to or greater than two, as one given sub-function that forms the encryption/decoding function; the selection circuit comprises a switching circuit configured to feed back an output from an n-th division of the divided sub-function to an input to (n+1)th division of the divided sub-function, where n represents an integer equal to or greater than one and equal to or smaller than (N−1), in accordance with the selection signal; and the signal processing circuit is configured to output the selection signal that corresponds to forming the switching circuit for feeding back when implementing the function of generating the physical random number, and to output the selection signal that corresponds to avoiding forming the switching circuit for feeding back when implementing the function of generating the PUF response.

8. The integrated security device according to claim 4, wherein: the encryption/decoding processing circuit comprises a divided sub-function for executing processing in units divided by N, where N represents an integer equal to or greater than two, as one given sub-function that forms the encryption/decoding function; the selection circuit comprises a switching circuit configured to feed back an output from an n-th division of the divided sub-function to an input to (n+1)th division of the divided sub-function, where n represents an integer equal to or greater than one and equal to or smaller than (N−1), in accordance with the selection signal; and the signal processing circuit is configured to output the selection signal that corresponds to forming the switching circuit for feeding back when implementing the function of generating the physical random number, and to output the selection signal that corresponds to avoiding forming the switching circuit for feeding back when implementing the function of generating the PUF response.

9. The integrated security device according to claim 1, wherein the signal processing circuit is further configured to perform processing for generating the physical random number based on a transition state in repeatedly reading a signal having a predetermined bit transition probability a predetermined number of times via the selection circuit.

10. The integrated security device according to claim 2, wherein the signal processing circuit is further configured to perform processing for generating the physical random number based on a transition state in repeatedly reading a signal having a predetermined bit transition probability a predetermined number of times via the selection circuit.

11. The integrated security device according to claim 3, wherein the signal processing circuit is further configured to perform processing for generating the physical random number based on a transition state in repeatedly reading a signal having a predetermined bit transition probability a predetermined number of times via the selection circuit.

12. The integrated security device according to claim 4, wherein the signal processing circuit is further configured to perform processing for generating the physical random number based on a transition state in repeatedly reading a signal having a predetermined bit transition probability a predetermined number of times via the selection circuit.

13. The integrated security device according to claim 1, wherein: the encryption/decoding function is formed of a plurality of logic stages, the encryption/decoding function comprising at least a first sub-function that forms a logic circuit on a first stage and a second sub-function that forms a logic circuit on a second stage; and the signal processing circuit is configured to supply the selection circuit with the selection signal that corresponds to selecting an output signal from the first sub-function when implementing the function of generating the PUF response, and to supply the selection circuit with the selection signal that corresponds to selecting an output signal from the second sub-function when implementing the function of generating the physical random number.

14. The integrated security device according to claim 2, wherein: the encryption/decoding function is formed of a plurality of logic stages, the encryption/decoding function comprising at least a first sub-function that forms a logic circuit on a first stage and a second sub-function that forms a logic circuit on a second stage; and the signal processing circuit is configured to supply the selection circuit with the selection signal that corresponds to selecting an output signal from the first sub-function when implementing the function of generating the PUF response, and to supply the selection circuit with the selection signal that corresponds to selecting an output signal from the second sub-function when implementing the function of generating the physical random number.

15. The integrated security device according to claim 3, wherein: the encryption/decoding function is formed of a plurality of logic stages, the encryption/decoding function comprising at least a first sub-function that forms a logic circuit on a first stage and a second sub-function that forms a logic circuit on a second stage; and the signal processing circuit is configured to supply the selection circuit with the selection signal that corresponds to selecting an output signal from the first sub-function when implementing the function of generating the PUF response, and to supply the selection circuit with the selection signal that corresponds to selecting an output signal from the second sub-function when implementing the function of generating the physical random number.

16. The integrated security device according to claim 4, wherein: the encryption/decoding function is formed of a plurality of logic stages, the encryption/decoding function comprising at least a first sub-function that forms a logic circuit on a first stage and a second sub-function that forms a logic circuit on a second stage; and the signal processing circuit is configured to supply the selection circuit with the selection signal that corresponds to selecting an output signal from the first sub-function when implementing the function of generating the PUF response, and to supply the selection circuit with the selection signal that corresponds to selecting an output signal from the second sub-function when implementing the function of generating the physical random number.

17. A signal processing method for an integrated security device, comprising: an encryption/decoding processing of executing processing necessary for authentication by using a logic circuit that forms an encryption/decoding function; supplying a selection circuit with a selection signal for selectively executing a function of generating a physical random number or a function of generating a physical unclonable function (PUF) response; selecting, by the selection circuit, signals whose number corresponds to a specific number of lines from among signals from a plurality of intermediate nodes of the logic circuit in accordance with the selection signal; detecting a glitch caused by the selected signals corresponding to the specific number of lines selected by the selection circuit in accordance with the selection signal; and executing the function of generating the physical random number and the function of generating the PUF response based on the glitch detected in accordance with the signals corresponding to the specific number of lines selected based on the selection signal.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a block diagram of a security device obtained by integrating a function of PUF, a function for random number generation, and a function of encryption according to a first embodiment of the present invention.

(2) FIG. 2 is a block diagram of a security device obtained by integrating a function of PUF, a function for random number generation, and a function of encryption according to a second embodiment of the present invention.

(3) FIG. 3 is a block diagram of a security device obtained by integrating a function of PUF, a function for random number generation, and a function of encryption according to a third embodiment of the present invention.

(4) FIG. 4 is a model of a binary symmetric channel according to the third embodiment of the present invention.

(5) FIG. 5 is a block diagram of a security device obtained by integrating a function of PUF, a function for random number generation, and a function of encryption according to a fourth embodiment of the present invention.

(6) FIG. 6 is a block diagram of a security device obtained by integrating a function of PUF, a function for random number generation, and a function of encryption according to a fifth embodiment of the present invention.

(7) FIG. 7 is a block diagram illustrating a configuration in which a function of a fuzzy extractor is added to FIG. 6 according to the fifth embodiment of the present invention and a key generation function using the PUF is added thereto.

(8) FIG. 8 is a hardware architecture for implementing the authentication function according to the fifth embodiment of the present invention.

(9) FIG. 9 is an example of a logic circuit for describing a principle of a glitch PUF.

(10) FIG. 10 is an exemplary configuration diagram of a GPUF circuit.

DESCRIPTION OF EMBODIMENTS

(11) Now, an integrated security device and a signal processing method to be used for an integrated security device according to preferred embodiments of the present invention are described with reference to the accompanying drawings.

(12) First, a fuzzy extractor and a glitch PUF serving as technical premises are described before descriptions are made of the embodiments of the present invention.

Description of the Fuzzy Extractor

(13) In general, it is difficult to use a response of the PUF as a key to be used for cryptography as it is. This is because it is difficult to guarantee that the response of the PUF includes no error every time and that the responses follow a uniform distribution. Therefore, normally, the fuzzy extractor (hereinafter referred to as “FE”) is used to perform key generation. Some versions exist for a method of forming the FE, and in the present application, a description is made of a configuration formed based on code offset.

(14) As an algorithm 1 and an algorithm 2, pieces of processing of the FE formed based on the code offset are collectively shown below in Table 1 and Table 2, respectively.

(15) TABLE-US-00001 TABLE 1 algorithm 1: key generation processing Gen performed by FE Setting: (n,k,2t + 1) error correction code C , general-purpose hash function h.sub.A Input: (l.Math.n)-bit PUF response W = (w.sub.1,w.sub.2,...,w.sub.l). Output: (K,S) ← Gen(W) , u-bit key K , (l.Math.n)-bit auxiliary data S = (s.sub.1,s.sub.2,...,s.sub.l) 1: i = 1 to l do 2:   generate k-bit random number r.sub.i 3:   c.sub.i ← Encode.sub.C(r.sub.i) 4:   s.sub.i ← w.sub.i ⊕ c.sub.i 5: end for 6:  K ← h.sub.A(w.sub.1,w.sub.2,...,w.sub.l) 7: return K,S

(16) TABLE-US-00002 TABLE 2 algorithm 2: key reproduction processing Rep performed by FE Setting: (n,k,2t + 1) error correction code C , general-purpose hash function h.sub.A Input: ( l.Math.n )-bit PUF response W′ = (w′.sub.1,w′.sub.2,...,w′.sub.l) ,( l.Math.n )-bit auxiliary data S = (s.sub.1,s.sub.2,...,s.sub.l). Output: K ← Rep(W′,S) , u-bit key K . 1: i = 1 to l do 2:   c′.sub.i ← w′.sub.i ⊕ s.sub.i 3:   c.sub.i ← Decode.sub.C(c′.sub.i) 4:   w.sub.i ← c.sub.i ⊕ s.sub.i 5: end for 6:  K ← h.sub.A(w.sub.1,w.sub.2,...,w.sub.l) 7: return K,S

(17) The algorithm 1 is processing for generating a key corresponding to an initial key for the FE, and the algorithm 2 is processing for reproducing a key for generating the same bit string as the initial key.

(18) Encode.sub.C and Decode.sub.C within the algorithm 1 and the algorithm 2, respectively, represent encoding processing and correction processing within an error correction code C. An agreement between the generated key and the reproduced key is guaranteed by the following expression (1) in terms of a Hamming distance of a PUF response within the algorithm 1 and the algorithm 2.
[Math. 1]
∀iε{1, . . . ,l},dis.sub.Ham(w.sub.i,w′.sub.i)≦t  (1)

(19) Further, assuming that an information amount between chips held by a k-bit PUF output is k′, the following expression (2) is an appropriate design parameter.
[Math. 2]
l=┌u/k′┐  (2)

Description of the Glitch PUF

(20) The glitch PUF (hereinafter referred to as “GPUF”) is one method of forming a PUF that uses a phenomenon called “glitch” caused by a relationship in delay between input/output signals of respective gates forming a logic circuit.

(21) FIG. 9 is an example of a logic circuit for describing a principle of the glitch PUF, and exemplifies a case where the logic circuit is formed of an AND circuit 91 and an XOR circuit 92. Now, a simple logic circuit illustrated in FIG. 9 is used to describe the principal of the glitch PUF. In such a circuit as illustrated in FIG. 9 for performing logical operations of the AND circuit 91, the XOR circuit 92, and the like for a plurality of input signals, transient signal transitions called “glitch” generally occur due to differences in delay among the respective signals.

(22) In FIG. 9, when input signals (x1, x2, and x3) all change from “0” to “1”, a glitch having a protrusion shape first occurs in an output from the XOR circuit 92 due to a time difference between the changes of the signals x1 and x2. Then, when the change of the signal x3 reaches the AND circuit 91 earlier than the above-mentioned glitch, the above-mentioned glitch propagates to an output from the AND circuit 91 (see the waveforms shown on the left side of FIG. 9). In contrast, when the change of x3 reaches the AND circuit 91 later than the above-mentioned glitch, the above-mentioned glitch does not propagate to the output from the AND circuit 91 (see the waveforms shown on the right side of FIG. 9).

(23) In addition, even in a case where x3 is earlier, depending on a transistor characteristic of the AND circuit 91, a glitch having a short width may fail to propagate to the output. However, when a glitch is limited to the one having a sufficiently long width, a glitch shape thereof is determined by a relative relationship in delay in the same manner as in a case of a delay-PUF such as an arbiter-PUF, and it is expected that the shape is maintained even when an operating environment changes.

(24) A method of forming the GPUF is indicated in Non Patent Literature 1. Here, as an algorithm 3 and an algorithm 4, descriptions obtained by converting an operation of the GPUF into pseudo codes are shown below as Table 3 and Table 4, respectively.

(25) TABLE-US-00003 TABLE 3 algorithm 3: operation of GPUF performed in key generation processing Setting: parity b.sub.i = G2R.sub.f(x′.sub.i .fwdarw. x.sub.i) of rising edge in each output signal that occurs depending on state transition x′.sub.i .fwdarw. x.sub.i of input signal relative to random logic f with m-bit input and n-bit output n-bit data b.sub.i = (b.sub.i,1,b.sub.i,2,...,b.sub.i,n).sub.2 . Input: (l.Math.m)-bit data X = (x.sub.1,x.sub.2,...,x.sub.l) , repeat count cnt.sub.re , stability determination threshold value th.sub.err . Output: (W,S.sub.mask) ← GPUF.sub.Gen(X,cnt.sub.re,th.sub.err) , ( l.Math.n )-bit PUF response W = (w.sub.1,w.sub.2,...,w.sub.l), (l.Math.n)-bit auxiliary data S.sub.mask = (s.sub.1,s.sub.2,...,s.sub.l). 1:  i = 1 to l do 2:    cnt[1 : n] ← all0 3:    j = 1 to cnt.sub.re do 4:      b.sub.i = G2R.sub.f(x′.sub.i .fwdarw. x.sub.i) 5:      k = 1 to n do 6:        cnt[k] ← cnt[k] + b.sub.i,k 7:      end for 8:    end for 9:    j = 1 to n do 10:     if(cnt[j] ≦ th.sub.err) then 11:       w.sub.i,j ← 0,s.sub.i,j ← 1 12:     else if(cnt.sub.re−1-th.sub.err ≦ cnt[j]) 13:       w.sub.i,j ← 1,s.sub.i,j ← 1 14:     else 15:       s.sub.i,j ← 0 16:     end if 17:   end for 18: end for 19: return W,S.sub.mask ;

(26) TABLE-US-00004 TABLE 4 algorithm 4: operation of GPUF performed in key reproduction processing Setting: parity b.sub.i = G2R.sub.f(x′.sub.i .fwdarw. x.sub.i) of rising edge in each output signal that occurs depending on state transition x′.sub.i .fwdarw. x.sub.i of input signal relative to random logic f with m-bit input and n-bit output n-bit data b.sub.i = (b.sub.i,1,b.sub.i,2,...,b.sub.i,n).sub.2 . Input: (l.Math.m)-bit data X = (x.sub.1,x.sub.2,...,x.sub.l) , (l.Math.n)-bit auxiliary data S.sub.mask = (s.sub.1,s.sub.2,...,s.sub.l) , repeat count cnt.sub.re . Output: W ← GPUF.sub.Rep(X,S.sub.mask,cnt.sub.re) , (l.Math.n)-bit PUF response W = (w.sub.1,w.sub.2,...,w.sub.l) . 1:  i = 1 to l do 2:    cnt[1 : n] ← all0 3:    j = 1 to cnt.sub.re do 4:      b.sub.i = G2R.sub.f(x′.sub.i .fwdarw. x.sub.i) 5:      k = 1 to n do 6:        cnt[k] ← cnt[k] + b.sub.i,k 7:      end for 8:    end for 9:    j = 1 to n do 10:     if(cnt[j] < cnt.sub.re / 2) then 11:       w.sub.i,j ← 0 12:     else 13:       w.sub.i,j ← 1 14:     end if 15:   end for 16:   w.sub.i ← w.sub.i ∩ s.sub.i 17: end for 19: return W ;

(27) The algorithm 3 represents the operation of the GPUF performed at a time of key generation processing. At the time of key generation processing, in order to lower an error rate of the PUF response, processing for determining whether an edge for the same input state transition has an even or odd number a plurality of times and examining whether or not an output therefrom is stable is performed. Specifically, iterative processing is performed the number of times defined by a repeat count cnt.sub.re.

(28) After that, processing for performing an examination relating to stability of a bit with a stability determination threshold value th.sub.err, used as a requirement for each output bit and handling a bit that does not satisfy the requirement as “0” at times of the key generation and key reproduction by setting a bit value of auxiliary data S.sub.mask corresponding to the bit to “0” is performed.

(29) In contrast thereto, in the operation of the glitch PUF at a time of key reproduction processing indicated in the algorithm 4, the iterative processing is carried out in the same manner as at the time of the generation except that the final response is determined by majority decision and mask processing using S.sub.mask.

(30) FIG. 10 is an exemplary configuration diagram of a GPUF circuit. In FIG. 10, an “input register” 101 is a register for storing x′.sub.i and x.sub.i within the algorithms 3 and 4. Further, in FIG. 10, a “random logic f” 102 is a combinational circuit for processing a random logic f within the algorithms 3 and 4.

(31) Further, in FIG. 10, a “glitch count register” 103 is a flip-flop (FF) using a signal for determining whether a rising edge has an even or odd number as a clock. This FF is reset by a “clear” signal illustrated in FIG. 10 immediately before performing determination processing.

(32) Further, in FIG. 10, an “output register” 104 is a register for storing again a determination result b.sub.i of whether the rising edge stored in the “glitch count register” 103 has an even or odd number.

(33) In addition, in FIG. 10, a “counter & comparator” 105 includes registers 105a for managing the number of occurrences of 0 and 1 of each bit based on the determination result b.sub.i, and performs calculation of a PUF response w.sub.ii and auxiliary data s.sup.m.sub.ii in accordance with an occurrence function.

(34) Now, for the sake of a better understanding, an operation illustrated in FIG. 10 is described by taking a specific example.

(35) It is assumed that the “input register” 101 illustrated in FIG. 10 is an 8-bit register and that 0x00 being held is changed to 0x55. This operation corresponds to within the algorithms 3 and 4.

(36) At this time, there is a change in an input to the “random logic f” 102 serving as the combinational circuit, which also causes a change in an output therefrom. The output is subjected to a behavior having different presence/absence of a pulse, as described above with reference to FIG. 9, for each LSI due to variations in circuit delays of the “random logic f” 102.

(37) Here, assuming that cnt.sub.re=7 and th.sub.err=0, the input change of 0x00.fwdarw.0x55 is executed seven times. In the algorithm 3, when all the pulses generated in accordance with the input change 0x00.fwdarw.0x55 for the seven times have the same parity, s.sub.ii←1 is established. On the other hand, when the parities of the pulses differ even once, s.sub.ii←0 is established. Further, w.sub.ii←0 is established when the pulses have even numbers all seven times, while w.sub.ii←1 is established when the pulses have odd numbers all seven times.

(38) The above-mentioned determination is processed by the “counter & comparator” 105 illustrated in FIG. 10. For example, in the algorithm 3, when “1” is determined all seven times, “1, 1, 1” is stored in a 3-bit counter of the “counter & comparator” 105. Therefore, an AND result for each of the bits is “1”, and s.sub.ii←1 is established.

(39) Further, when “0” is determined all seven times, “0, 0, 0” is stored in the 3-bit counter. Therefore, a NAND result thereof is “1”, and s.sub.ii←1 is established. When the parities of the pulses differ even once, a 3-bit register does not exhibit all the same values, and hence s.sub.ii←0 is established.

(40) Further, in the algorithm 4, when the response corresponding to the same input change for the seven times is “1” four or more times, w.sub.ii←1 is established, while w.sub.ii←0 is established when the response is “0” four or more times. In any one of the cases, a determination function can be implemented by outputting an MSB of the counter.

(41) As described above, in the algorithm 3, when the input change returns as stable outputs as to have the same response all seven times, s.sub.ii←1 is established, and otherwise s.sub.ii←0 is established. Further, in the algorithm 4, the majority decision is performed for the response corresponding to the input change determined to return the stable response in the algorithm 3, thereby determining the response.

(42) The stability of the response of the GPUF, namely, an error probability of the response bit, depends on a circuit configuration of the “random logic f” 102. This bit error rate tends to rise as the number of logic stages becomes larger. For example, there is such dependency that the error probability is 1% with a given number of logic stages while the error probability becomes 10% as the number of logic stages increases.

(43) With consideration given to the descriptions made above relating to the fuzzy extractor and the glitch PUF serving as technical premises, the embodiments of the present invention are described below with reference to the accompanying drawings.

First Embodiment

(44) FIG. 1 is a block diagram of a security device obtained by integrating a function of PUF, a function for random number generation, and a function of encryption according to a first embodiment of the present invention. An encrypter/decoder 11 is a circuit block for performing normal encryption/decoding processing. Further, signals are output from a plurality of intermediate nodes of a logic circuit forming the encrypter/decoder 11 to the outside of the circuit block.

(45) A selector 12 selects signals whose number corresponds to a specific number of lines from among the signals output from the encrypter/decoder 11 through the plurality of intermediate nodes. In addition, a glitch detector 13 performs glitch detection for the signals selected by the selector 12, to output a detection result thereof.

(46) Note that, a path changing signal input to the encrypter/decoder 11 is a signal for switching the circuit through which data processed by the encrypter/decoder 11 is to pass. Further, the intermediate node selected by the selector 12 is switched based on a value of an intermediate node selection signal input to the selector 12.

(47) In this manner, by using the intermediate node selection signal, it is possible to switch between a signal from the intermediate node for performing the glitch detection when operating as the PUF and a signal from the intermediate node for performing the glitch detection when operating as a physical random number, which allows the same glitch detector 13 to be used.

Second Embodiment

(48) In a second embodiment of the present invention, a description is made of an aspect in which the configuration illustrated in FIG. 1 according to the above-mentioned first embodiment is made more concrete. FIG. 2 is a block diagram of a security device obtained by integrating a function of PUF, a function for random number generation, and a function of encryption according to the second embodiment of the present invention.

(49) A counter 21 determines the stability of the result of the glitch detection performed by the glitch detector 13 as described above. At this time, the stability is determined by using a most significant bit of the counter 21. For example, in a case of the majority decision, frequencies of “0” and “1” can be determined by the MSB. Further, in this second embodiment, a least significant bit of the counter 21 is used for a random number.

(50) The response of the PUF serves as an input to a key generator 22 in accordance with the algorithms 1 and 2. A first selector 23 selects one of a plurality of signals, which are read as an output from the key generator 22, in accordance with a key selection signal from the outside, and outputs the selected one to the encrypter/decoder 11. In this manner, the first selector 23 can supply the encrypter/decoder 11 with a device identifier generated by a physical characteristic.

(51) On the other hand, a random number output corresponding to an output of the least significant bit of the counter 21 is read into a second selector 24. Then, the second selector 24 selects any one of plaintext/ciphertext inputs from the outside in accordance with a plaintext selection signal from the outside, and outputs the selected one to the encrypter/decoder 11 along with the random number output read from the counter 21.

(52) As a result, the encrypter/decoder 11 can process an encryption function based on the device identifier generated by the physical characteristic and on the random number.

Third Embodiment

(53) FIG. 3 is a block diagram of a security device obtained by integrating a function of PUF, a function for random number generation, and a function of encryption according to a third embodiment of the present invention. First, a description is made of an encryption function Enc. Note that, here, for the sake of simplicity in description, secret information K used in the encryption function is omitted.

(54) A general encryption function is formed of iteration of sub-functions. For example, in the example of FIG. 3, the processing of the encryption function Enc is defined by the iterative processing of a sub-function f 32 and a sub-function g 33. In other words, assuming that a repeat count is n, processing of:
H.sub.1=g(f(P));
is performed for a plaintext P stored in an “input register” 31 within FIG. 3, and a value of the “input register” 31 is updated to H1.

(55) In the same manner, processing of:
H.sub.2=g(f(H.sub.1));
is performed, and after such processing is repeated n times,
C.fwdarw.H.sub.n=g(f(H.sub.n-1));
stored in the “input register” 31 is set as a ciphertext C, to finish the processing of the encryption function.

(56) At this time, in the third embodiment, signal lines of the sub-function f 32 and the sub-function g 33 are drawn from a circuit path for performing the processing of the encryption function Enc, and a selector 34 that allows each of the signal lines to be selected is provided. At this time, an output from the sub-function f 32 is selected to operate the function of PUF, while the signal line of the sub-function g 33 is selected to operate a function of a physical random number generator.

(57) In other words, the signal line whose number of logic stages are determined only by the sub-function f 32 is handled as a random logic of the PUF, while a composite function g.Math.f having a larger number of logic stages is handled as a random logic used for the physical random number generator.

(58) When FIG. 3 operates as the PUF, the “input register” 31 that stores the plaintext and an intermediate value H.sub.i in the encryption processing functions in the same manner as the “input register” 101 described above with reference to FIG. 10. Further, the sub-function f 32 illustrated in FIG. 3 functions in the same manner as the “random logic f” 102 described above with reference to FIG. 10.

(59) In the subsequent part, the implementation methods of carrying out FIG. 10 and FIG. 3 agree with each other. In other words, a “PUF/RNG logic” 35 illustrated in FIG. 3 is formed of the “glitch count register” 103, the “output register” 104, and the “counter & comparator” 105 described above with reference to FIG. 10.

(60) The respective inputs X=(x1, x2, . . . , and x1) within the algorithms 3 and 4 are updated by setting, as the next inputs, the ciphertext C obtained by encryption using the plaintext P and a key K or the intermediate value H.sub.i thereof.

(61) As an algorithm 5, an operation as the physical random number generator within FIG. 3 is shown below as Table 5.

(62) TABLE-US-00005 TABLE 5 algorithm 5: physical random number generation performed by GPUF Setting: parity b.sub.i = G2R.sub.f(x′.sub.i .fwdarw. x.sub.i) of rising edge in each output signal that occurs depending on state transition x′.sub.i .fwdarw. x.sub.i of input signal relative to random logic f with m-bit input and n-bit output n-bit data b.sub.i = (b.sub.i,1,b.sub.i,2,...,b.sub.i,n).sub.2 . Input: m-bit data x′,x, repeat count cnt.sub.re . Output: r ← GPUF(x,cnt.sub.re) , n-bit random number r = (r.sub.1,r.sub.2,...,r.sub.n).sub.2 . 1:  i = 1 to cnt.sub.re do 4:    b.sub.i = G2R.sub.f(x′ .fwdarw. x) 5:    j = 1 to n do 6:      cnt[j] ← cnt[j] + b.sub.i,j 7:    end for 8:  end for 9:  i = 1 to n do 10:   r.sub.i ← cnt[i] mod 2 11 end for 19: return r ;

(63) To summarize the algorithm 5, a limitation is imposed on the state transition of the input signal within the algorithm 3 or the algorithm 4, the operation of the GPUF is performed, and as the subsequent response, processing for outputting an LSB of the counter is performed instead of the majority decision. Accordingly, the algorithm 5 can be implemented only by adding the function of outputting signals to the circuits for performing the processing of the algorithm 3 and the algorithm 4.

(64) Further, FIG. 4 is a model of a binary symmetric channel according to the third embodiment of the present invention. Assuming the binary symmetric channel illustrated in FIG. 4 as a model (namely, model in which a probability of transition from “0” to “1” or “1” to “0” is represented by p and a probability of transition from “0” to “0” or “1” to “1” is represented by 1−p), a bit inversion probability within the algorithm 5 is represented by the following expression (3).

(65) $\begin{array}{cc}\left[\mathrm{Math}.3\right]& \\ \underset{k=0}{\overset{.Math.{\mathrm{cnt}}_{\mathrm{re}}\text{/}2.Math.}{.Math.}}\left(\begin{array}{c}{\mathrm{cnt}}_{\mathrm{re}}\\ 2k+1\end{array}\right){p^{2k+1}\left(1-p\right)}^{{\mathrm{cnt}}_{\mathrm{re}}-\left(2k+1\right)}.& \left(3\right)\end{array}$

(66) When cnt.sub.re is large, the above-mentioned expression (3) converges to 0.5 even with p that is small. For example, when cnt.sub.re=255, the above-mentioned calculation result is 0.49999992976191 with p=0.03, and sufficient random number property (randomness) can be obtained.

(67) It is a point of FIG. 3 that a random logic that operates as the PUF and a random logic that operates as the physical random number generator are each implemented by using the circuits (corresponding to the sub-functions f and g) initially implemented for the processing of the encryption function Enc and are switched depending on how large the numbers of logic stages of the respective random logics are. In addition, the point resides in that an input update of the PUF is scheduled by the encryption function.

Fourth Embodiment

(68) The above-mentioned third embodiment is configured so that the sub-function f and the sub-function g of the encryption function Enc are used as the random logic of the PUF and the physical random number generator as they are. However, when the numbers of logic stages of the sub-function f and the sub-function g are small, it is conceivable that a sufficient bit error rate cannot be obtained and that the random number property becomes insufficient in spite of the encryption function Enc functioning as the PUF.

(69) Therefore, in a fourth embodiment of the present invention, a description is made of a configuration for aiming at performing an operation for obtaining appropriate random number property by adding a small-scale circuit to the circuit configuration of the encryption function Enc.

(70) FIG. 5 is a block diagram of a security device obtained by integrating a function of PUF, a function for random number generation, and a function of encryption according to the fourth embodiment of the present invention. In this configuration illustrated in FIG. 5, it is assumed that the sub-function f of the encryption function Enc is processing performed in given divided units. For example, in a case of a block cipher, substitution processing such as S-box corresponds to this processing.

(71) At this time, as illustrated in FIG. 5, AND and XOR gates are used to provide a path for feeding back an output from a given sub-function f52 to an input to a different sub-function f52. In this case, assuming that the input signal of the AND gate is “0”, FIG. 5 is equivalent to an arithmetic operation necessary for the encryption function Enc. On the other hand, assuming that the input signal of the AND gate is “1”, FIG. 5 is equivalent to an arithmetic operation necessary for physical random number generation, and a circuit path having the number of logic stages corresponding to two stages of the sub-function f is formed.

(72) With this configuration, even when the initially provided encryption function Enc has a small number of logic stages, it is possible to increase the number of logic stages while maintaining a functionality of the original encryption function.

Fifth Embodiment

(73) In a fifth embodiment of the present invention, a description is made of a configuration obtained by making the above-mentioned fourth embodiment more concrete. FIG. 6 is a block diagram of a security device obtained by integrating a function of PUF, a function for random number generation, and a function of encryption according to the fifth embodiment of the present invention. In the fifth embodiment, a configuration that assumes the AES of the U.S. standard cryptography as the encryption function Enc is employed.

(74) In FIG. 6, a part surrounded by the dotted line on the left side indicates “basic modules for the AES” 61 serving as the circuit initially necessary to implement a function of the AES, while a part surrounded by the dash-dot line on the right side indicates “additional modules for PUF & RNG” 62 serving as the circuit to be added for the PUF and the random number generation. A basic operation is the same as that of FIG. 2 described above, and it is possible to switch between the operations of the AES and the PUF and the function of the random number generation by switching “0” and “1” of the input to the AND gate of the logic indicated as “chain logic” in FIG. 6.

(75) FIG. 7 is a block diagram illustrating a configuration in which a function of a fuzzy extractor is added to the configuration of FIG. 6 according to the fifth embodiment of the present invention and a key generation function using the PUF is added thereto. By the configuration illustrated in FIG. 7, the following three functions required for an authentication protocol are all implemented.

(76) <Function 1> Holding the secret information K securely within each device.

(77) <Function 2> Generating a random number C.

(78) <Function 3> Processing the encryption function Enc.

(79) Note that, this operation illustrated in FIG. 7 follows the algorithms 1 and 2.

(80) Next, a description is made of an operation of the authentication protocol using the module of this embodiment.

(81) (Operation 1) In accordance with the algorithm 4, the module of this embodiment performs the operation as the PUF, and the “additional modules for PUF & RNG” 62 generate a response w of the PUF.

(82) (Operation 2) In accordance with the algorithm 2, a key K.sub.PUF is generated by an “encoder/decoder” 71 and a “hash” 72 from the response w of the PUF and auxiliary data S and S.sub.mask, and is loaded into the “basic modules for AES” 61 serving as an AES circuit of the module of this embodiment.

(83) (Operation 3) The “basic modules for AES” 61 load data D=Enc(K, K.sub.PUF) obtained by encrypting an authentication key K stored in a non-secure area with the key K.sub.PUF into the module of this embodiment as the ciphertext, and decode the data D into the authentication key K with K=Dec(D, K.sub.PUF), and load the authentication key into the module of this embodiment as a key.

(84) (Operation 4) The “basic modules for AES” 61 load the data D=Enc(K, K.sub.PUF) obtained by encrypting the authentication key K stored in the non-secure area with the key K.sub.PUF into the module of this embodiment as the ciphertext, decode the data D into the authentication key K with K=Dec(D, K.sub.PUF), and load the authentication key into the module of this embodiment as a key.

(85) (Operation 5) The “additional modules for PUF & RNG” 62 perform the random number generation in the module of this embodiment, and output a generated random number R to the outside so as to be transmitted to an authentication destination.

(86) (Operation 6) The “basic modules for AES” 61 perform encryption C=Enc(R, K) for the random number R.

(87) (Operation 7) The “basic modules for AES” 61 compare data C′ received from the authentication destination with C, and determine that the authentication is successful when there is a match therebetween, while the authentication is unsuccessful when there is a mismatch therebetween.

(88) FIG. 8 is a hardware architecture for implementing the authentication function according to the first to fifth embodiments of the present invention. As illustrated in FIG. 8, a security device 801 according to the present invention uses any one of the integrated security devices described in the respective embodiments as an integrated module 808. Further, the integrated module 808 is connected to a CPU 802, memories 803 and 804, and an I/O 805 via a local bus 807. In addition, this integrated module 808 is connected to an HF 810 via an FEC 809. The integrated security device according to the present invention can be embodied as such a hardware configuration illustrated in FIG. 8.

(89) Note that, the present invention is not limited to the above-mentioned first to fifth embodiments. In other words, the present invention can be carried out by changing a component without departing from the gist thereof. Further, various inventions can be formed by appropriately combining the plurality of components disclosed in the above-mentioned first to fifth embodiments. In addition, some components may be deleted from all the components illustrated in the first to fifth embodiments. In addition, the components may be combined appropriately over different embodiments.