Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer form

Abstract

A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.

Claims

1. A method of making a semiconductor device, comprising: providing a reconstituted panel including a plurality of semiconductor die; disposing the reconstituted panel over a substrate; bonding the semiconductor die to the substrate; depositing an encapsulant around the semiconductor die after bonding the semiconductor die to the substrate; and singulating the substrate after bonding the semiconductor die to the substrate.

2. The method of claim 1, further including forming an interconnect structure over the semiconductor die, wherein bonding the semiconductor die to the substrate further includes bonding the interconnect structure to the substrate.

3. The method of claim 2, wherein the interconnect structure includes a stud bump.

4. The method of claim 1, further including depositing the encapsulant between the semiconductor die and substrate.

5. A method of making a semiconductor device, comprising: providing a reconstituted panel by, providing a carrier, singulating a plurality of semiconductor die from a semiconductor wafer, and disposing the semiconductor die over the carrier after singulating the semiconductor die; forming a first interconnect structure over the semiconductor die while the semiconductor die are disposed over the carrier; and disposing the reconstituted panel over a substrate.

6. The method of claim 5, further including bonding the first interconnect structure to the substrate while the semiconductor die are disposed over the carrier.

7. The method of claim 5, further including bonding the first interconnect structure to the substrate using thermocompression.

8. The method of claim 5, further including depositing an insulating material between the semiconductor die and substrate.

9. A semiconductor device, comprising: a substrate; a reconstituted panel including a plurality of semiconductor die disposed side-by-side over the substrate; a first interconnect structure bonded between the substrate and the semiconductor die; and a second interconnect structure formed over the substrate opposite the semiconductor die; a third interconnect structure formed over the substrate with the first interconnect structure bonded to the third interconnect structure.

10. The semiconductor device of claim 9, wherein the first interconnect structure includes a stud bump and the second interconnect structure includes a bump.

11. The semiconductor device of claim 9, wherein the reconstituted panel further includes a carrier, wherein the plurality of semiconductor die are disposed on the carrier.

12. The semiconductor device of claim 9, wherein the substrate includes a printed circuit board.

13. The semiconductor device of claim 9, further including an encapsulant or an underfill material deposited between the plurality of semiconductor die and the substrate.

14. The method of claim 1, further including bonding the semiconductor die to the substrate metallurgically.

15. The method of claim 3, further including forming a conductive bump on the substrate opposite the semiconductor die.

16. The method of claim 8, further including depositing the insulating material extending between two adjacent semiconductor die.

17. A method of making a semiconductor device, comprising: providing a plurality of semiconductor die; disposing the semiconductor die on a carrier; disposing the semiconductor die and carrier over a substrate; depositing an encapsulant over the semiconductor die between the substrate and carrier; and singulating the substrate after depositing the encapsulant.

18. The method of claim 17, further including bonding the semiconductor die to the substrate using a first interconnect structure.

19. The method of claim 18, wherein the first interconnect structure includes a stud bump.

20. The method of claim 18, further including depositing the encapsulant between the substrate and semiconductor die around the first interconnect structure.

21. The method of claim 18, further including forming a second interconnect structure over the substrate opposite the semiconductor die.

22. The method of claim 21, wherein the first interconnect structure includes a stud bump and the second interconnect structure includes a solder bump.

23. The method of claim 17, wherein the substrate includes a printed circuit board (PCB).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates a printed circuit board (PCB) with different types of packages mounted to a surface of the PCB;

(2) FIGS. 2a-2c illustrate further detail of the representative semiconductor packages mounted to the PCB;

(3) FIGS. 3a-3c illustrate a semiconductor wafer with a plurality of semiconductor die separated by a saw street;

(4) FIGS. 4a-4n illustrate a process of bonding a semiconductor die to a substrate while in reconstituted wafer form with the die attached to the carrier;

(5) FIG. 5 illustrates a flipchip semiconductor package after singulation from the reconstituted wafer of FIGS. 4a-4n;

(6) FIGS. 6a-6b illustrate a mold underfill of the semiconductor die and substrate while in reconstituted wafer form with the die attached to the carrier;

(7) FIG. 7 illustrates a flipchip semiconductor package after singulation from the reconstituted wafer of FIGS. 6a-6b;

(8) FIGS. 8a-8b illustrate another mold underfill of the semiconductor die and substrate while in reconstituted wafer form with the die attached to the carrier; and

(9) FIG. 9 illustrates a flipchip semiconductor package after singulation from the reconstituted wafer of FIGS. 8a-8b.

DETAILED DESCRIPTION OF THE DRAWINGS

(10) The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.

(11) Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions.

(12) Passive and active components are formed over the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the electrical conductivity of semiconductor material in active devices by dynamically changing the semiconductor material conductivity in response to an electric field or base current. Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of the electric field or base current.

(13) Active and passive components are formed by layers of materials with different electrical properties. The layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition can involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components.

(14) Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and then packaging the semiconductor die for structural support and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with solder bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.

(15) FIG. 1 illustrates electronic device 50 having a chip carrier substrate or printed circuit board (PCB) 52 with a plurality of semiconductor packages mounted on its surface. Electronic device 50 can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown in FIG. 1 for purposes of illustration.

(16) Electronic device 50 can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device 50 can be a subcomponent of a larger system. For example, electronic device 50 can be part of a cellular phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device. Alternatively, electronic device 50 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, radio frequency (RF) circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the products to be accepted by the market. The distance between semiconductor devices may be decreased to achieve higher density.

(17) In FIG. 1, PCB 52 provides a general substrate for structural support and electrical interconnect of the semiconductor packages mounted on the PCB. Conductive signal traces 54 are formed over a surface or within layers of PCB 52 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces 54 provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces 54 also provide power and ground connections to each of the semiconductor packages.

(18) In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate carrier. Second level packaging involves mechanically and electrically attaching the intermediate carrier to the PCB. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB.

(19) For the purpose of illustration, several types of first level packaging, including bond wire package 56 and flipchip 58, are shown on PCB 52. Additionally, several types of second level packaging, including ball grid array (BGA) 60, bump chip carrier (BCC) 62, dual in-line package (DIP) 64, land grid array (LGA) 66, multi-chip module (MCM) 68, quad flat non-leaded package (QFN) 70, and quad flat package 72, are shown mounted on PCB 52. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB 52. In some embodiments, electronic device 50 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

(20) FIGS. 2a-2c show exemplary semiconductor packages. FIG. 2a illustrates further detail of DIP 64 mounted on PCB 52. Semiconductor die 74 includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and are electrically interconnected according to the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of semiconductor die 74. Contact pads 76 are one or more layers of conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within semiconductor die 74. During assembly of DIP 64, semiconductor die 74 is mounted to an intermediate carrier 78 using a gold-silicon eutectic layer or adhesive material such as thermal epoxy or epoxy resin. The package body includes an insulative packaging material such as polymer or ceramic. Conductor leads 80 and bond wires 82 provide electrical interconnect between semiconductor die 74 and PCB 52. Encapsulant 84 is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating semiconductor die 74 or bond wires 82.

(21) FIG. 2b illustrates further detail of BCC 62 mounted on PCB 52. Semiconductor die 88 is mounted over carrier 90 using an underfill or epoxy-resin adhesive material 92. Bond wires 94 provide first level packaging interconnect between contact pads 96 and 98. Molding compound or encapsulant 100 is deposited over semiconductor die 88 and bond wires 94 to provide physical support and electrical isolation for the device. Contact pads 102 are formed over a surface of PCB 52 using a suitable metal deposition process such as electrolytic plating or electroless plating to prevent oxidation. Contact pads 102 are electrically connected to one or more conductive signal traces 54 in PCB 52. Bumps 104 are formed between contact pads 98 of BCC 62 and contact pads 102 of PCB 52.

(22) In FIG. 2c, semiconductor die 58 is mounted face down to intermediate carrier 106 with a flipchip style first level packaging. Active region 108 of semiconductor die 58 contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed according to the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements within active region 108. Semiconductor die 58 is electrically and mechanically connected to carrier 106 through bumps 110.

(23) BGA 60 is electrically and mechanically connected to PCB 52 with a BGA style second level packaging using bumps 112. Semiconductor die 58 is electrically connected to conductive signal traces 54 in PCB 52 through bumps 110, signal lines 114, and bumps 112. A molding compound or encapsulant 116 is deposited over semiconductor die 58 and carrier 106 to provide physical support and electrical isolation for the device. The flipchip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die 58 to conduction tracks on PCB 52 in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die 58 can be mechanically and electrically connected directly to PCB 52 using flipchip style first level packaging without intermediate carrier 106.

(24) FIG. 3a shows a semiconductor wafer 120 with a base substrate material 122, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support. A plurality of semiconductor die or components 124 is formed on wafer 120 separated by a non-active, inter-die wafer area or saw street 126 as described above. Saw street 126 provides cutting areas to singulate semiconductor wafer 120 into individual semiconductor die 124. In one embodiment, semiconductor wafer 120 has a width or diameter of 200-300 millimeters (mm). In another embodiment, semiconductor wafer 120 has a width or diameter of 100-450 mm.

(25) FIG. 3b shows a cross-sectional view of a portion of semiconductor wafer 120. Each semiconductor die 124 has a back or non-active surface 128 and active surface 130 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 130 to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit. Semiconductor die 124 may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing. In one embodiment, semiconductor die 124 is a flipchip type semiconductor die.

(26) An electrically conductive layer 132 is formed over active surface 130 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 132 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 132 operates as contact pads electrically connected to the circuits on active surface 130. Conductive layer 132 can be formed as contact pads disposed side-by-side a first distance from the edge of semiconductor die 124, as shown in FIG. 3b. Alternatively, conductive layer 132 can be formed as contact pads that are offset in multiple rows such that a first row of contact pads is disposed a first distance from the edge of the die, and a second row of contact pads alternating with the first row is disposed a second distance from the edge of the die.

(27) An insulating or passivation layer 134 is formed over active surface 130 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. The insulating layer 134 contains one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or other material having similar insulating and structural properties. Alternatively, insulating layer 134 can be formed before conductive layer 132. A portion of insulating layer 134 would be removed by an etching process or laser direct ablation (LDA) to expose active surface 130 and form conductive layer 132.

(28) Semiconductor wafer 120 undergoes electrical testing and inspection as part of a quality control process. Manual visual inspection and automated optical systems are used to perform inspections on semiconductor wafer 120. Software can be used in the automated optical analysis of semiconductor wafer 120. Visual inspection methods may employ equipment such as a scanning electron microscope, high-intensity or ultra-violet light, or metallurgical microscope. Semiconductor wafer 120 is inspected for structural characteristics including warpage, thickness variation, surface particulates, irregularities, cracks, delamination, and discoloration.

(29) The active and passive components within semiconductor die 124 undergo testing at the wafer level for electrical performance and circuit function. Each semiconductor die 124 is tested for functionality and electrical parameters using a probe or other testing device. A probe is used to make electrical contact with nodes or contact pads 132 on each semiconductor die 124 and provides electrical stimuli to the contact pads. Semiconductor die 124 responds to the electrical stimuli, which is measured and compared to an expected response to test functionality of the semiconductor die. The electrical tests may include circuit functionality, lead integrity, resistivity, continuity, reliability, junction depth, electro-static discharge (ESD), radio frequency (RF) performance, drive current, threshold current, leakage current, and operational parameters specific to the component type. The inspection and electrical testing of semiconductor wafer 120 enables semiconductor die 124 that pass to be designated as known good die (KGD) for use in a semiconductor package.

(30) In FIG. 3c, semiconductor wafer 120 is singulated through saw street 126 using a saw blade or laser cutting tool 136 into individual semiconductor die 124. The individual semiconductor die 124 can be inspected and electrically tested for identification of KGD post singulation.

(31) FIGS. 4a-4n illustrate, in relation to FIGS. 1 and 2a-2c, a process of bonding a semiconductor die to a substrate while the die is attached to a carrier. FIG. 4a shows a cross-sectional view of a portion of a carrier or temporary substrate 140. In one embodiment, carrier 140 is a tape. A carrier frame 142 is positioned over carrier 140 and secured to the carrier with an adhesive layer. Carrier 140 and/or carrier frame 142 contain sacrificial base material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost, rigid material for structural support. Carrier frame 142 includes openings 144 for alignment and placement of semiconductor die 124 over carrier 140.

(32) In FIG. 4b, semiconductor die 124 from FIG. 3c are mounted within openings 144 of carrier frame 142 to carrier 140 using, for example, a pick and place operation with back surface 128 oriented toward the carrier. FIG. 4c shows semiconductor die 124 mounted within openings 144 of carrier frame 142 to carrier 140 with an adhesive layer as reconstituted or reconfigured wafer 146. FIG. 4d shows a plan view of semiconductor die 124 mounted within openings 144 of carrier frame 142 to carrier 140 as reconstituted wafer 146.

(33) In another embodiment, FIG. 4e shows a cross-sectional view of a portion of a carrier frame 150. A carrier tape 152 is formed over carrier frame 150. Carrier frame 150 and/or carrier tape 152 contain sacrificial base material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost, rigid material for structural support.

(34) In FIG. 4f, semiconductor die 124 from FIG. 3c are mounted over carrier tape 152 and carrier frame 150 using, for example, a pick and place operation with back surface 128 oriented toward the carrier tape. FIG. 4g shows semiconductor die 124 mounted to carrier tape 152 and carrier frame 150 with an adhesive layer as reconstituted or reconfigured wafer 156. FIG. 4h shows a plan view of semiconductor die 124 mounted to carrier tape 152 and carrier frame 150 as reconstituted wafer 156.

(35) Carrier structures 140-142 and 150-152 can be a round or rectangular panel (greater than 300 mm) with capacity for multiple semiconductor die 124. Carriers 140-142 and 150-152 may have a larger surface area than the surface area of semiconductor wafer 120. A larger carrier reduces the manufacturing cost of the semiconductor package as more semiconductor die can be processed on the larger carrier thereby reducing the cost per unit. Semiconductor packaging and processing equipment are designed and configured for the size of the wafer or carrier being processed.

(36) To further reduce manufacturing costs, the size of carriers 140-142 and 150-152 is selected independent of the size of semiconductor die 124 or size of semiconductor wafer 120. That is, carriers 140-142 and 150-152 have a fixed or standardized size, which can accommodate various size semiconductor die 124 singulated from one or more semiconductor wafers 120. In one embodiment, carriers 140-142 and 150-152 are circular with a diameter of 330 mm. In another embodiment, carriers 140-142 and 150-152 are rectangular with a width of 560 mm and length of 600 mm. Semiconductor die 124 may have dimensions of 10 mm by 10 mm, which are placed on the standardized carrier 140-142 or 150-152. Alternatively, semiconductor die 124 may have dimensions of 20 mm by 20 mm, which are placed on the same standardized carrier 140-142 or 150-152. Accordingly, standardized carrier 140-142 or 150-152 can handle any size semiconductor die 124, which allows subsequent semiconductor processing equipment to be standardized to a common carrier, i.e., independent of die size or incoming wafer size. Semiconductor packaging equipment can be designed and configured for the standard carrier using a common set of processing tools, equipment, and bill of materials to process any semiconductor die size from any incoming wafer size. The common or standardized carrier 140-142 or 150-152 lowers manufacturing costs and capital risk by reducing or eliminating the need for specialized semiconductor processing lines based on die size or incoming wafer size. By selecting a predetermined carrier size to use for any size semiconductor die from all semiconductor wafer, a flexible manufacturing line can be implemented.

(37) Reconstituted wafers 146 and 156 can be processed into many types of semiconductor packages, including flipchip packages, embedded wafer level ball grid array (eWLB), fan-in wafer level chip scale packages (WLCSP), reconstituted or embedded wafer level chip scale packages (eWLCSP), fan-out WLCSP, three dimensional (3D) packages, such as package-on-package (PoP), or other semiconductor packages. Reconstituted wafers 146 and 156 are configured according to the specifications of the resulting semiconductor package. In one embodiment, semiconductor die 124 are placed on carrier 140-142 or 150-152 in a high-density arrangement, i.e., 300 micrometers (μm) apart or less, for processing fan-in devices. In another embodiment, semiconductor die 124 are separated by a distance of 50 μm on carrier 140-142 or 150-152. The distance between semiconductor die 124 on carrier 140-142 or 150-152 is optimized for manufacturing the semiconductor packages at the lowest unit cost. The larger surface area of carrier 140-142 or 150-152 accommodates more semiconductor die 124 and lowers manufacturing cost as more semiconductor die 124 are processed per reconstituted wafer 146 or 156. The number of semiconductor die 124 mounted to carrier 140-142 or 150-152 can be greater than the number of semiconductor die 124 singulated from semiconductor wafer 120. Carriers 140-142 and 150-152 and reconstituted wafers 146 and 156 provide the flexibility to manufacture many different types of semiconductor packages using different size semiconductor die 124 from different sized semiconductor wafers 120.

(38) The remaining discussion is directed to reconstituted wafer 146 containing semiconductor die 124 mounted to carrier 140 and carrier frame 142, although the same principles apply to reconstituted wafer 156 containing semiconductor die 124 mounted to carrier frame 150 and carrier tape 152. Continuing from FIG. 4c, a plurality of electrical interconnects or stud bumps 160 are formed over conductive layer 132 of semiconductor die 124 while in reconstituted wafer form with the semiconductor die attached to carrier 140 and carrier frame 142, as shown in FIG. 4i. Stud bumps 160 include a base portion 160a and stem portion 160b. Conductive material 164, such as Au, Ag, Cu, Al, or alloy thereof, is dispensed or extruded from applicator 162 to form stud bumps 160. Stud bumps 160 are trimmed, cut, planarized, or otherwise leveled to a desired uniform height, such as 10-100 μm. FIG. 4j shows a plan view of stud bumps 160 formed over conductive layer 132 of semiconductor die 124 disposed within openings 144 of carrier frame 142 over carrier 140.

(39) FIG. 4k shows substrate or PCB 170 containing insulating material 172 and conductive layers 174. In one embodiment, substrate 170 contains one or more laminated layers of prepreg, FR-4, FR-1, CEM-1, or CEM-3 with a combination of phenolic cotton paper, epoxy, resin, woven glass, matte glass, polyester, and other reinforcement fibers or fabrics. Substrate 170 can also be a multi-layer flexible laminate, ceramic, copper foil, glass, or semiconductor wafer including an active surface containing one or more transistors, diodes, and other circuit elements to implement analog circuits or digital circuits. The insulating material 172 may contain one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, hafnium oxide (HfO2), benzocyclobutene (BCB), polyimide (PI), polybenzoxazoles (PBO), polymer, or other dielectric material having similar structural and insulating properties. Conductive layers 174 contain Al, Cu, Sn, Ni, Au, Ag, Ti, W, or other suitable electrically conductive material formed using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating. Conductive layers 174 include lateral redistribution layers (RDL) and vertical conductive vias to provide electrical interconnect through substrate 170. Portions of conductive layers 174 are electrically common or electrically isolated according to the design and function of the semiconductor die 124 mounted to substrate 170.

(40) An electrically conductive bump material is deposited over conductive layer 174 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 174 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 176. In some applications, bumps 176 are reflowed a second time to improve electrical contact to conductive layer 174. Bumps 176 can also be compression bonded or thermocompression bonded to conductive layer 174. Bumps 176 represent one type of interconnect structure that can be formed over conductive layer 174. The interconnect structure can also use conductive paste, stud bump, micro bump, or other electrical interconnect.

(41) Heat tip 180 is mounted to carrier 140 and carrier frame 142 of reconstituted wafer 146 for bonding of stud bumps 160 to bumps 176 of substrate 170. Reconstituted wafer 146 is positioned over substrate 170 with stud bumps 160 aligned to bumps 176. Stud bumps 160 are brought into contact with bumps 176 to form an electrical and metallurgical union using gang reflow or thermocompression bonding with the aid of heat tip 180. Heat tip 180 applies a force F under an elevated temperature for the reflow or thermocompression bonding of stud bumps 160 to bumps 176. FIG. 4l shows stud bumps 160 electrically and metallurgically bonded to bumps 176. The bonding of stud bumps 160 of semiconductor die 124 to bumps 176 of substrate 170 is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to carrier 140 and carrier frame 142 (or carrier frame 150 and carrier tape 152) to provide a high throughput of the flipchip type interconnect to the substrate.

(42) In FIG. 4m, heat tip 180 is removed, as well as carrier 140 and carrier frame 142, by chemical etching, mechanical peeling, chemical mechanical planarization (CMP), mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping to expose back surface 128 of semiconductor die 124.

(43) In FIG. 4n, an underfill material 182, such as epoxy resin, is deposited between semiconductor die 124 and substrate 170. Underfill material 182 can be deposited by a capillary underfill process. Alternatively, a non-conductive paste or non-conductive film can be applied to substrate 170 prior to attaching semiconductor die 124. Bumps 184 are formed over conductive layer 174 on a surface of substrate 170 opposite semiconductor die 124. Semiconductor die 124 are singulated through substrate 170 with saw blade or laser cutting tool 186 into individual flipchip packages 188.

(44) FIG. 5 shows flipchip package 188 after singulation. Semiconductor die 124 is electrically connected through stud bumps 160 and bumps 176 to conductive layer 174 and bumps 184 of substrate 170 for external interconnect. The bonding of stud bumps 160 of semiconductor die 124 to bumps 176 of substrate 170 is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to carrier 140 and carrier frame 142 (or carrier frame 150 and carrier tape 152) to provide a high throughput of the flipchip type interconnect to the substrate. The flipchip package 188 may undergo inspection and electrical testing before or after singulation.

(45) In another embodiment, continuing from FIG. 4m, semiconductor die 124 and substrate 170 are placed in chase mold 190, as shown in FIG. 6a. Chase mold 190 includes an upper mold support 192 and lower mold support 194. Upper mold support 192 has a cavity for containing semiconductor die 124, substrate 170, and encapsulant or molding compound. Semiconductor die 124 and substrate 170 are placed over lower mold support 194 with a surface of the substrate, opposite the semiconductor die, contacting the lower mold support. The upper mold support 192 and lower mold support 194 are brought together to close chase mold 190. A volume of encapsulant or molding compound 196 is injected under an elevated temperature and pressure through inlet 198 to cover semiconductor die 124 and substrate 170. Encapsulant 196 can be a polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. In particular, encapsulant 196 covers the four side surfaces, back surface 128 of semiconductor die 124, and an area between the semiconductor die and substrate. The volume of encapsulant 196 is measured according to the space requirements of the chase mold cavity less the area occupied by semiconductor die 124 and substrate 170. Encapsulant 196 is evenly dispersed and uniformly distributed under an elevated temperature within chase mold 190 around and between semiconductor die 124 and substrate 170. In one embodiment, the molding temperature ranges from 80-150° C. with a molding time of 250-1000 seconds. The molding cure temperature ranges from 100-180° C. with a molding cure time of 20-120 minutes. Encapsulant 196 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.

(46) In FIG. 6b, semiconductor die 124 and substrate 170 are removed from chase mold 190. Bumps 200 are formed over conductive layer 174 on a surface of substrate 170 opposite semiconductor die 124. Semiconductor die 124 are singulated through substrate 170 with saw blade or laser cutting tool 202 into individual flipchip packages 204.

(47) FIG. 7 shows flipchip package 204 after singulation. Semiconductor die 124 is electrically connected through stud bumps 160 and bumps 176 to conductive layer 174 and bumps 200 of substrate 170 for external interconnect. The bonding of stud bumps 160 of semiconductor die 124 to bumps 176 of substrate 170 is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to carrier 140 and carrier frame 142 (or carrier frame 150 and carrier tape 152) to provide a high throughput of the flipchip type interconnect to the substrate. The flipchip package 204 may undergo inspection and electrical testing before or after singulation.

(48) In another embodiment, continuing from FIG. 4m, semiconductor die 124 and substrate 170 are placed in chase mold 210, as shown in FIG. 8a. Chase mold 210 includes an upper mold support 212 and lower mold support 214. Upper mold support 212 has a cavity for containing semiconductor die 124, substrate 170, and encapsulant or molding compound. Semiconductor die 124 and substrate 170 are placed over lower mold support 214 with a surface of the substrate, opposite the semiconductor die, contacting the lower mold support. The upper mold support 212 and lower mold support 214 are brought together to close chase mold 210. Back surface 128 of semiconductor die 124 contacts sealing layer 217 of upper mold support 212 to block formation of encapsulant 216 over the back surface of the semiconductor die. A volume of encapsulant or molding compound 216 is injected under an elevated temperature and pressure through inlet 218 to cover semiconductor die 124 and substrate 170. Encapsulant 216 can be a polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. In particular, encapsulant 216 covers the four side surfaces of semiconductor die 124, as well as between the semiconductor die and substrate. Back surface 128 remains devoid of encapsulant 216. The volume of encapsulant 216 is measured according to the space requirements of the chase mold cavity less the area occupied by semiconductor die 124 and substrate 170. Encapsulant 216 is evenly dispersed and uniformly distributed under an elevated temperature within chase mold 210 around semiconductor die 124. In one embodiment, the molding temperature ranges from 80-150° C. with a molding time of 250-1000 seconds. The molding cure temperature ranges from 100-180° C. with a molding cure time of 20-120 minutes. Encapsulant 216 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.

(49) In FIG. 8b, semiconductor die 124 and substrate 170 are removed from chase mold 210. Bumps 220 are formed over conductive layer 174 on a surface of substrate 170 opposite semiconductor die 124. Semiconductor die 124 are singulated through substrate 170 with saw blade or laser cutting tool 222 into individual flipchip packages 224.

(50) FIG. 9 shows flipchip package 224 after singulation. Semiconductor die 124 is electrically connected through stud bumps 160 and bumps 176 to conductive layer 174 and bumps 220 of substrate 170 for external interconnect. The bonding of stud bumps 160 of semiconductor die 124 to bumps 176 of substrate 170 is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to carrier 140 and carrier frame 142 (or carrier frame 150 and carrier tape 152) to provide a high throughput of the flipchip type interconnect to the substrate. The flipchip package 224 may undergo inspection and electrical testing before or after singulation.

(51) While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.